diff options
| author | Bryan O'Donoghue <bodonoghue@codehermit.ie> | 2008-02-03 23:21:29 +0000 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2008-02-05 23:33:22 -0600 |
| commit | 03bbfe8b97eb277f1af27fef5a14224f7878a983 (patch) | |
| tree | fa9710df6d0b0ee982dce3a0c68c4e2fff1cba43 /arch/powerpc/boot | |
| parent | 5cfade1829440af45cd24ea7483d2e16876fc602 (diff) | |
[POWERPC] 8xx: Add clock-frequency to adder875 and mpc885ads dts
cpm_uart_core has a dependency on fsl,cpm-brg/clock-frequency, this
means that a .dts that uses the cpm uart driver needs to supply a
clock-frequency entry for get_brgfreq to return a meaningful number.
Signed-off-by: Bryan O'Donoghue <bodonoghue@codehermit.ie>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot')
| -rw-r--r-- | arch/powerpc/boot/dts/adder875-redboot.dts | 1 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/adder875-uboot.dts | 1 | ||||
| -rw-r--r-- | arch/powerpc/boot/dts/mpc885ads.dts | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/adder875-redboot.dts b/arch/powerpc/boot/dts/adder875-redboot.dts index 930bfb3894e..28e9cd3d7a2 100644 --- a/arch/powerpc/boot/dts/adder875-redboot.dts +++ b/arch/powerpc/boot/dts/adder875-redboot.dts @@ -151,6 +151,7 @@ compatible = "fsl,mpc875-brg", "fsl,cpm1-brg", "fsl,cpm-brg"; + clock-frequency = <50000000>; reg = <0x9f0 0x10>; }; diff --git a/arch/powerpc/boot/dts/adder875-uboot.dts b/arch/powerpc/boot/dts/adder875-uboot.dts index 0197242dacf..54fb60ec03e 100644 --- a/arch/powerpc/boot/dts/adder875-uboot.dts +++ b/arch/powerpc/boot/dts/adder875-uboot.dts @@ -150,6 +150,7 @@ compatible = "fsl,mpc875-brg", "fsl,cpm1-brg", "fsl,cpm-brg"; + clock-frequency = <50000000>; reg = <0x9f0 0x10>; }; diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts index 8848e637293..d84a012c2aa 100644 --- a/arch/powerpc/boot/dts/mpc885ads.dts +++ b/arch/powerpc/boot/dts/mpc885ads.dts @@ -166,6 +166,7 @@ compatible = "fsl,mpc885-brg", "fsl,cpm1-brg", "fsl,cpm-brg"; + clock-frequency = <0>; reg = <9f0 10>; }; |