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| author | Ingo Molnar <mingo@elte.hu> | 2009-03-30 23:53:32 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-03-30 23:53:32 +0200 |
| commit | 65fb0d23fcddd8697c871047b700c78817bdaa43 (patch) | |
| tree | 119e6e5f276622c4c862f6c9b6d795264ba1603a /arch/powerpc/include/asm/reg_booke.h | |
| parent | 8c083f081d0014057901c68a0a3e0f8ca7ac8d23 (diff) | |
| parent | dfbbe89e197a77f2c8046a51c74e33e35f878080 (diff) | |
Merge branch 'linus' into cpumask-for-linus
Conflicts:
arch/x86/kernel/cpu/common.c
Diffstat (limited to 'arch/powerpc/include/asm/reg_booke.h')
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 67453766bff..a56f4d61aa7 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -10,6 +10,7 @@ #define __ASM_POWERPC_REG_BOOKE_H__ /* Machine State Register (MSR) Fields */ +#define MSR_GS (1<<28) /* Guest state */ #define MSR_UCLE (1<<26) /* User-mode cache lock enable */ #define MSR_SPE (1<<25) /* Enable SPE */ #define MSR_DWE (1<<10) /* Debug Wait Enable */ @@ -110,6 +111,7 @@ #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ #define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */ +#define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */ #define SPRN_PIT 0x3DB /* Programmable Interval Timer */ #define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */ #define SPRN_L2CSR0 0x3F9 /* L2 Data Cache Control and Status Register 0 */ |