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author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-19 17:40:40 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-06-19 17:40:40 -0700 |
commit | 773d7a09e1a1349a5319ac8665e9c612c6aa27d8 (patch) | |
tree | 3b2272bb3cfcab04ba6459cba116e577278c9392 /arch/powerpc/include/asm/reg_booke.h | |
parent | 17fad5209e6b55148dbd20156cdaf2c7e67faa40 (diff) | |
parent | b71a107c66ad952c9d35ec046a803efc89a80556 (diff) |
Merge branch 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (35 commits)
powerpc/5121: make clock debug output more readable
powerpc/5xxx: Add common mpc5xxx_get_bus_frequency() function
powerpc/5200: Update pcm030.dts to add i2c eeprom and delete cruft
powerpc/5200: convert mpc52xx_psc_spi to use cs_control callback
fbdev/xilinxfb: Fix improper casting and tighen up probe path
usb/ps3: Add missing annotations
powerpc: Add memory clobber to mtspr()
powerpc: Fix invalid construct in our CPU selection Kconfig
ps3rom: Use ps3_system_bus_[gs]et_drvdata() instead of direct access
powerpc: Add configurable -Werror for arch/powerpc
of_serial: Add UPF_FIXED_TYPE flag
drivers/hvc: Add missing __devexit_p()
net/ps3: gelic - Add missing annotations
powerpc: Introduce macro spin_event_timeout()
powerpc/warp: Fix ISA_DMA_THRESHOLD default
powerpc/bootwrapper: Custom build options for XPedite52xx targets
powerpc/85xx: Add defconfig for X-ES MPC85xx boards
powerpc/85xx: Add dts files for X-ES MPC85xx boards
powerpc/85xx: Add platform support for X-ES MPC85xx boards
83xx: add support for the kmeter1 board.
...
Diffstat (limited to 'arch/powerpc/include/asm/reg_booke.h')
-rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 601ddbc4600..6bcf364cbb2 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -389,12 +389,14 @@ #define ICCR_CACHE 1 /* Cacheable */ /* Bit definitions for L1CSR0. */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ /* Bit definitions for L1CSR1. */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ |