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| author | Ingo Molnar <mingo@elte.hu> | 2008-10-12 11:32:17 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-10-12 11:32:17 +0200 |
| commit | 206855c321adee56db3946ca09a5887cddb9d598 (patch) | |
| tree | 13a2729d4d0e37170552bd9ad3c6bba71ba0c55c /arch/powerpc/include/asm | |
| parent | e8d3f455de4f42d4bab2f6f1aeb2cf3bd18eb508 (diff) | |
| parent | cb58ffc3889f0545628f138f849e759a331b8ddc (diff) | |
Merge branch 'x86/urgent' into core/signal
Conflicts:
arch/x86/kernel/signal_64.c
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/dcr-regs.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h index 29b0ecef980..f15296cf359 100644 --- a/arch/powerpc/include/asm/dcr-regs.h +++ b/arch/powerpc/include/asm/dcr-regs.h @@ -68,6 +68,10 @@ #define SDR0_UART3 0x0123 #define SDR0_CUST0 0x4000 +/* SDRs (460EX/460GT) */ +#define SDR0_ETH_CFG 0x4103 +#define SDR0_ETH_CFG_ECS 0x00000100 /* EMAC int clk source */ + /* * All those DCR register addresses are offsets from the base address * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is |