diff options
| author | Kumar Gala <galak@kernel.crashing.org> | 2012-01-05 12:37:16 -0600 |
|---|---|---|
| committer | galak <galak@spiff.(none)> | 2012-03-15 12:12:19 -0500 |
| commit | f0b8b3417d836f89d873f6d5de43d54f02cb11e2 (patch) | |
| tree | 754f4a23cddc0d216c343e584b6d43195224545b /arch/powerpc/include | |
| parent | cb41fa024e0cc306472c1c08c93758263724d0e8 (diff) | |
powerpc/fsl-booke: Fixup calc_cam_sz to support MMU v2
The registers that describe size supported by TLB are different on MMU
v2 as well as we support power of two page sizes. For now we continue
to assume that FSL variable size array supports all page sizes up to the
maximum one reported in TLB1PS.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/include')
| -rw-r--r-- | arch/powerpc/include/asm/reg_booke.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h index 500fe1dc43e..8a97aa7289d 100644 --- a/arch/powerpc/include/asm/reg_booke.h +++ b/arch/powerpc/include/asm/reg_booke.h @@ -62,6 +62,7 @@ #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */ #define SPRN_TLB0PS 0x158 /* TLB 0 Page Size Register */ +#define SPRN_TLB1PS 0x159 /* TLB 1 Page Size Register */ #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */ #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */ #define SPRN_EPTCFG 0x15e /* Embedded Page Table Config */ |