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authorKumar Gala <galak@kernel.crashing.org>2008-10-28 18:01:39 +0000
committerPaul Mackerras <paulus@samba.org>2008-10-31 16:13:50 +1100
commit3c10c9c45e290022ca7d2aa1ad33a0b6ed767520 (patch)
tree002769098cd2b53aad995acac3c42f0331302588 /arch/powerpc/include
parentf9226d572d2f8b5f564596db8c6a13e458c46191 (diff)
powerpc/mpic: Fix regression caused by change of default IRQ affinity
The Freescale implementation of MPIC only allows a single CPU destination for non-IPI interrupts. We add a flag to the mpic_init to distinquish these variants of MPIC. We pull in the irq_choose_cpu from sparc64 to select a single CPU as the destination of the interrupt. This is to deal with the fact that the default smp affinity was changed by commit 18404756765c713a0be4eb1082920c04822ce588 ("genirq: Expose default irq affinity mask (take 3)") to be all CPUs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/include')
-rw-r--r--arch/powerpc/include/asm/mpic.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index 34d9ac433ac..c2ccca53b99 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -355,6 +355,8 @@ struct mpic
#define MPIC_NO_BIAS 0x00000400
/* Ignore NIRQS as reported by FRR */
#define MPIC_BROKEN_FRR_NIRQS 0x00000800
+/* Destination only supports a single CPU at a time */
+#define MPIC_SINGLE_DEST_CPU 0x00001000
/* MPIC HW modification ID */
#define MPIC_REGSET_MASK 0xf0000000