diff options
| author | David S. Miller <davem@davemloft.net> | 2011-04-11 13:44:25 -0700 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-04-11 13:44:25 -0700 |
| commit | 1c01a80cfec6f806246f31ff2680cd3639b30e67 (patch) | |
| tree | 0b554aad2ec1da71ecf6339d4ba51617bfe1dc3c /arch/powerpc/oprofile/op_model_cell.c | |
| parent | c44d79950b2daa1025e62eede73e4e4a274d1ef3 (diff) | |
| parent | 4a9f65f6304a00f6473e83b19c1e83caa1e42530 (diff) | |
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts:
drivers/net/smsc911x.c
Diffstat (limited to 'arch/powerpc/oprofile/op_model_cell.c')
| -rw-r--r-- | arch/powerpc/oprofile/op_model_cell.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/oprofile/op_model_cell.c b/arch/powerpc/oprofile/op_model_cell.c index c4d2b716756..cb515cff745 100644 --- a/arch/powerpc/oprofile/op_model_cell.c +++ b/arch/powerpc/oprofile/op_model_cell.c @@ -67,7 +67,7 @@ #define MAX_SPU_COUNT 0xFFFFFF /* maximum 24 bit LFSR value */ -/* Minumum HW interval timer setting to send value to trace buffer is 10 cycle. +/* Minimum HW interval timer setting to send value to trace buffer is 10 cycle. * To configure counter to send value every N cycles set counter to * 2^32 - 1 - N. */ @@ -1470,7 +1470,7 @@ static int cell_global_start(struct op_counter_config *ctr) * trace buffer at the maximum rate possible. The trace buffer is configured * to store the PCs, wrapping when it is full. The performance counter is * initialized to the max hardware count minus the number of events, N, between - * samples. Once the N events have occured, a HW counter overflow occurs + * samples. Once the N events have occurred, a HW counter overflow occurs * causing the generation of a HW counter interrupt which also stops the * writing of the SPU PC values to the trace buffer. Hence the last PC * written to the trace buffer is the SPU PC that we want. Unfortunately, @@ -1656,7 +1656,7 @@ static void cell_handle_interrupt_ppu(struct pt_regs *regs, * The counters were frozen by the interrupt. * Reenable the interrupt and restart the counters. * If there was a race between the interrupt handler and - * the virtual counter routine. The virutal counter + * the virtual counter routine. The virtual counter * routine may have cleared the interrupts. Hence must * use the virt_cntr_inter_mask to re-enable the interrupts. */ |