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authorMilton Miller <miltonm@bga.com>2007-12-14 15:52:09 +1100
committerPaul Mackerras <paulus@samba.org>2007-12-20 16:15:34 +1100
commitd7cf0edb8f7d53bfc8b5e40893415d48656c0399 (patch)
treeb868deafc979c1e93b0aa17ec22c0be268e66e7d /arch/powerpc/platforms/pseries/xics.h
parent7e1961ff4954d6ab627d9b606785afdcd0dda84b (diff)
[POWERPC] Push down or eliminate smp_processor_id calls in xics code
The per-processor interrupt request register and current processor priority register are only accessed on the current cpu. In fact the hypervisor doesn't even let us choose which cpu's registers to access. The only function to use cpu twice is xics_migrate_irqs_away, not a fast path. But we can cache the result of get_hard_processor_id() instead of calling get_hard_smp_processor_id(cpu) in a loop across the call to rtas. Years ago the irq code passed smp_processor_id into get_irq, I thought we might initialize the CPPR third party at boot as an extra measure of saftey, and it made the code symmetric with the qirr (queued interrupt for software generated interrupts), but now it is just extra and sometimes unneeded work to pass it down. Signed-off-by: Milton Miller <miltonm@bga.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/platforms/pseries/xics.h')
-rw-r--r--arch/powerpc/platforms/pseries/xics.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/pseries/xics.h b/arch/powerpc/platforms/pseries/xics.h
index db0ec3ba3ae..9ffd809d29e 100644
--- a/arch/powerpc/platforms/pseries/xics.h
+++ b/arch/powerpc/platforms/pseries/xics.h
@@ -21,9 +21,6 @@ extern void xics_cause_IPI(int cpu);
extern void xics_request_IPIs(void);
extern void xics_migrate_irqs_away(void);
-/* first argument is ignored for now*/
-void pSeriesLP_cppr_info(int n_cpu, u8 value);
-
struct xics_ipi_struct {
volatile unsigned long value;
} ____cacheline_aligned;