diff options
| author | Olof Johansson <olof@lixom.net> | 2007-12-27 22:16:29 -0600 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2007-12-28 09:22:25 -0600 |
| commit | d87bf3bed71375b141e95b5fdbac413ac4b65184 (patch) | |
| tree | 4920be669338029456f625e6f6a587b8e31185b0 /arch/powerpc/sysdev/mpic.c | |
| parent | f365355e65ee619e3b7baeca69b46fd2c4a5ec68 (diff) | |
[POWERPC] pasemi: Distribute interrupts evenly across cpus
By default the OpenPIC on PWRficient will bias to one core (since that
will improve changes of the other core being able to stay idle/powered
down). However, this conflicts with most irq load balancing schemes,
since setting an interrupt to be delivered to either core doesn't really
result in the load being shared. It also doesn't work well with the
soft irq disable feature of PPC, since EE will stay on until the first
interrupt is taken while soft disabled.
Set the gconf0 config bit that enables even distribution of interrupts
among the two cores.
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/powerpc/sysdev/mpic.c')
| -rw-r--r-- | arch/powerpc/sysdev/mpic.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c index 5a9d8c141e6..f88ff09c471 100644 --- a/arch/powerpc/sysdev/mpic.c +++ b/arch/powerpc/sysdev/mpic.c @@ -1279,6 +1279,11 @@ void __init mpic_init(struct mpic *mpic) mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) | MPIC_GREG_GCONF_8259_PTHROU_DIS); + if (mpic->flags & MPIC_NO_BIAS) + mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0), + mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0)) + | MPIC_GREG_GCONF_NO_BIAS); + /* Set current processor priority to 0 */ mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0); |