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| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2007-10-12 21:27:47 -0400 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2007-10-12 21:27:47 -0400 |
| commit | b981d8b3f5e008ff10d993be633ad00564fc22cd (patch) | |
| tree | e292dc07b22308912cf6a58354a608b9e5e8e1fd /arch/powerpc/sysdev/mv64x60_pic.c | |
| parent | b11d2127c4893a7315d1e16273bc8560049fa3ca (diff) | |
| parent | 2b9e0aae1d50e880c58d46788e5e3ebd89d75d62 (diff) | |
Merge master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:
drivers/macintosh/adbhid.c
Diffstat (limited to 'arch/powerpc/sysdev/mv64x60_pic.c')
| -rw-r--r-- | arch/powerpc/sysdev/mv64x60_pic.c | 12 |
1 files changed, 2 insertions, 10 deletions
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c index 01d31628777..19e6ef26379 100644 --- a/arch/powerpc/sysdev/mv64x60_pic.c +++ b/arch/powerpc/sysdev/mv64x60_pic.c @@ -202,11 +202,6 @@ static struct irq_chip mv64x60_chip_gpp = { * mv64x60_host_ops functions */ -static int mv64x60_host_match(struct irq_host *h, struct device_node *np) -{ - return mv64x60_irq_host->host_data == np; -} - static struct irq_chip *mv64x60_chips[] = { [MV64x60_LEVEL1_LOW] = &mv64x60_chip_low, [MV64x60_LEVEL1_HIGH] = &mv64x60_chip_high, @@ -228,7 +223,6 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq, } static struct irq_host_ops mv64x60_host_ops = { - .match = mv64x60_host_match, .map = mv64x60_host_map, }; @@ -253,14 +247,12 @@ void __init mv64x60_init_irq(void) np = of_find_compatible_node(NULL, NULL, "marvell,mv64x60-pic"); reg = of_get_property(np, "reg", &size); paddr = of_translate_address(np, reg); - of_node_put(np); mv64x60_irq_reg_base = ioremap(paddr, reg[1]); - mv64x60_irq_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, MV64x60_NUM_IRQS, + mv64x60_irq_host = irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, + MV64x60_NUM_IRQS, &mv64x60_host_ops, MV64x60_NUM_IRQS); - mv64x60_irq_host->host_data = np; - spin_lock_irqsave(&mv64x60_lock, flags); out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK, mv64x60_cached_gpp_mask); |