Merge branch 'linus' into timers/nohz

117 files changed, 0 insertions, 25840 deletions

diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
deleted file mode 100644
index 76551b67903..00000000000
--- a/arch/ppc/platforms/4xx/Kconfig
+++ /dev/null
@@ -1,285 +0,0 @@
-config 4xx
-	bool
-	depends on 40x || 44x
-	default y
-
-config WANT_EARLY_SERIAL
-	bool
-	select SERIAL_8250
-	default n
-
-menu "IBM 4xx options"
-	depends on 4xx
-
-choice
-	prompt "Machine Type"
-	depends on 40x
-	default WALNUT
-
-config BUBINGA
-	bool "Bubinga"
-	select WANT_EARLY_SERIAL
-	help
-	  This option enables support for the IBM 405EP evaluation board.
-
-config CPCI405
-	bool "CPCI405"
-	help
-	  This option enables support for the CPCI405 board.
-
-config EP405
-	bool "EP405/EP405PC"
-	select EMBEDDEDBOOT
-	help
-	  This option enables support for the EP405/EP405PC boards.
-
-config REDWOOD_5
-	bool "Redwood-5"
-	help
-	  This option enables support for the IBM STB04 evaluation board.
-
-config REDWOOD_6
-	bool "Redwood-6"
-	help
-	  This option enables support for the IBM STBx25xx evaluation board.
-
-config SYCAMORE
-	bool "Sycamore"
-	help
-	  This option enables support for the IBM PPC405GPr evaluation board.
-
-config WALNUT
-	bool "Walnut"
-	help
-	  This option enables support for the IBM PPC405GP evaluation board.
-
-config XILINX_ML300
-	bool "Xilinx-ML300"
-	select XILINX_VIRTEX_II_PRO
-	select EMBEDDEDBOOT
-	help
-	  This option enables support for the Xilinx ML300 evaluation board.
-
-config XILINX_ML403
-	bool "Xilinx-ML403"
-	select XILINX_VIRTEX_4_FX
-	select EMBEDDEDBOOT
-	help
-	  This option enables support for the Xilinx ML403 evaluation board.
-endchoice
-
-choice
-	prompt "Machine Type"
-	depends on 44x
-	default EBONY
-
-config BAMBOO
-	bool "Bamboo"
-	select WANT_EARLY_SERIAL
-	help
-	  This option enables support for the IBM PPC440EP evaluation board.
-
-config EBONY
-	bool "Ebony"
-	select WANT_EARLY_SERIAL
-	help
-	  This option enables support for the IBM PPC440GP evaluation board.
-
-config LUAN
-	bool "Luan"
-	select WANT_EARLY_SERIAL
-	help
-	  This option enables support for the IBM PPC440SP evaluation board.
-
-config YUCCA
-	bool "Yucca"
-	select WANT_EARLY_SERIAL
-	help
-	  This option enables support for the AMCC PPC440SPe evaluation board.
-
-config OCOTEA
-	bool "Ocotea"
-	select WANT_EARLY_SERIAL
-	help
-	  This option enables support for the IBM PPC440GX evaluation board.
-
-config TAISHAN
-	bool "Taishan"
-	select WANT_EARLY_SERIAL
-	help
-	  This option enables support for the AMCC PPC440GX evaluation board.
-
-endchoice
-
-config EP405PC
-	bool "EP405PC Support"
-	depends on EP405
-
-
-# It's often necessary to know the specific 4xx processor type.
-# Fortunately, it is impled (so far) from the board type, so we
-# don't need to ask more redundant questions.
-config NP405H
-	bool
-	depends on ASH
-	default y
-
-config 440EP
-	bool
-	depends on BAMBOO
-	select PPC_FPU
-	default y
-
-config 440GP
-	bool
-	depends on EBONY
-	default y
-
-config 440GX
-	bool
-	depends on OCOTEA || TAISHAN
-	default y
-
-config 440SP
-	bool
-	depends on LUAN
-	default y
-
-config 440SPE
-	bool
-	depends on YUCCA
-	default y
-
-config 440
-	bool
-	depends on 440GP || 440SP || 440SPE || 440EP
-	default y
-
-config 440A
-	bool
-	depends on 440GX
-	default y
-
-config IBM440EP_ERR42
-	bool
-	depends on 440EP
-	default y
-
-# All 405-based cores up until the 405GPR and 405EP have this errata.
-config IBM405_ERR77
-	bool
-	depends on 40x && !403GCX && !405GPR && !405EP
-	default y
-
-# All 40x-based cores, up until the 405GPR and 405EP have this errata.
-config IBM405_ERR51
-	bool
-	depends on 40x && !405GPR && !405EP
-	default y
-
-config BOOKE
-	bool
-	depends on 44x
-	default y
-
-config IBM_OCP
-	bool
-	depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || TAISHAN || WALNUT
-	default y
-
-config IBM_EMAC4
-	bool
-	depends on 440GX || 440SP || 440SPE
-	default y
-
-config BIOS_FIXUP
-	bool
-	depends on BUBINGA || EP405 || SYCAMORE || WALNUT || CPCI405
-	default y
-
-# OAK doesn't exist but wanted to keep this around for any future 403GCX boards
-config 403GCX
-	bool
-	depends on OAK
-	default y
-
-config 405EP
-	bool
-	depends on BUBINGA
-	default y
-
-config 405GP
-	bool
-	depends on CPCI405 || EP405 || WALNUT
-	default y
-
-config 405GPR
-	bool
-	depends on SYCAMORE
-	default y
-
-config XILINX_VIRTEX_II_PRO
-	bool
-	select XILINX_VIRTEX
-
-config XILINX_VIRTEX_4_FX
-	bool
-	select XILINX_VIRTEX
-
-config XILINX_VIRTEX
-	bool
-
-config STB03xxx
-	bool
-	depends on REDWOOD_5 || REDWOOD_6
-	default y
-
-config EMBEDDEDBOOT
-	bool
-
-config IBM_OPENBIOS
-	bool
-	depends on ASH || REDWOOD_5 || REDWOOD_6
-	default y
-
-config PPC4xx_DMA
-	bool "PPC4xx DMA controller support"
-	depends on 4xx
-
-config PPC4xx_EDMA
-	bool
-	depends on !STB03xxx && PPC4xx_DMA
-	default y
-
-config PPC_GEN550
-	bool
-	depends on 4xx
-	default y
-
-choice
-	prompt "TTYS0 device and default console"
-	depends on 40x
-	default UART0_TTYS0
-
-config UART0_TTYS0
-	bool "UART0"
-
-config UART0_TTYS1
-	bool "UART1"
-
-endchoice
-
-config SERIAL_SICC
-	bool "SICC Serial port support"
-	depends on STB03xxx
-
-config UART1_DFLT_CONSOLE
-	bool
-	depends on SERIAL_SICC && UART0_TTYS1
-	default y
-
-config SERIAL_SICC_CONSOLE
-	bool
-	depends on SERIAL_SICC && UART0_TTYS1
-	default y
-endmenu
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
deleted file mode 100644
index 723ad7985cc..00000000000
--- a/arch/ppc/platforms/4xx/Makefile
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# Makefile for the PowerPC 4xx linux kernel.
-
-obj-$(CONFIG_BAMBOO)		+= bamboo.o
-obj-$(CONFIG_CPCI405)		+= cpci405.o
-obj-$(CONFIG_EBONY)		+= ebony.o
-obj-$(CONFIG_EP405)		+= ep405.o
-obj-$(CONFIG_BUBINGA)		+= bubinga.o
-obj-$(CONFIG_LUAN)		+= luan.o
-obj-$(CONFIG_YUCCA)		+= yucca.o
-obj-$(CONFIG_OCOTEA)		+= ocotea.o
-obj-$(CONFIG_REDWOOD_5)		+= redwood5.o
-obj-$(CONFIG_REDWOOD_6)		+= redwood6.o
-obj-$(CONFIG_SYCAMORE)		+= sycamore.o
-obj-$(CONFIG_TAISHAN)		+= taishan.o
-obj-$(CONFIG_WALNUT)		+= walnut.o
-obj-$(CONFIG_XILINX_ML300)	+= xilinx_ml300.o
-obj-$(CONFIG_XILINX_ML403)	+= xilinx_ml403.o
-
-obj-$(CONFIG_405GP)		+= ibm405gp.o
-obj-$(CONFIG_REDWOOD_5)		+= ibmstb4.o
-obj-$(CONFIG_NP405H)		+= ibmnp405h.o
-obj-$(CONFIG_REDWOOD_6)		+= ibmstbx25.o
-obj-$(CONFIG_440EP)		+= ibm440ep.o
-obj-$(CONFIG_440GP)		+= ibm440gp.o
-obj-$(CONFIG_440GX)		+= ibm440gx.o
-obj-$(CONFIG_440SP)		+= ibm440sp.o
-obj-$(CONFIG_440SPE)		+= ppc440spe.o
-obj-$(CONFIG_405EP)		+= ibm405ep.o
-obj-$(CONFIG_405GPR)		+= ibm405gpr.o
-
diff --git a/arch/ppc/platforms/4xx/bamboo.c b/arch/ppc/platforms/4xx/bamboo.c
deleted file mode 100644
index 01f20f4c14f..00000000000
--- a/arch/ppc/platforms/4xx/bamboo.c
+++ /dev/null
@@ -1,442 +0,0 @@
-/*
- * Bamboo board specific routines
- *
- * Wade Farnsworth <wfarnsworth@mvista.com>
- * Copyright 2004 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/ethtool.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-
-#include <syslib/gen550.h>
-#include <syslib/ibm440gx_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-/*
- * Bamboo external IRQ triggering/polarity settings
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ0: Ethernet transceiver */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* IRQ1: Expansion connector */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ2: PCI slot 0 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ3: PCI slot 1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ4: PCI slot 2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ5: PCI slot 3 */
-	(IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE), /* IRQ6: SMI pushbutton */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ7: EXT */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ8: EXT */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* IRQ9: EXT */
-};
-
-static void __init
-bamboo_calibrate_decr(void)
-{
-	unsigned int freq;
-
-	if (mfspr(SPRN_CCR1) & CCR1_TCS)
-		freq = BAMBOO_TMRCLK;
-	else
-		freq = clocks.cpu;
-
-	ibm44x_calibrate_decr(freq);
-
-}
-
-static int
-bamboo_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: IBM\n");
-	seq_printf(m, "machine\t\t: PPC440EP EVB (Bamboo)\n");
-
-	return 0;
-}
-
-static inline int
-bamboo_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *	PCI IDSEL/INTPIN->INTLINE
-	 * 	   A   B   C   D
-	 */
-	{
-		{ 28, 28, 28, 28 },	/* IDSEL 1 - PCI Slot 0 */
-		{ 27, 27, 27, 27 },	/* IDSEL 2 - PCI Slot 1 */
-		{ 26, 26, 26, 26 },	/* IDSEL 3 - PCI Slot 2 */
-		{ 25, 25, 25, 25 },	/* IDSEL 4 - PCI Slot 3 */
-	};
-
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __init bamboo_set_emacdata(void)
-{
-	u8 * base_addr;
-	struct ocp_def *def;
-	struct ocp_func_emac_data *emacdata;
-	u8 val;
-	int mode;
-	u32 excluded = 0;
-
-	base_addr = ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR, 16);
-	val = readb(base_addr);
-	iounmap((void *) base_addr);
-	if (BAMBOO_SEL_MII(val))
-		mode = PHY_MODE_MII;
-	else if (BAMBOO_SEL_RMII(val))
-		mode = PHY_MODE_RMII;
-	else
-		mode = PHY_MODE_SMII;
-
-	/*
-	 * SW2 on the Bamboo is used for ethernet configuration and is accessed
-	 * via the CONFIG2 register in the FPGA.  If the ANEG pin is set,
-	 * overwrite the supported features with the settings in SW2.
-	 *
-	 * This is used as a workaround for the improperly biased RJ-45 sockets
-	 * on the Rev. 0 Bamboo.  By default only 10baseT is functional.
-	 * Removing inductors L17 and L18 from the board allows 100baseT, but
-	 * disables 10baseT.  The Rev. 1 has no such limitations.
-	 */
-
-	base_addr = ioremap64(BAMBOO_FPGA_CONFIG2_REG_ADDR, 8);
-	val = readb(base_addr);
-	iounmap((void *) base_addr);
-	if (!BAMBOO_AUTONEGOTIATE(val)) {
-		excluded |= SUPPORTED_Autoneg;
-		if (BAMBOO_FORCE_100Mbps(val)) {
-			excluded |= SUPPORTED_10baseT_Full;
-			excluded |= SUPPORTED_10baseT_Half;
-			if (BAMBOO_FULL_DUPLEX_EN(val))
-				excluded |= SUPPORTED_100baseT_Half;
-			else
-				excluded |= SUPPORTED_100baseT_Full;
-		} else {
-			excluded |= SUPPORTED_100baseT_Full;
-			excluded |= SUPPORTED_100baseT_Half;
-			if (BAMBOO_FULL_DUPLEX_EN(val))
-				excluded |= SUPPORTED_10baseT_Half;
-			else
-				excluded |= SUPPORTED_10baseT_Full;
-		}
-	}
-
-	/* Set mac_addr, phy mode and unsupported phy features for each EMAC */
-
-	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
-	emacdata = def->additions;
-	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-	emacdata->phy_mode = mode;
-	emacdata->phy_feat_exc = excluded;
-
-	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
-	emacdata = def->additions;
-	memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
-	emacdata->phy_mode = mode;
-	emacdata->phy_feat_exc = excluded;
-}
-
-static int
-bamboo_exclude_device(unsigned char bus, unsigned char devfn)
-{
-	return (bus == 0 && devfn == 0);
-}
-
-#define PCI_READW(offset) \
-        (readw((void *)((u32)pci_reg_base+offset)))
-
-#define PCI_WRITEW(value, offset) \
-	(writew(value, (void *)((u32)pci_reg_base+offset)))
-
-#define PCI_WRITEL(value, offset) \
-	(writel(value, (void *)((u32)pci_reg_base+offset)))
-
-static void __init
-bamboo_setup_pci(void)
-{
-	void *pci_reg_base;
-	unsigned long memory_size;
-	memory_size = ppc_md.find_end_of_memory();
-
-	pci_reg_base = ioremap64(BAMBOO_PCIL0_BASE, BAMBOO_PCIL0_SIZE);
-
-	/* Enable PCI I/O, Mem, and Busmaster cycles */
-	PCI_WRITEW(PCI_READW(PCI_COMMAND) |
-		   PCI_COMMAND_MEMORY |
-		   PCI_COMMAND_MASTER, PCI_COMMAND);
-
-	/* Disable region first */
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA);
-
-	/* PLB starting addr: 0x00000000A0000000 */
-	PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE, BAMBOO_PCIL0_PMM0LA);
-
-	/* PCI start addr, 0xA0000000 (PCI Address) */
-	PCI_WRITEL(BAMBOO_PCI_MEM_BASE, BAMBOO_PCIL0_PMM0PCILA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA);
-
-	/* Enable no pre-fetch, enable region */
-	PCI_WRITEL(((0xffffffff -
-		     (BAMBOO_PCI_UPPER_MEM - BAMBOO_PCI_MEM_BASE)) | 0x01),
-		      BAMBOO_PCIL0_PMM0MA);
-
-	/* Disable region one */
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA);
-
-	/* Disable region two */
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA);
-	PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA);
-
-	/* Now configure the PCI->PLB windows, we only use PTM1
-	 *
-	 * For Inbound flow, set the window size to all available memory
-	 * This is required because if size is smaller,
-	 * then Eth/PCI DD would fail as PCI card not able to access
-	 * the memory allocated by DD.
-	 */
-
-	PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS);	/* disabled region 1 */
-	PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA);	/* begin of address map */
-
-	memory_size = 1 << fls(memory_size - 1);
-
-	/* Size low + Enabled */
-	PCI_WRITEL((0xffffffff - (memory_size - 1)) | 0x1, BAMBOO_PCIL0_PTM1MS);
-
-	eieio();
-	iounmap(pci_reg_base);
-}
-
-static void __init
-bamboo_setup_hose(void)
-{
-	unsigned int bar_response, bar;
-	struct pci_controller *hose;
-
-	bamboo_setup_pci();
-
-	hose = pcibios_alloc_controller();
-
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	hose->pci_mem_offset = BAMBOO_PCI_MEM_OFFSET;
-
-	pci_init_resource(&hose->io_resource,
-			BAMBOO_PCI_LOWER_IO,
-			BAMBOO_PCI_UPPER_IO,
-			IORESOURCE_IO,
-			"PCI host bridge");
-
-	pci_init_resource(&hose->mem_resources[0],
-			BAMBOO_PCI_LOWER_MEM,
-			BAMBOO_PCI_UPPER_MEM,
-			IORESOURCE_MEM,
-			"PCI host bridge");
-
-	ppc_md.pci_exclude_device = bamboo_exclude_device;
-
-	hose->io_space.start = BAMBOO_PCI_LOWER_IO;
-	hose->io_space.end = BAMBOO_PCI_UPPER_IO;
-	hose->mem_space.start = BAMBOO_PCI_LOWER_MEM;
-	hose->mem_space.end = BAMBOO_PCI_UPPER_MEM;
-	isa_io_base =
-		(unsigned long)ioremap64(BAMBOO_PCI_IO_BASE, BAMBOO_PCI_IO_SIZE);
-	hose->io_base_virt = (void *)isa_io_base;
-
-	setup_indirect_pci(hose,
-			BAMBOO_PCI_CFGA_PLB32,
-			BAMBOO_PCI_CFGD_PLB32);
-	hose->set_cfg_type = 1;
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-	}
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = bamboo_map_irq;
-}
-
-TODC_ALLOC();
-
-static void __init
-bamboo_early_serial_map(void)
-{
-	struct uart_port port;
-
-	/* Setup ioremapped serial port access */
-	memset(&port, 0, sizeof(port));
-	port.membase = ioremap64(PPC440EP_UART0_ADDR, 8);
-	port.irq = 0;
-	port.uartclk = clocks.uart0;
-	port.regshift = 0;
-	port.iotype = UPIO_MEM;
-	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	port.line = 0;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 0 failed\n");
-	}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(0, &port);
-#endif
-
-	port.membase = ioremap64(PPC440EP_UART1_ADDR, 8);
-	port.irq = 1;
-	port.uartclk = clocks.uart1;
-	port.line = 1;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 1 failed\n");
-	}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(1, &port);
-#endif
-
-	port.membase = ioremap64(PPC440EP_UART2_ADDR, 8);
-	port.irq = 3;
-	port.uartclk = clocks.uart2;
-	port.line = 2;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 2 failed\n");
-	}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(2, &port);
-#endif
-
-	port.membase = ioremap64(PPC440EP_UART3_ADDR, 8);
-	port.irq = 4;
-	port.uartclk = clocks.uart3;
-	port.line = 3;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 3 failed\n");
-	}
-}
-
-static void __init
-bamboo_setup_arch(void)
-{
-
-	bamboo_set_emacdata();
-
-	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
-	ocp_sys_info.opb_bus_freq = clocks.opb;
-
-	/* Setup TODC access */
-	TODC_INIT(TODC_TYPE_DS1743,
-			0,
-			0,
-			ioremap64(BAMBOO_RTC_ADDR, BAMBOO_RTC_SIZE),
-			8);
-
-	/* init to some ~sane value until calibrate_delay() runs */
-        loops_per_jiffy = 50000000/HZ;
-
-	/* Setup PCI host bridge */
-	bamboo_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_HDA1;
-#endif
-
-	bamboo_early_serial_map();
-
-	/* Identify the system */
-	printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
-		unsigned long r5, unsigned long r6, unsigned long r7)
-{
-	ibm44x_platform_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = bamboo_setup_arch;
-	ppc_md.show_cpuinfo = bamboo_show_cpuinfo;
-	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
-
-	ppc_md.calibrate_decr = bamboo_calibrate_decr;
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = bamboo_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/bamboo.h b/arch/ppc/platforms/4xx/bamboo.h
deleted file mode 100644
index dcd3d09a0a7..00000000000
--- a/arch/ppc/platforms/4xx/bamboo.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * Bamboo board definitions
- *
- * Wade Farnsworth <wfarnsworth@mvista.com>
- *
- * Copyright 2004 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_BAMBOO_H__
-#define __ASM_BAMBOO_H__
-
-#include <platforms/4xx/ibm440ep.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0		0x0EF600E00
-
-/* Location of MAC addresses in PIBS image */
-#define PIBS_FLASH_BASE			0xfff00000
-#define PIBS_MAC_BASE			(PIBS_FLASH_BASE+0xc0400)
-#define PIBS_MAC_SIZE			0x200
-#define PIBS_MAC_OFFSET			0x100
-
-/* Default clock rate */
-#define BAMBOO_TMRCLK			25000000
-
-/* RTC/NVRAM location */
-#define BAMBOO_RTC_ADDR			0x080000000ULL
-#define BAMBOO_RTC_SIZE			0x2000
-
-/* FPGA Registers */
-#define BAMBOO_FPGA_ADDR		0x080002000ULL
-
-#define BAMBOO_FPGA_CONFIG2_REG_ADDR	(BAMBOO_FPGA_ADDR + 0x1)
-#define BAMBOO_FULL_DUPLEX_EN(x)	(x & 0x08)
-#define BAMBOO_FORCE_100Mbps(x)		(x & 0x04)
-#define BAMBOO_AUTONEGOTIATE(x)		(x & 0x02)
-
-#define BAMBOO_FPGA_SETTING_REG_ADDR	(BAMBOO_FPGA_ADDR + 0x3)
-#define BAMBOO_BOOT_SMALL_FLASH(x)	(!(x & 0x80))
-#define BAMBOO_LARGE_FLASH_EN(x)	(!(x & 0x40))
-#define BAMBOO_BOOT_NAND_FLASH(x)	(!(x & 0x20))
-
-#define BAMBOO_FPGA_SELECTION1_REG_ADDR (BAMBOO_FPGA_ADDR + 0x4)
-#define BAMBOO_SEL_MII(x)		(x & 0x80)
-#define BAMBOO_SEL_RMII(x)		(x & 0x40)
-#define BAMBOO_SEL_SMII(x)		(x & 0x20)
-
-/* Flash */
-#define BAMBOO_SMALL_FLASH_LOW		0x087f00000ULL
-#define BAMBOO_SMALL_FLASH_HIGH		0x0fff00000ULL
-#define BAMBOO_SMALL_FLASH_SIZE		0x100000
-#define BAMBOO_LARGE_FLASH_LOW		0x087800000ULL
-#define BAMBOO_LARGE_FLASH_HIGH1	0x0ff800000ULL
-#define BAMBOO_LARGE_FLASH_HIGH2	0x0ffc00000ULL
-#define BAMBOO_LARGE_FLASH_SIZE		0x400000
-#define BAMBOO_SRAM_LOW			0x087f00000ULL
-#define BAMBOO_SRAM_HIGH1		0x0fff00000ULL
-#define BAMBOO_SRAM_HIGH2		0x0ff800000ULL
-#define BAMBOO_SRAM_SIZE		0x100000
-#define BAMBOO_NAND_FLASH_REG_ADDR	0x090000000ULL
-#define BAMBOO_NAND_FLASH_REG_SIZE	0x2000
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE			4
-
-#define UART0_IO_BASE			0xEF600300
-#define UART1_IO_BASE			0xEF600400
-#define UART2_IO_BASE			0xEF600500
-#define UART3_IO_BASE			0xEF600600
-
-#define BASE_BAUD			33177600/3/16
-#define UART0_INT			0
-#define UART1_INT			1
-#define UART2_INT			3
-#define UART3_INT			4
-
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (void*)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)		\
-	STD_UART_OP(2)		\
-	STD_UART_OP(3)
-
-/* PCI support */
-#define BAMBOO_PCI_CFGA_PLB32		0xeec00000
-#define BAMBOO_PCI_CFGD_PLB32		0xeec00004
-
-#define BAMBOO_PCI_IO_BASE		0x00000000e8000000ULL
-#define BAMBOO_PCI_IO_SIZE		0x00010000
-#define BAMBOO_PCI_MEM_OFFSET		0x00000000
-#define BAMBOO_PCI_PHY_MEM_BASE		0x00000000a0000000ULL
-
-#define BAMBOO_PCI_LOWER_IO		0x00000000
-#define BAMBOO_PCI_UPPER_IO		0x0000ffff
-#define BAMBOO_PCI_LOWER_MEM		0xa0000000
-#define BAMBOO_PCI_UPPER_MEM		0xafffffff
-#define BAMBOO_PCI_MEM_BASE		0xa0000000
-
-#define BAMBOO_PCIL0_BASE		0x00000000ef400000ULL
-#define BAMBOO_PCIL0_SIZE		0x40
-
-#define BAMBOO_PCIL0_PMM0LA		0x000
-#define BAMBOO_PCIL0_PMM0MA		0x004
-#define BAMBOO_PCIL0_PMM0PCILA		0x008
-#define BAMBOO_PCIL0_PMM0PCIHA		0x00C
-#define BAMBOO_PCIL0_PMM1LA		0x010
-#define BAMBOO_PCIL0_PMM1MA		0x014
-#define BAMBOO_PCIL0_PMM1PCILA		0x018
-#define BAMBOO_PCIL0_PMM1PCIHA		0x01C
-#define BAMBOO_PCIL0_PMM2LA		0x020
-#define BAMBOO_PCIL0_PMM2MA		0x024
-#define BAMBOO_PCIL0_PMM2PCILA		0x028
-#define BAMBOO_PCIL0_PMM2PCIHA		0x02C
-#define BAMBOO_PCIL0_PTM1MS		0x030
-#define BAMBOO_PCIL0_PTM1LA		0x034
-#define BAMBOO_PCIL0_PTM2MS		0x038
-#define BAMBOO_PCIL0_PTM2LA		0x03C
-
-#endif                          /* __ASM_BAMBOO_H__ */
-#endif                          /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/bubinga.c b/arch/ppc/platforms/4xx/bubinga.c
deleted file mode 100644
index cd696be55ac..00000000000
--- a/arch/ppc/platforms/4xx/bubinga.c
+++ /dev/null
@@ -1,265 +0,0 @@
-/*
- * Support for IBM PPC 405EP evaluation board (Bubinga).
- *
- * Author: SAW (IBM), derived from walnut.c.
- *         Maintained by MontaVista Software <source@mvista.com>
- *
- * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/blkdev.h>
-#include <linux/pci.h>
-#include <linux/rtc.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/processor.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/todc.h>
-#include <asm/kgdb.h>
-#include <asm/ocp.h>
-#include <asm/ibm_ocp_pci.h>
-
-#include <platforms/4xx/ibm405ep.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-extern bd_t __res;
-
-void *bubinga_rtc_base;
-
-/* Some IRQs unique to the board
- * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
- */
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	    /*
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *      A       B       C       D
-	     */
-	{
-		{28, 28, 28, 28},	/* IDSEL 1 - PCI slot 1 */
-		{29, 29, 29, 29},	/* IDSEL 2 - PCI slot 2 */
-		{30, 30, 30, 30},	/* IDSEL 3 - PCI slot 3 */
-		{31, 31, 31, 31},	/* IDSEL 4 - PCI slot 4 */
-	};
-
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-};
-
-/* The serial clock for the chip is an internal clock determined by
- * different clock speeds/dividers.
- * Calculate the proper input baud rate and setup the serial driver.
- */
-static void __init
-bubinga_early_serial_map(void)
-{
-	u32 uart_div;
-	int uart_clock;
-	struct uart_port port;
-
-         /* Calculate the serial clock input frequency
-          *
-          * The base baud is the PLL OUTA (provided in the board info
-          * structure) divided by the external UART Divisor, divided
-          * by 16.
-          */
-	uart_div = (mfdcr(DCRN_CPC0_UCR_BASE) & DCRN_CPC0_UCR_U0DIV);
-	uart_clock = __res.bi_procfreq / uart_div;
-
-	/* Setup serial port access */
-	memset(&port, 0, sizeof(port));
-	port.membase = (void*)ACTING_UART0_IO_BASE;
-	port.irq = ACTING_UART0_INT;
-	port.uartclk = uart_clock;
-	port.regshift = 0;
-	port.iotype = UPIO_MEM;
-	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	port.line = 0;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 0 failed\n");
-	}
-
-	port.membase = (void*)ACTING_UART1_IO_BASE;
-	port.irq = ACTING_UART1_INT;
-	port.line = 1;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 1 failed\n");
-	}
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
-
-	unsigned int bar_response, bar;
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 * The following code is simplified by assuming that the bootrom
-	 * has been well behaved in following this mapping.
-	 */
-
-#ifdef DEBUG
-	int i;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
-	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
-
-	/* Disable region first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Disable region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000001);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-	out_le32((void *) &(pcip->ptm2la), 0x00000000);
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-	/* end workaround */
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-#endif
-}
-
-void __init
-bubinga_setup_arch(void)
-{
-	ppc4xx_setup_arch();
-
-	ibm_ocp_set_emac(0, 1);
-
-        bubinga_early_serial_map();
-
-        /* RTC step for the evb405ep */
-        bubinga_rtc_base = (void *) BUBINGA_RTC_VADDR;
-        TODC_INIT(TODC_TYPE_DS1743, bubinga_rtc_base, bubinga_rtc_base,
-                  bubinga_rtc_base, 8);
-        /* Identify the system */
-        printk("IBM Bubinga port (MontaVista Software, Inc. <source@mvista.com>)\n");
-}
-
-void __init
-bubinga_map_io(void)
-{
-	ppc4xx_map_io();
-     	io_block_mapping(BUBINGA_RTC_VADDR,
-                         BUBINGA_RTC_PADDR, BUBINGA_RTC_SIZE, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = bubinga_setup_arch;
-	ppc_md.setup_io_mappings = bubinga_map_io;
-
-#ifdef CONFIG_GEN_RTC
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = bubinga_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/bubinga.h b/arch/ppc/platforms/4xx/bubinga.h
deleted file mode 100644
index 5c408060eb3..00000000000
--- a/arch/ppc/platforms/4xx/bubinga.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Bubinga board definitions
- *
- * Copyright (c) 2005 DENX Software Engineering
- * Stefan Roese <sr@denx.de>
- *
- * Based on original work by
- *	SAW (IBM)
- *	2003 (c) MontaVista Softare Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __BUBINGA_H__
-#define __BUBINGA_H__
-
-#include <platforms/4xx/ibm405ep.h>
-#include <asm/ppcboot.h>
-
-/* Memory map for the Bubinga board.
- * Generic 4xx plus RTC.
- */
-
-#define BUBINGA_RTC_PADDR	((uint)0xf0000000)
-#define BUBINGA_RTC_VADDR	BUBINGA_RTC_PADDR
-#define BUBINGA_RTC_SIZE	((uint)8*1024)
-
-/* The UART clock is based off an internal clock -
- * define BASE_BAUD based on the internal clock and divider(s).
- * Since BASE_BAUD must be a constant, we will initialize it
- * using clock/divider values which OpenBIOS initializes
- * for typical configurations at various CPU speeds.
- * The base baud is calculated as (FWDA / EXT UART DIV / 16)
- */
-#define BASE_BAUD		0
-
-/* Flash */
-#define PPC40x_FPGA_BASE	0xF0300000
-#define PPC40x_FPGA_REG_OFFS	1	/* offset to flash map reg */
-#define PPC40x_FLASH_ONBD_N(x)	(x & 0x02)
-#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
-#define PPC40x_FLASH_LOW	0xFFF00000
-#define PPC40x_FLASH_HIGH	0xFFF80000
-#define PPC40x_FLASH_SIZE	0x80000
-
-#define PPC4xx_MACHINE_NAME	"IBM Bubinga"
-
-#endif /* __BUBINGA_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/cpci405.c b/arch/ppc/platforms/4xx/cpci405.c
deleted file mode 100644
index 2e7e25dd84c..00000000000
--- a/arch/ppc/platforms/4xx/cpci405.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Board setup routines for the esd CPCI-405 cPCI Board.
- *
- * Copyright 2001-2006 esd electronic system design - hannover germany
- *
- * Authors: Matthias Fuchs
- *          matthias.fuchs@esd-electronics.com
- *          Stefan Roese
- *          stefan.roese@esd-electronics.com
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/machdep.h>
-#include <asm/todc.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <asm/ocp.h>
-#include <asm/ibm_ocp_pci.h>
-#include <platforms/4xx/ibm405gp.h>
-
-#ifdef CONFIG_GEN_RTC
-void *cpci405_nvram;
-#endif
-
-extern bd_t __res;
-
-/*
- * Some IRQs unique to CPCI-405.
- */
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *      PCI IDSEL/INTPIN->INTLINE
-	 *      A       B       C       D
-	 */
-	{
-		{28,	29,	30,	27},	/* IDSEL 15 - cPCI slot 8 */
-		{29,	30,	27,	28},	/* IDSEL 16 - cPCI slot 7 */
-		{30,	27,	28,	29},	/* IDSEL 17 - cPCI slot 6 */
-		{27,	28,	29,	30},	/* IDSEL 18 - cPCI slot 5 */
-		{28,	29,	30,	27},	/* IDSEL 19 - cPCI slot 4 */
-		{29,	30,	27,	28},	/* IDSEL 20 - cPCI slot 3 */
-		{30,	27,	28,	29},	/* IDSEL 21 - cPCI slot 2 */
-        };
-	const long min_idsel = 15, max_idsel = 21, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-};
-
-/* The serial clock for the chip is an internal clock determined by
- * different clock speeds/dividers.
- * Calculate the proper input baud rate and setup the serial driver.
- */
-static void __init
-cpci405_early_serial_map(void)
-{
-	u32 uart_div;
-	int uart_clock;
-	struct uart_port port;
-
-         /* Calculate the serial clock input frequency
-          *
-          * The uart clock is the cpu frequency (provided in the board info
-          * structure) divided by the external UART Divisor.
-          */
-	uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1;
-	uart_clock = __res.bi_procfreq / uart_div;
-
-	/* Setup serial port access */
-	memset(&port, 0, sizeof(port));
-#if defined(CONFIG_UART0_TTYS0)
-	port.membase = (void*)UART0_IO_BASE;
-	port.irq = UART0_INT;
-#else
-	port.membase = (void*)UART1_IO_BASE;
-	port.irq = UART1_INT;
-#endif
-	port.uartclk = uart_clock;
-	port.regshift = 0;
-	port.iotype = UPIO_MEM;
-	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	port.line = 0;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 0 failed\n");
-	}
-#if defined(CONFIG_UART0_TTYS0)
-	port.membase = (void*)UART1_IO_BASE;
-	port.irq = UART1_INT;
-#else
-	port.membase = (void*)UART0_IO_BASE;
-	port.irq = UART0_INT;
-#endif
-	port.line = 1;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 1 failed\n");
-	}
-}
-
-void __init
-cpci405_setup_arch(void)
-{
-	ppc4xx_setup_arch();
-
-	ibm_ocp_set_emac(0, 0);
-
-        cpci405_early_serial_map();
-
-#ifdef CONFIG_GEN_RTC
-	TODC_INIT(TODC_TYPE_MK48T35,
-		  cpci405_nvram, cpci405_nvram, cpci405_nvram, 8);
-#endif
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
-	unsigned int bar_response, bar;
-
-	/* Disable region first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Disable region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000001);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-	out_le32((void *) &(pcip->ptm2la), 0x00000000);
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-	}
-#endif
-}
-
-void __init
-cpci405_map_io(void)
-{
-	ppc4xx_map_io();
-
-#ifdef CONFIG_GEN_RTC
-	cpci405_nvram = ioremap(CPCI405_NVRAM_PADDR, CPCI405_NVRAM_SIZE);
-#endif
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = cpci405_setup_arch;
-	ppc_md.setup_io_mappings = cpci405_map_io;
-
-#ifdef CONFIG_GEN_RTC
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/cpci405.h b/arch/ppc/platforms/4xx/cpci405.h
deleted file mode 100644
index a6c0a138b0d..00000000000
--- a/arch/ppc/platforms/4xx/cpci405.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * CPCI-405 board specific definitions
- *
- * Copyright 2001-2006 esd electronic system design - hannover germany
- *
- * Authors: Matthias Fuchs
- *          matthias.fuchs@esd-electronics.com
- *          Stefan Roese
- *          stefan.roese@esd-electronics.com
- */
-
-#ifdef __KERNEL__
-#ifndef __CPCI405_H__
-#define __CPCI405_H__
-
-#include <platforms/4xx/ibm405gp.h>
-#include <asm/ppcboot.h>
-
-/* Map for the NVRAM space */
-#define CPCI405_NVRAM_PADDR	((uint)0xf0200000)
-#define CPCI405_NVRAM_SIZE	((uint)32*1024)
-
-#define BASE_BAUD		0
-
-#define PPC4xx_MACHINE_NAME     "esd CPCI-405"
-
-#endif	/* __CPCI405_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ebony.c b/arch/ppc/platforms/4xx/ebony.c
deleted file mode 100644
index 8027a36fc5b..00000000000
--- a/arch/ppc/platforms/4xx/ebony.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * Ebony board specific routines
- *
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003-2005 Zultys Technologies
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-#include <asm/tlbflush.h>
-
-#include <syslib/gen550.h>
-#include <syslib/ibm440gp_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-/*
- * Ebony external IRQ triggering/polarity settings
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ0: PCI slot 0 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ1: PCI slot 1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ2: PCI slot 2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ3: PCI slot 3 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ4: IRDA */
-	(IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE),	/* IRQ5: SMI pushbutton */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ6: PHYs */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ7: AUX */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ8: EXT */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ9: EXT */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ10: EXT */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ11: EXT */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ12: EXT */
-};
-
-static void __init
-ebony_calibrate_decr(void)
-{
-	unsigned int freq;
-
-	/*
-	 * Determine system clock speed
-	 *
-	 * If we are on Rev. B silicon, then use
-	 * default external system clock.  If we are
-	 * on Rev. C silicon then errata forces us to
-	 * use the internal clock.
-	 */
-	if (strcmp(cur_cpu_spec->cpu_name, "440GP Rev. B") == 0)
-		freq = EBONY_440GP_RB_SYSCLK;
-	else
-		freq = EBONY_440GP_RC_SYSCLK;
-
-	ibm44x_calibrate_decr(freq);
-}
-
-static int
-ebony_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: IBM\n");
-	seq_printf(m, "machine\t\t: Ebony\n");
-
-	return 0;
-}
-
-static inline int
-ebony_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *	PCI IDSEL/INTPIN->INTLINE
-	 * 	   A   B   C   D
-	 */
-	{
-		{ 23, 23, 23, 23 },	/* IDSEL 1 - PCI Slot 0 */
-		{ 24, 24, 24, 24 },	/* IDSEL 2 - PCI Slot 1 */
-		{ 25, 25, 25, 25 },	/* IDSEL 3 - PCI Slot 2 */
-		{ 26, 26, 26, 26 },	/* IDSEL 4 - PCI Slot 3 */
-	};
-
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-#define PCIX_WRITEL(value, offset) \
-	(writel(value, pcix_reg_base + offset))
-
-/*
- * FIXME: This is only here to "make it work".  This will move
- * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
- * configuration library. -Matt
- */
-static void __init
-ebony_setup_pcix(void)
-{
-	void __iomem *pcix_reg_base;
-
-	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
-
-	/* Disable all windows */
-	PCIX_WRITEL(0, PCIX0_POM0SA);
-	PCIX_WRITEL(0, PCIX0_POM1SA);
-	PCIX_WRITEL(0, PCIX0_POM2SA);
-	PCIX_WRITEL(0, PCIX0_PIM0SA);
-	PCIX_WRITEL(0, PCIX0_PIM1SA);
-	PCIX_WRITEL(0, PCIX0_PIM2SA);
-
-	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
-	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
-	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
-	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
-	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
-	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
-
-	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
-	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
-	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
-	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
-
-	eieio();
-}
-
-static void __init
-ebony_setup_hose(void)
-{
-	struct pci_controller *hose;
-
-	/* Configure windows on the PCI-X host bridge */
-	ebony_setup_pcix();
-
-	hose = pcibios_alloc_controller();
-
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	hose->pci_mem_offset = EBONY_PCI_MEM_OFFSET;
-
-	pci_init_resource(&hose->io_resource,
-			EBONY_PCI_LOWER_IO,
-			EBONY_PCI_UPPER_IO,
-			IORESOURCE_IO,
-			"PCI host bridge");
-
-	pci_init_resource(&hose->mem_resources[0],
-			EBONY_PCI_LOWER_MEM,
-			EBONY_PCI_UPPER_MEM,
-			IORESOURCE_MEM,
-			"PCI host bridge");
-
-	hose->io_space.start = EBONY_PCI_LOWER_IO;
-	hose->io_space.end = EBONY_PCI_UPPER_IO;
-	hose->mem_space.start = EBONY_PCI_LOWER_MEM;
-	hose->mem_space.end = EBONY_PCI_UPPER_MEM;
-	hose->io_base_virt = ioremap64(EBONY_PCI_IO_BASE, EBONY_PCI_IO_SIZE);
-	isa_io_base = (unsigned long)hose->io_base_virt;
-
-	setup_indirect_pci(hose,
-			EBONY_PCI_CFGA_PLB32,
-			EBONY_PCI_CFGD_PLB32);
-	hose->set_cfg_type = 1;
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = ebony_map_irq;
-}
-
-TODC_ALLOC();
-
-static void __init
-ebony_early_serial_map(void)
-{
-	struct uart_port port;
-
-	/* Setup ioremapped serial port access */
-	memset(&port, 0, sizeof(port));
-	port.membase = ioremap64(PPC440GP_UART0_ADDR, 8);
-	port.irq = 0;
-	port.uartclk = clocks.uart0;
-	port.regshift = 0;
-	port.iotype = UPIO_MEM;
-	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	port.line = 0;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 0 failed\n");
-	}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(0, &port);
-
-	/* Purge TLB entry added in head_44x.S for early serial access */
-	_tlbie(UART0_IO_BASE, 0);
-#endif
-
-	port.membase = ioremap64(PPC440GP_UART1_ADDR, 8);
-	port.irq = 1;
-	port.uartclk = clocks.uart1;
-	port.line = 1;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 1 failed\n");
-	}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(1, &port);
-#endif
-}
-
-static void __init
-ebony_setup_arch(void)
-{
-	struct ocp_def *def;
-	struct ocp_func_emac_data *emacdata;
-
-	/* Set mac_addr for each EMAC */
-	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
-	emacdata = def->additions;
-	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
-	emacdata->phy_mode = PHY_MODE_RMII;
-	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-
-	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 1);
-	emacdata = def->additions;
-	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
-	emacdata->phy_mode = PHY_MODE_RMII;
-	memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
-
-	/*
-	 * Determine various clocks.
-	 * To be completely correct we should get SysClk
-	 * from FPGA, because it can be changed by on-board switches
-	 * --ebs
-	 */
-	ibm440gp_get_clocks(&clocks, 33333333, 6 * 1843200);
-	ocp_sys_info.opb_bus_freq = clocks.opb;
-
-	/* Setup TODC access */
-	TODC_INIT(TODC_TYPE_DS1743,
-			0,
-			0,
-			ioremap64(EBONY_RTC_ADDR, EBONY_RTC_SIZE),
-			8);
-
-	/* init to some ~sane value until calibrate_delay() runs */
-        loops_per_jiffy = 50000000/HZ;
-
-	/* Setup PCI host bridge */
-	ebony_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_HDA1;
-#endif
-
-	ebony_early_serial_map();
-
-	/* Identify the system */
-	printk("IBM Ebony port (MontaVista Software, Inc. (source@mvista.com))\n");
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
-		unsigned long r5, unsigned long r6, unsigned long r7)
-{
-	ibm44x_platform_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = ebony_setup_arch;
-	ppc_md.show_cpuinfo = ebony_show_cpuinfo;
-	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
-
-	ppc_md.calibrate_decr = ebony_calibrate_decr;
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = ebony_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/ebony.h b/arch/ppc/platforms/4xx/ebony.h
deleted file mode 100644
index f40e33d39d7..00000000000
--- a/arch/ppc/platforms/4xx/ebony.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Ebony board definitions
- *
- * Matt Porter <mporter@mvista.com>
- *
- * Copyright 2002 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_EBONY_H__
-#define __ASM_EBONY_H__
-
-#include <platforms/4xx/ibm440gp.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0	0xE0000800
-
-/* Where to find the MAC info */
-#define OPENBIOS_MAC_BASE	0xfffffe0c
-#define OPENBIOS_MAC_OFFSET	0x0c
-
-/* Default clock rates for Rev. B and Rev. C silicon */
-#define EBONY_440GP_RB_SYSCLK	33000000
-#define EBONY_440GP_RC_SYSCLK	400000000
-
-/* RTC/NVRAM location */
-#define EBONY_RTC_ADDR		0x0000000148000000ULL
-#define EBONY_RTC_SIZE		0x2000
-
-/* Flash */
-#define EBONY_FPGA_ADDR		0x0000000148300000ULL
-#define EBONY_BOOT_SMALL_FLASH(x)	(x & 0x20)
-#define EBONY_ONBRD_FLASH_EN(x)		(x & 0x02)
-#define EBONY_FLASH_SEL(x)		(x & 0x01)
-#define EBONY_SMALL_FLASH_LOW1	0x00000001ff800000ULL
-#define EBONY_SMALL_FLASH_LOW2	0x00000001ff880000ULL
-#define EBONY_SMALL_FLASH_HIGH1	0x00000001fff00000ULL
-#define EBONY_SMALL_FLASH_HIGH2	0x00000001fff80000ULL
-#define EBONY_SMALL_FLASH_SIZE	0x80000
-#define EBONY_LARGE_FLASH_LOW	0x00000001ff800000ULL
-#define EBONY_LARGE_FLASH_HIGH	0x00000001ffc00000ULL
-#define EBONY_LARGE_FLASH_SIZE	0x400000
-
-#define EBONY_SMALL_FLASH_BASE	0x00000001fff80000ULL
-#define EBONY_LARGE_FLASH_BASE	0x00000001ff800000ULL
-
-/*
- * Serial port defines
- */
-
-#if defined(__BOOTER__)
-/* OpenBIOS defined UART mappings, used by bootloader shim */
-#define UART0_IO_BASE	0xE0000200
-#define UART1_IO_BASE	0xE0000300
-#else
-/* head_44x.S created UART mapping, used before early_serial_setup.
- * We cannot use default OpenBIOS UART mappings because they
- * don't work for configurations with more than 512M RAM.    --ebs
- */
-#define UART0_IO_BASE	0xF0000200
-#define UART1_IO_BASE	0xF0000300
-#endif
-
-/* external Epson SG-615P */
-#define BASE_BAUD	691200
-
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (void*)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-
-/* PCI support */
-#define EBONY_PCI_LOWER_IO	0x00000000
-#define EBONY_PCI_UPPER_IO	0x0000ffff
-#define EBONY_PCI_LOWER_MEM	0x80002000
-#define EBONY_PCI_UPPER_MEM	0xffffefff
-
-#define EBONY_PCI_CFGREGS_BASE	0x000000020ec00000
-#define EBONY_PCI_CFGA_PLB32	0x0ec00000
-#define EBONY_PCI_CFGD_PLB32	0x0ec00004
-
-#define EBONY_PCI_IO_BASE	0x0000000208000000ULL
-#define EBONY_PCI_IO_SIZE	0x00010000
-#define EBONY_PCI_MEM_OFFSET	0x00000000
-
-#endif				/* __ASM_EBONY_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ep405.c b/arch/ppc/platforms/4xx/ep405.c
deleted file mode 100644
index 5aa29502280..00000000000
--- a/arch/ppc/platforms/4xx/ep405.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Embedded Planet 405GP board
- * http://www.embeddedplanet.com
- *
- * Author: Matthew Locke <mlocke@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include <linux/pci.h>
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/machdep.h>
-#include <asm/todc.h>
-#include <asm/ocp.h>
-#include <asm/ibm_ocp_pci.h>
-
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-u8 *ep405_bcsr;
-u8 *ep405_nvram;
-
-static struct {
-	u8 cpld_xirq_select;
-	int pci_idsel;
-	int irq;
-} ep405_devtable[] = {
-#ifdef CONFIG_EP405PC
-	{0x07, 0x0E, 25},		/* EP405PC: USB */
-#endif
-};
-
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	int i;
-
-	/* AFAICT this is only called a few times during PCI setup, so
-	   performance is not critical */
-	for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
-		if (idsel == ep405_devtable[i].pci_idsel)
-			return ep405_devtable[i].irq;
-	}
-	return -1;
-};
-
-void __init
-ep405_setup_arch(void)
-{
-	ppc4xx_setup_arch();
-
-	ibm_ocp_set_emac(0, 0);
-
-	if (__res.bi_nvramsize == 512*1024) {
-		/* FIXME: we should properly handle NVRTCs of different sizes */
-		TODC_INIT(TODC_TYPE_DS1557, ep405_nvram, ep405_nvram, ep405_nvram, 8);
-	}
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
-	unsigned int bar_response, bar;
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 */
-
-	/* Disable region zero first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Disable region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000000);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* Configure PTM (PCI->PLB) region 1 */
-	out_le32((void *) &(pcip->ptm1la), 0x00000000); /* PLB base address */
-	/* Disable PTM region 2 */
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-	/* end workaround */
-#endif
-}
-
-void __init
-ep405_map_io(void)
-{
-	bd_t *bip = &__res;
-
-	ppc4xx_map_io();
-
-	ep405_bcsr = ioremap(EP405_BCSR_PADDR, EP405_BCSR_SIZE);
-
-	if (bip->bi_nvramsize > 0) {
-		ep405_nvram = ioremap(EP405_NVRAM_PADDR, bip->bi_nvramsize);
-	}
-}
-
-void __init
-ep405_init_IRQ(void)
-{
-	int i;
-
-	ppc4xx_init_IRQ();
-
-	/* Workaround for a bug in the firmware it incorrectly sets
-	   the IRQ polarities for XIRQ0 and XIRQ1 */
-	mtdcr(DCRN_UIC_PR(DCRN_UIC0_BASE), 0xffffff80); /* set the polarity */
-	mtdcr(DCRN_UIC_SR(DCRN_UIC0_BASE), 0x00000060); /* clear bogus interrupts */
-
-	/* Activate the XIRQs from the CPLD */
-	writeb(0xf0, ep405_bcsr+10);
-
-	/* Set up IRQ routing */
-	for (i = 0; i < ARRAY_SIZE(ep405_devtable); i++) {
-		if ( (ep405_devtable[i].irq >= 25)
-		     && (ep405_devtable[i].irq) <= 31) {
-			writeb(ep405_devtable[i].cpld_xirq_select, ep405_bcsr+5);
-			writeb(ep405_devtable[i].irq - 25, ep405_bcsr+6);
-		}
-	}
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = ep405_setup_arch;
-	ppc_md.setup_io_mappings = ep405_map_io;
-	ppc_md.init_IRQ = ep405_init_IRQ;
-
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-
-	if (__res.bi_nvramsize == 512*1024) {
-		ppc_md.time_init = todc_time_init;
-		ppc_md.set_rtc_time = todc_set_rtc_time;
-		ppc_md.get_rtc_time = todc_get_rtc_time;
-	} else {
-		printk("EP405: NVRTC size is not 512k (not a DS1557).  Not sure what to do with it\n");
-	}
-}
diff --git a/arch/ppc/platforms/4xx/ep405.h b/arch/ppc/platforms/4xx/ep405.h
deleted file mode 100644
index 9814fc43172..00000000000
--- a/arch/ppc/platforms/4xx/ep405.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Embedded Planet 405GP board
- * http://www.embeddedplanet.com
- *
- * Author: Matthew Locke <mlocke@mvista.com>
- *
- * 2000 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_EP405_H__
-#define __ASM_EP405_H__
-
-/* We have a 405GP core */
-#include <platforms/4xx/ibm405gp.h>
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-typedef struct board_info {
-	unsigned int	 bi_memsize;		/* DRAM installed, in bytes */
-	unsigned char	 bi_enetaddr[6];	/* Local Ethernet MAC address */
-	unsigned int	 bi_intfreq;		/* Processor speed, in Hz */
-	unsigned int	 bi_busfreq;		/* PLB Bus speed, in Hz */
-	unsigned int	 bi_pci_busfreq;	/* PCI Bus speed, in Hz */
-	unsigned int	 bi_nvramsize;		/* Size of the NVRAM/RTC */
-} bd_t;
-
-/* Some 4xx parts use a different timebase frequency from the internal clock.
-*/
-#define bi_tbfreq bi_intfreq
-
-extern u8 *ep405_bcsr;
-extern u8 *ep405_nvram;
-
-/* Map for the BCSR and NVRAM space */
-#define EP405_BCSR_PADDR	((uint)0xf4000000)
-#define EP405_BCSR_SIZE		((uint)16)
-#define EP405_NVRAM_PADDR	((uint)0xf4200000)
-
-/* serial defines */
-#define BASE_BAUD		399193
-
-#define PPC4xx_MACHINE_NAME "Embedded Planet 405GP"
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __ASM_EP405_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405ep.c b/arch/ppc/platforms/4xx/ibm405ep.c
deleted file mode 100644
index fb3630a1608..00000000000
--- a/arch/ppc/platforms/4xx/ibm405ep.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Support for IBM PPC 405EP processors.
- *
- * Author: SAW (IBM), derived from ibmnp405l.c.
- *         Maintained by MontaVista Software <source@mvista.com>
- *
- * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-
-#include <asm/ibm4xx.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-#include <platforms/4xx/ibm405ep.h>
-
-static struct ocp_func_mal_data ibm405ep_mal0_def = {
-	.num_tx_chans	= 4,		/* Number of TX channels */
-	.num_rx_chans	= 2,		/* Number of RX channels */
-	.txeob_irq	= 11,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 12,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 13,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 14,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 10,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_emac_data ibm405ep_emac0_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx	= -1,		/* ZMII device index */
-	.zmii_mux	= 0,		/* ZMII input of this EMAC */
-	.mal_idx	= 0,		/* MAL device index */
-	.mal_rx_chan	= 0,		/* MAL rx channel number */
-	.mal_tx_chan	= 0,		/* MAL tx channel number */
-	.wol_irq	= 9,		/* WOL interrupt number */
-	.mdio_idx	= 0,		/* MDIO via EMAC0 */
-	.tah_idx	= -1,		/* No TAH */
-};
-
-static struct ocp_func_emac_data ibm405ep_emac1_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx	= -1,		/* ZMII device index */
-	.zmii_mux	= 0,		/* ZMII input of this EMAC */
-	.mal_idx	= 0,		/* MAL device index */
-	.mal_rx_chan	= 1,		/* MAL rx channel number */
-	.mal_tx_chan	= 2,		/* MAL tx channel number */
-	.wol_irq	= 9,		/* WOL interrupt number */
-	.mdio_idx	= 0,		/* MDIO via EMAC0 */
-	.tah_idx	= -1,		/* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_iic_data ibm405ep_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_OPB,
-	  .index	= 0,
-	  .paddr	= 0xEF600000,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= UART0_IO_BASE,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= UART1_IO_BASE,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .paddr	= 0xEF600500,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibm405ep_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .paddr	= 0xEF600700,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm405ep_mal0_def,
-	  .show		= &ocp_show_mal_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= EMAC0_BASE,
-	  .irq		= 15,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm405ep_emac0_def,
-	  .show		= &ocp_show_emac_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 1,
-	  .paddr	= 0xEF600900,
-	  .irq		= 17,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm405ep_emac1_def,
-	  .show		= &ocp_show_emac_data
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity 	= 0xffff7f80,
-	  .triggering	= 0x00000000,
-	  .ext_irq_mask	= 0x0000007f,	/* IRQ0 - IRQ6 */
-	}
-};
diff --git a/arch/ppc/platforms/4xx/ibm405ep.h b/arch/ppc/platforms/4xx/ibm405ep.h
deleted file mode 100644
index 3ef20a54708..00000000000
--- a/arch/ppc/platforms/4xx/ibm405ep.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * IBM PPC 405EP processor defines.
- *
- * Author: SAW (IBM), derived from ibm405gp.h.
- *         Maintained by MontaVista Software <source@mvista.com>
- *
- * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM405EP_H__
-#define __ASM_IBM405EP_H__
-
-
-/* ibm405.h at bottom of this file */
-
-/* PCI
- * PCI Bridge config reg definitions
- * see 17-19 of manual
- */
-
-#define PPC405_PCI_CONFIG_ADDR	0xeec00000
-#define PPC405_PCI_CONFIG_DATA	0xeec00004
-
-#define PPC405_PCI_PHY_MEM_BASE	0x80000000	/* hose_a->pci_mem_offset */
-						/* setbat */
-#define PPC405_PCI_MEM_BASE	PPC405_PCI_PHY_MEM_BASE	/* setbat */
-#define PPC405_PCI_PHY_IO_BASE	0xe8000000	/* setbat */
-#define PPC405_PCI_IO_BASE	PPC405_PCI_PHY_IO_BASE	/* setbat */
-
-#define PPC405_PCI_LOWER_MEM	0x80000000	/* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM	0xBfffffff	/* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO	0x00000000	/* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO	0x0000ffff	/* hose_a->io_space.end */
-
-#define PPC405_ISA_IO_BASE	PPC405_PCI_IO_BASE
-
-#define PPC4xx_PCI_IO_PADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR	PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR	PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR	PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
-
-/* serial port defines */
-#define RS_TABLE_SIZE	2
-
-#define UART0_INT	0
-#define UART1_INT	1
-
-#define PCIL0_BASE	0xEF400000
-#define UART0_IO_BASE	0xEF600300
-#define UART1_IO_BASE	0xEF600400
-#define EMAC0_BASE	0xEF600800
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
-
-#if defined(CONFIG_UART0_TTYS0)
-#define ACTING_UART0_IO_BASE	UART0_IO_BASE
-#define ACTING_UART1_IO_BASE	UART1_IO_BASE
-#define ACTING_UART0_INT	UART0_INT
-#define ACTING_UART1_INT	UART1_INT
-#else
-#define ACTING_UART0_IO_BASE	UART1_IO_BASE
-#define ACTING_UART1_IO_BASE	UART0_IO_BASE
-#define ACTING_UART0_INT	UART1_INT
-#define ACTING_UART1_INT	UART0_INT
-#endif
-
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, ACTING_UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (u8 *)ACTING_UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_DEBUG_IO_BASE	ACTING_UART0_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-
-/* DCR defines */
-#define DCRN_CPMSR_BASE         0x0BA
-#define DCRN_CPMFR_BASE         0x0B9
-
-#define DCRN_CPC0_PLLMR0_BASE   0x0F0
-#define DCRN_CPC0_BOOT_BASE     0x0F1
-#define DCRN_CPC0_CR1_BASE      0x0F2
-#define DCRN_CPC0_EPRCSR_BASE   0x0F3
-#define DCRN_CPC0_PLLMR1_BASE   0x0F4
-#define DCRN_CPC0_UCR_BASE      0x0F5
-#define DCRN_CPC0_UCR_U0DIV     0x07F
-#define DCRN_CPC0_SRR_BASE      0x0F6
-#define DCRN_CPC0_JTAGID_BASE   0x0F7
-#define DCRN_CPC0_SPARE_BASE    0x0F8
-#define DCRN_CPC0_PCI_BASE      0x0F9
-
-
-#define IBM_CPM_GPT             0x80000000      /* GPT interface */
-#define IBM_CPM_PCI             0x40000000      /* PCI bridge */
-#define IBM_CPM_UIC             0x00010000      /* Universal Int Controller */
-#define IBM_CPM_CPU             0x00008000      /* processor core */
-#define IBM_CPM_EBC             0x00002000      /* EBC controller */
-#define IBM_CPM_SDRAM0          0x00004000      /* SDRAM memory controller */
-#define IBM_CPM_GPIO0           0x00001000      /* General Purpose IO */
-#define IBM_CPM_TMRCLK          0x00000400      /* CPU timers */
-#define IBM_CPM_PLB             0x00000100      /* PLB bus arbiter */
-#define IBM_CPM_OPB             0x00000080      /* PLB to OPB bridge */
-#define IBM_CPM_DMA             0x00000040      /* DMA controller */
-#define IBM_CPM_IIC0            0x00000010      /* IIC interface */
-#define IBM_CPM_UART1           0x00000002      /* serial port 0 */
-#define IBM_CPM_UART0           0x00000001      /* serial port 1 */
-#define DFLT_IBM4xx_PM          ~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
-                                        | IBM_CPM_OPB | IBM_CPM_EBC \
-                                        | IBM_CPM_SDRAM0 | IBM_CPM_PLB \
-                                        | IBM_CPM_UIC | IBM_CPM_TMRCLK)
-#define DCRN_DMA0_BASE          0x100
-#define DCRN_DMA1_BASE          0x108
-#define DCRN_DMA2_BASE          0x110
-#define DCRN_DMA3_BASE          0x118
-#define DCRNCAP_DMA_SG          1       /* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE         0x120
-#define DCRN_EBC_BASE           0x012
-#define DCRN_DCP0_BASE          0x014
-#define DCRN_MAL_BASE           0x180
-#define DCRN_OCM0_BASE          0x018
-#define DCRN_PLB0_BASE          0x084
-#define DCRN_PLLMR_BASE         0x0B0
-#define DCRN_POB0_BASE          0x0A0
-#define DCRN_SDRAM0_BASE        0x010
-#define DCRN_UIC0_BASE          0x0C0
-#define UIC0 DCRN_UIC0_BASE
-
-#include <asm/ibm405.h>
-
-#endif				/* __ASM_IBM405EP_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gp.c b/arch/ppc/platforms/4xx/ibm405gp.c
deleted file mode 100644
index 2ac67a2f0ba..00000000000
--- a/arch/ppc/platforms/4xx/ibm405gp.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- *
- *    Copyright 2000-2001 MontaVista Software Inc.
- *      Original author: Armin Kuster akuster@mvista.com
- *
- *    Module name: ibm405gp.c
- *
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <platforms/4xx/ibm405gp.h>
-#include <asm/ibm4xx.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm405gp_emac0_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx	= -1,		/* ZMII device index */
-	.zmii_mux	= 0,		/* ZMII input of this EMAC */
-	.mal_idx	= 0,		/* MAL device index */
-	.mal_rx_chan	= 0,		/* MAL rx channel number */
-	.mal_tx_chan	= 0,		/* MAL tx channel number */
-	.wol_irq	= 9,		/* WOL interrupt number */
-	.mdio_idx	= -1,		/* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm405gp_mal0_def = {
-	.num_tx_chans	= 1,		/* Number of TX channels */
-	.num_rx_chans	= 1,		/* Number of RX channels */
-	.txeob_irq	= 11,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 12,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 13,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 14,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 10,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm405gp_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_OPB,
-	  .index	= 0,
-	  .paddr	= 0xEF600000,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= UART0_IO_BASE,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= UART1_IO_BASE,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .paddr	= 0xEF600500,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibm405gp_iic0_def,
-	  .show		= &ocp_show_iic_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .paddr	= 0xEF600700,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm405gp_mal0_def,
-	  .show		= &ocp_show_mal_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= EMAC0_BASE,
-	  .irq		= 15,
-	  .pm		= IBM_CPM_EMAC0,
-	  .additions	= &ibm405gp_emac0_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity 	= 0xffffff80,
-	  .triggering	= 0x10000000,
-	  .ext_irq_mask	= 0x0000007f,	/* IRQ0 - IRQ6 */
-	}
-};
diff --git a/arch/ppc/platforms/4xx/ibm405gp.h b/arch/ppc/platforms/4xx/ibm405gp.h
deleted file mode 100644
index 9f15e551871..00000000000
--- a/arch/ppc/platforms/4xx/ibm405gp.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Author: Armin Kuster akuster@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM405GP_H__
-#define __ASM_IBM405GP_H__
-
-
-/* ibm405.h at bottom of this file */
-
-/* PCI
- * PCI Bridge config reg definitions
- * see 17-19 of manual
- */
-
-#define PPC405_PCI_CONFIG_ADDR	0xeec00000
-#define PPC405_PCI_CONFIG_DATA	0xeec00004
-
-#define PPC405_PCI_PHY_MEM_BASE	0x80000000	/* hose_a->pci_mem_offset */
-						/* setbat */
-#define PPC405_PCI_MEM_BASE	PPC405_PCI_PHY_MEM_BASE	/* setbat */
-#define PPC405_PCI_PHY_IO_BASE	0xe8000000	/* setbat */
-#define PPC405_PCI_IO_BASE	PPC405_PCI_PHY_IO_BASE	/* setbat */
-
-#define PPC405_PCI_LOWER_MEM	0x80000000	/* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM	0xBfffffff	/* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO	0x00000000	/* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO	0x0000ffff	/* hose_a->io_space.end */
-
-#define PPC405_ISA_IO_BASE	PPC405_PCI_IO_BASE
-
-#define PPC4xx_PCI_IO_PADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR	PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR	PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR	PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
-
-/* serial port defines */
-#define RS_TABLE_SIZE	2
-
-#define UART0_INT	0
-#define UART1_INT	1
-
-#define PCIL0_BASE	0xEF400000
-#define UART0_IO_BASE	0xEF600300
-#define UART1_IO_BASE	0xEF600400
-#define EMAC0_BASE	0xEF600800
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (u8 *)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE	UART1_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(1)		\
-	STD_UART_OP(0)
-#endif
-
-/* DCR defines */
-#define DCRN_CHCR_BASE		0x0B1
-#define DCRN_CHPSR_BASE		0x0B4
-#define DCRN_CPMSR_BASE		0x0B8
-#define DCRN_CPMFR_BASE		0x0BA
-
-#define CHR0_U0EC	0x00000080	/* Select external clock for UART0 */
-#define CHR0_U1EC	0x00000040	/* Select external clock for UART1 */
-#define CHR0_UDIV	0x0000003E	/* UART internal clock divisor */
-#define CHR1_CETE	0x00800000	/* CPU external timer enable */
-
-#define DCRN_CHPSR_BASE         0x0B4
-#define  PSR_PLL_FWD_MASK        0xC0000000
-#define  PSR_PLL_FDBACK_MASK     0x30000000
-#define  PSR_PLL_TUNING_MASK     0x0E000000
-#define  PSR_PLB_CPU_MASK        0x01800000
-#define  PSR_OPB_PLB_MASK        0x00600000
-#define  PSR_PCI_PLB_MASK        0x00180000
-#define  PSR_EB_PLB_MASK         0x00060000
-#define  PSR_ROM_WIDTH_MASK      0x00018000
-#define  PSR_ROM_LOC             0x00004000
-#define  PSR_PCI_ASYNC_EN        0x00001000
-#define  PSR_PCI_ARBIT_EN        0x00000400
-
-#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
-#define IBM_CPM_PCI		0x40000000	/* PCI bridge */
-#define IBM_CPM_CPU		0x20000000	/* processor core */
-#define IBM_CPM_DMA		0x10000000	/* DMA controller */
-#define IBM_CPM_OPB		0x08000000	/* PLB to OPB bridge */
-#define IBM_CPM_DCP		0x04000000	/* CodePack */
-#define IBM_CPM_EBC		0x02000000	/* ROM/SRAM peripheral controller */
-#define IBM_CPM_SDRAM0		0x01000000	/* SDRAM memory controller */
-#define IBM_CPM_PLB		0x00800000	/* PLB bus arbiter */
-#define IBM_CPM_GPIO0		0x00400000	/* General Purpose IO (??) */
-#define IBM_CPM_UART0		0x00200000	/* serial port 0 */
-#define IBM_CPM_UART1		0x00100000	/* serial port 1 */
-#define IBM_CPM_UIC		0x00080000	/* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK		0x00040000	/* CPU timers */
-#define IBM_CPM_EMAC0		0x00020000	/* on-chip ethernet MM unit */
-#define DFLT_IBM4xx_PM		~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
-					| IBM_CPM_OPB | IBM_CPM_EBC \
-					| IBM_CPM_SDRAM0 | IBM_CPM_PLB \
-					| IBM_CPM_UIC | IBM_CPM_TMRCLK)
-
-#define DCRN_DMA0_BASE		0x100
-#define DCRN_DMA1_BASE		0x108
-#define DCRN_DMA2_BASE		0x110
-#define DCRN_DMA3_BASE		0x118
-#define DCRNCAP_DMA_SG		1	/* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE		0x120
-#define DCRN_EBC_BASE		0x012
-#define DCRN_DCP0_BASE		0x014
-#define DCRN_MAL_BASE		0x180
-#define DCRN_OCM0_BASE		0x018
-#define DCRN_PLB0_BASE		0x084
-#define DCRN_PLLMR_BASE		0x0B0
-#define DCRN_POB0_BASE		0x0A0
-#define DCRN_SDRAM0_BASE	0x010
-#define DCRN_UIC0_BASE		0x0C0
-#define UIC0 DCRN_UIC0_BASE
-
-#include <asm/ibm405.h>
-
-#endif				/* __ASM_IBM405GP_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.c b/arch/ppc/platforms/4xx/ibm405gpr.c
deleted file mode 100644
index 9f4dacffdbb..00000000000
--- a/arch/ppc/platforms/4xx/ibm405gpr.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <platforms/4xx/ibm405gpr.h>
-#include <asm/ibm4xx.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm405gpr_emac0_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx	= -1,		/* ZMII device index */
-	.zmii_mux	= 0,		/* ZMII input of this EMAC */
-	.mal_idx	= 0,		/* MAL device index */
-	.mal_rx_chan	= 0,		/* MAL rx channel number */
-	.mal_tx_chan	= 0,		/* MAL tx channel number */
-	.wol_irq	= 9,		/* WOL interrupt number */
-	.mdio_idx	= -1,		/* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm405gpr_mal0_def = {
-	.num_tx_chans	= 1,		/* Number of TX channels */
-	.num_rx_chans	= 1,		/* Number of RX channels */
-	.txeob_irq	= 11,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 12,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 13,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 14,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 10,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm405gpr_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_OPB,
-	  .index	= 0,
-	  .paddr	= 0xEF600000,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= UART0_IO_BASE,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= UART1_IO_BASE,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .paddr	= 0xEF600500,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibm405gpr_iic0_def,
-	  .show		= &ocp_show_iic_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .paddr	= 0xEF600700,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm405gpr_mal0_def,
-	  .show		= &ocp_show_mal_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= EMAC0_BASE,
-	  .irq		= 15,
-	  .pm		= IBM_CPM_EMAC0,
-	  .additions	= &ibm405gpr_emac0_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity 	= 0xffffe000,
-	  .triggering	= 0x10000000,
-	  .ext_irq_mask	= 0x00001fff,	/* IRQ7 - IRQ12, IRQ0 - IRQ6 */
-	}
-};
diff --git a/arch/ppc/platforms/4xx/ibm405gpr.h b/arch/ppc/platforms/4xx/ibm405gpr.h
deleted file mode 100644
index 9e01f1515de..00000000000
--- a/arch/ppc/platforms/4xx/ibm405gpr.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBM405GPR_H__
-#define __ASM_IBM405GPR_H__
-
-
-/* ibm405.h at bottom of this file */
-
-/* PCI
- * PCI Bridge config reg definitions
- * see 17-19 of manual
- */
-
-#define PPC405_PCI_CONFIG_ADDR	0xeec00000
-#define PPC405_PCI_CONFIG_DATA	0xeec00004
-
-#define PPC405_PCI_PHY_MEM_BASE	0x80000000	/* hose_a->pci_mem_offset */
-						/* setbat */
-#define PPC405_PCI_MEM_BASE	PPC405_PCI_PHY_MEM_BASE	/* setbat */
-#define PPC405_PCI_PHY_IO_BASE	0xe8000000	/* setbat */
-#define PPC405_PCI_IO_BASE	PPC405_PCI_PHY_IO_BASE	/* setbat */
-
-#define PPC405_PCI_LOWER_MEM	0x80000000	/* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM	0xBfffffff	/* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO	0x00000000	/* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO	0x0000ffff	/* hose_a->io_space.end */
-
-#define PPC405_ISA_IO_BASE	PPC405_PCI_IO_BASE
-
-#define PPC4xx_PCI_IO_PADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_VADDR	PPC4xx_PCI_IO_PADDR
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_PADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_VADDR	PPC4xx_PCI_CFG_PADDR
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_PADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_VADDR	PPC4xx_PCI_LCFG_PADDR
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_PADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_VADDR	PPC4xx_ONB_IO_PADDR
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
-
-/* serial port defines */
-#define RS_TABLE_SIZE	2
-
-#define UART0_INT	0
-#define UART1_INT	1
-
-#define PCIL0_BASE	0xEF400000
-#define UART0_IO_BASE	0xEF600300
-#define UART1_IO_BASE	0xEF600400
-#define EMAC0_BASE	0xEF600800
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (u8 *)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE	UART1_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(1)		\
-	STD_UART_OP(0)
-#endif
-
-/* DCR defines */
-#define DCRN_CHCR_BASE		0x0B1
-#define DCRN_CHPSR_BASE		0x0B4
-#define DCRN_CPMSR_BASE		0x0B8
-#define DCRN_CPMFR_BASE		0x0BA
-
-#define CHR0_U0EC	0x00000080	/* Select external clock for UART0 */
-#define CHR0_U1EC	0x00000040	/* Select external clock for UART1 */
-#define CHR0_UDIV	0x0000003E	/* UART internal clock divisor */
-#define CHR1_CETE	0x00800000	/* CPU external timer enable */
-
-#define DCRN_CHPSR_BASE         0x0B4
-#define  PSR_PLL_FWD_MASK        0xC0000000
-#define  PSR_PLL_FDBACK_MASK     0x30000000
-#define  PSR_PLL_TUNING_MASK     0x0E000000
-#define  PSR_PLB_CPU_MASK        0x01800000
-#define  PSR_OPB_PLB_MASK        0x00600000
-#define  PSR_PCI_PLB_MASK        0x00180000
-#define  PSR_EB_PLB_MASK         0x00060000
-#define  PSR_ROM_WIDTH_MASK      0x00018000
-#define  PSR_ROM_LOC             0x00004000
-#define  PSR_PCI_ASYNC_EN        0x00001000
-#define  PSR_PCI_ARBIT_EN        0x00000400
-
-#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
-#define IBM_CPM_PCI		0x40000000	/* PCI bridge */
-#define IBM_CPM_CPU		0x20000000	/* processor core */
-#define IBM_CPM_DMA		0x10000000	/* DMA controller */
-#define IBM_CPM_OPB		0x08000000	/* PLB to OPB bridge */
-#define IBM_CPM_DCP		0x04000000	/* CodePack */
-#define IBM_CPM_EBC		0x02000000	/* ROM/SRAM peripheral controller */
-#define IBM_CPM_SDRAM0		0x01000000	/* SDRAM memory controller */
-#define IBM_CPM_PLB		0x00800000	/* PLB bus arbiter */
-#define IBM_CPM_GPIO0		0x00400000	/* General Purpose IO (??) */
-#define IBM_CPM_UART0		0x00200000	/* serial port 0 */
-#define IBM_CPM_UART1		0x00100000	/* serial port 1 */
-#define IBM_CPM_UIC		0x00080000	/* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK		0x00040000	/* CPU timers */
-#define IBM_CPM_EMAC0		0x00020000	/* on-chip ethernet MM unit */
-#define DFLT_IBM4xx_PM		~(IBM_CPM_PCI | IBM_CPM_CPU | IBM_CPM_DMA \
-					| IBM_CPM_OPB | IBM_CPM_EBC \
-					| IBM_CPM_SDRAM0 | IBM_CPM_PLB \
-					| IBM_CPM_UIC | IBM_CPM_TMRCLK)
-
-#define DCRN_DMA0_BASE		0x100
-#define DCRN_DMA1_BASE		0x108
-#define DCRN_DMA2_BASE		0x110
-#define DCRN_DMA3_BASE		0x118
-#define DCRNCAP_DMA_SG		1	/* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE		0x120
-#define DCRN_EBC_BASE		0x012
-#define DCRN_DCP0_BASE		0x014
-#define DCRN_MAL_BASE		0x180
-#define DCRN_OCM0_BASE		0x018
-#define DCRN_PLB0_BASE		0x084
-#define DCRN_PLLMR_BASE		0x0B0
-#define DCRN_POB0_BASE		0x0A0
-#define DCRN_SDRAM0_BASE	0x010
-#define DCRN_UIC0_BASE		0x0C0
-#define UIC0 DCRN_UIC0_BASE
-
-#include <asm/ibm405.h>
-
-#endif				/* __ASM_IBM405GPR_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440ep.c b/arch/ppc/platforms/4xx/ibm440ep.c
deleted file mode 100644
index 0de91532aab..00000000000
--- a/arch/ppc/platforms/4xx/ibm440ep.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * PPC440EP I/O descriptions
- *
- * Wade Farnsworth <wfarnsworth@mvista.com>
- * Copyright 2004 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <platforms/4xx/ibm440ep.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm440ep_emac0_def = {
-	.rgmii_idx	= -1,           /* No RGMII */
-	.rgmii_mux	= -1,           /* No RGMII */
-	.zmii_idx       = 0,            /* ZMII device index */
-	.zmii_mux       = 0,            /* ZMII input of this EMAC */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 0,            /* MAL rx channel number */
-	.mal_tx_chan    = 0,            /* MAL tx channel number */
-	.wol_irq        = 61,		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= -1,           /* No TAH */
-};
-
-static struct ocp_func_emac_data ibm440ep_emac1_def = {
-	.rgmii_idx	= -1,           /* No RGMII */
-	.rgmii_mux	= -1,           /* No RGMII */
-	.zmii_idx       = 0,            /* ZMII device index */
-	.zmii_mux       = 1,            /* ZMII input of this EMAC */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 1,            /* MAL rx channel number */
-	.mal_tx_chan    = 2,            /* MAL tx channel number */
-	.wol_irq        = 63,  		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= -1,           /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm440ep_mal0_def = {
-	.num_tx_chans   = 4,  		/* Number of TX channels */
-	.num_rx_chans   = 2,    	/* Number of RX channels */
-	.txeob_irq	= 10,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 11,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 33,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 34,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 32,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm440ep_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibm440ep_iic1_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_OPB,
-	  .index	= 0,
-	  .paddr	= 0x0EF600000ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= PPC440EP_UART0_ADDR,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= PPC440EP_UART1_ADDR,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 2,
-	  .paddr	= PPC440EP_UART2_ADDR,
-	  .irq		= UART2_INT,
-	  .pm		= IBM_CPM_UART2,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 3,
-	  .paddr	= PPC440EP_UART3_ADDR,
-	  .irq		= UART3_INT,
-	  .pm		= IBM_CPM_UART3,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 0,
-	  .paddr	= 0x0EF600700ULL,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibm440ep_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 1,
-	  .paddr	= 0x0EF600800ULL,
-	  .irq		= 7,
-	  .pm		= IBM_CPM_IIC1,
-	  .additions	= &ibm440ep_iic1_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .index	= 0,
-	  .paddr	= 0x0EF600B00ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .index	= 1,
-	  .paddr	= 0x0EF600C00ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440ep_mal0_def,
-	  .show		= &ocp_show_mal_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= 0x0EF600E00ULL,
-	  .irq		= 60,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440ep_emac0_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 1,
-	  .paddr	= 0x0EF600F00ULL,
-	  .irq		= 62,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440ep_emac1_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_ZMII,
-	  .paddr	= 0x0EF600D00ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity	= 0xffbffe03,
-	  .triggering   = 0x00000000,
-	  .ext_irq_mask = 0x000001fc,	/* IRQ0 - IRQ6 */
-	},
-	{ .polarity	= 0xffffc6af,
-	  .triggering	= 0x06000140,
-	  .ext_irq_mask = 0x00003800,	/* IRQ7 - IRQ9 */
-	},
-};
-
-static struct resource usb_gadget_resources[] = {
-	[0] = {
-		.start	= 0x050000100ULL,
-		.end 	= 0x05000017FULL,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= 55,
-		.end	= 55,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static u64 dma_mask = 0xffffffffULL;
-
-static struct platform_device usb_gadget_device = {
-	.name		= "musbhsfc",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(usb_gadget_resources),
-	.resource       = usb_gadget_resources,
-	.dev		= {
-		.dma_mask = &dma_mask,
-		.coherent_dma_mask = 0xffffffffULL,
-	}
-};
-
-static struct platform_device *ibm440ep_devs[] __initdata = {
-	&usb_gadget_device,
-};
-
-static int __init
-ibm440ep_platform_add_devices(void)
-{
-	return platform_add_devices(ibm440ep_devs, ARRAY_SIZE(ibm440ep_devs));
-}
-arch_initcall(ibm440ep_platform_add_devices);
-
diff --git a/arch/ppc/platforms/4xx/ibm440ep.h b/arch/ppc/platforms/4xx/ibm440ep.h
deleted file mode 100644
index d92572727d2..00000000000
--- a/arch/ppc/platforms/4xx/ibm440ep.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * PPC440EP definitions
- *
- * Wade Farnsworth <wfarnsworth@mvista.com>
- *
- * Copyright 2002 Roland Dreier
- * Copyright 2004 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_IBM440EP_H
-#define __PPC_PLATFORMS_IBM440EP_H
-
-#include <asm/ibm44x.h>
-
-/* UART */
-#define PPC440EP_UART0_ADDR		0x0EF600300
-#define PPC440EP_UART1_ADDR		0x0EF600400
-#define PPC440EP_UART2_ADDR		0x0EF600500
-#define PPC440EP_UART3_ADDR		0x0EF600600
-#define UART0_INT			0
-#define UART1_INT			1
-#define UART2_INT			3
-#define UART3_INT			4
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
-#define IBM_CPM_IIC1		0x40000000	/* IIC interface */
-#define IBM_CPM_PCI		0x20000000	/* PCI bridge */
-#define IBM_CPM_USB1H		0x08000000	/* USB 1.1 Host */
-#define IBM_CPM_FPU		0x04000000	/* floating point unit */
-#define IBM_CPM_CPU		0x02000000	/* processor core */
-#define IBM_CPM_DMA		0x01000000	/* DMA controller */
-#define IBM_CPM_BGO		0x00800000	/* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI		0x00400000	/* OPB to PLB bridge */
-#define IBM_CPM_EBC		0x00200000	/* External Bus Controller */
-#define IBM_CPM_EBM		0x00100000	/* Ext Bus Master Interface */
-#define IBM_CPM_DMC		0x00080000	/* SDRAM peripheral controller */
-#define IBM_CPM_PLB4		0x00040000	/* PLB4 bus arbiter */
-#define IBM_CPM_PLB4x3		0x00020000	/* PLB4 to PLB3 bridge controller */
-#define IBM_CPM_PLB3x4		0x00010000	/* PLB3 to PLB4 bridge controller */
-#define IBM_CPM_PLB3		0x00008000	/* PLB3 bus arbiter */
-#define IBM_CPM_PPM		0x00002000	/* PLB Performance Monitor */
-#define IBM_CPM_UIC1		0x00001000	/* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0		0x00000800	/* General Purpose IO (??) */
-#define IBM_CPM_GPT		0x00000400	/* General Purpose Timers  */
-#define IBM_CPM_UART0		0x00000200	/* serial port 0 */
-#define IBM_CPM_UART1		0x00000100	/* serial port 1 */
-#define IBM_CPM_UIC0		0x00000080	/* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK		0x00000040	/* CPU timers */
-#define IBM_CPM_EMAC0		0x00000020	/* ethernet port 0 */
-#define IBM_CPM_EMAC1		0x00000010	/* ethernet port 1 */
-#define IBM_CPM_UART2		0x00000008	/* serial port 2 */
-#define IBM_CPM_UART3		0x00000004	/* serial port 3 */
-#define IBM_CPM_USB2D		0x00000002	/* USB 2.0 Device */
-#define IBM_CPM_USB2H		0x00000001	/* USB 2.0 Host */
-
-#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU \
-				| IBM_CPM_EBC | IBM_CPM_BGO | IBM_CPM_FPU \
-				| IBM_CPM_EBM | IBM_CPM_PLB4 | IBM_CPM_3x4 \
-				| IBM_CPM_PLB3 | IBM_CPM_PLB4x3 \
-				| IBM_CPM_EMAC0 | IBM_CPM_TMRCLK \
-				| IBM_CPM_DMA | IBM_CPM_PCI | IBM_CPM_EMAC1)
-
-
-#endif /* __PPC_PLATFORMS_IBM440EP_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gp.c b/arch/ppc/platforms/4xx/ibm440gp.c
deleted file mode 100644
index b67a72e5c6f..00000000000
--- a/arch/ppc/platforms/4xx/ibm440gp.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * PPC440GP I/O descriptions
- *
- * Matt Porter <mporter@mvista.com>
- * Copyright 2002-2004 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <platforms/4xx/ibm440gp.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm440gp_emac0_def = {
-	.rgmii_idx	= -1,           /* No RGMII */
-	.rgmii_mux	= -1,           /* No RGMII */
-	.zmii_idx       = 0,            /* ZMII device index */
-	.zmii_mux       = 0,            /* ZMII input of this EMAC */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 0,            /* MAL rx channel number */
-	.mal_tx_chan    = 0,            /* MAL tx channel number */
-	.wol_irq        = 61,		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= -1,           /* No TAH */
-};
-
-static struct ocp_func_emac_data ibm440gp_emac1_def = {
-	.rgmii_idx	= -1,           /* No RGMII */
-	.rgmii_mux	= -1,           /* No RGMII */
-	.zmii_idx       = 0,            /* ZMII device index */
-	.zmii_mux       = 1,            /* ZMII input of this EMAC */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 1,            /* MAL rx channel number */
-	.mal_tx_chan    = 2,            /* MAL tx channel number */
-	.wol_irq        = 63,  		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= -1,           /* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm440gp_mal0_def = {
-	.num_tx_chans   = 4,  		/* Number of TX channels */
-	.num_rx_chans   = 2,    	/* Number of RX channels */
-	.txeob_irq	= 10,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 11,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 33,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 34,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 32,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm440gp_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibm440gp_iic1_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_OPB,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000000ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= PPC440GP_UART0_ADDR,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= PPC440GP_UART1_ADDR,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000400ULL,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibm440gp_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 1,
-	  .paddr	= 0x0000000140000500ULL,
-	  .irq		= 3,
-	  .pm		= IBM_CPM_IIC1,
-	  .additions	= &ibm440gp_iic1_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000700ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440gp_mal0_def,
-	  .show		= &ocp_show_mal_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000800ULL,
-	  .irq		= 60,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440gp_emac0_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 1,
-	  .paddr	= 0x0000000140000900ULL,
-	  .irq		= 62,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440gp_emac1_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_ZMII,
-	  .paddr	= 0x0000000140000780ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity 	= 0xfffffe03,
-	  .triggering	= 0x01c00000,
-	  .ext_irq_mask	= 0x000001fc,	/* IRQ0 - IRQ6 */
-	},
-	{ .polarity 	= 0xffffc0ff,
-	  .triggering	= 0x00ff8000,
-	  .ext_irq_mask	= 0x00003f00,	/* IRQ7 - IRQ12 */
-	},
-};
diff --git a/arch/ppc/platforms/4xx/ibm440gp.h b/arch/ppc/platforms/4xx/ibm440gp.h
deleted file mode 100644
index 391c90e1f5e..00000000000
--- a/arch/ppc/platforms/4xx/ibm440gp.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * PPC440GP definitions
- *
- * Roland Dreier <roland@digitalvampire.org>
- *
- * Copyright 2002 Roland Dreier
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- * This file contains code that was originally in the files ibm44x.h
- * and ebony.h, which were written by Matt Porter of MontaVista Software Inc.
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_IBM440GP_H
-#define __PPC_PLATFORMS_IBM440GP_H
-
-
-/* UART */
-#define PPC440GP_UART0_ADDR	0x0000000140000200ULL
-#define PPC440GP_UART1_ADDR	0x0000000140000300ULL
-#define UART0_INT		0
-#define UART1_INT		1
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
-#define IBM_CPM_IIC1		0x40000000	/* IIC interface */
-#define IBM_CPM_PCI		0x20000000	/* PCI bridge */
-#define IBM_CPM_CPU		0x02000000	/* processor core */
-#define IBM_CPM_DMA		0x01000000	/* DMA controller */
-#define IBM_CPM_BGO		0x00800000	/* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI		0x00400000	/* OPB to PLB bridge */
-#define IBM_CPM_EBC		0x00200000	/* External Bux Controller */
-#define IBM_CPM_EBM		0x00100000	/* Ext Bus Master Interface */
-#define IBM_CPM_DMC		0x00080000	/* SDRAM peripheral controller */
-#define IBM_CPM_PLB		0x00040000	/* PLB bus arbiter */
-#define IBM_CPM_SRAM		0x00020000	/* SRAM memory controller */
-#define IBM_CPM_PPM		0x00002000	/* PLB Performance Monitor */
-#define IBM_CPM_UIC1		0x00001000	/* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0		0x00000800	/* General Purpose IO (??) */
-#define IBM_CPM_GPT		0x00000400	/* General Purpose Timers  */
-#define IBM_CPM_UART0		0x00000200	/* serial port 0 */
-#define IBM_CPM_UART1		0x00000100	/* serial port 1 */
-#define IBM_CPM_UIC0		0x00000080	/* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK		0x00000040	/* CPU timers */
-
-#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
-				| IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
-				| IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
-				| IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI)
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE	2
-
-#include <asm/ibm44x.h>
-#include <syslib/ibm440gp_common.h>
-
-#endif /* __PPC_PLATFORMS_IBM440GP_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440gx.c b/arch/ppc/platforms/4xx/ibm440gx.c
deleted file mode 100644
index 685abffcb6c..00000000000
--- a/arch/ppc/platforms/4xx/ibm440gx.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * PPC440GX I/O descriptions
- *
- * Matt Porter <mporter@mvista.com>
- * Copyright 2002-2004 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <platforms/4xx/ibm440gx.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ibm440gx_emac0_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx       = 0,            /* ZMII device index */
-	.zmii_mux       = 0,            /* ZMII input of this EMAC */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 0,            /* MAL rx channel number */
-	.mal_tx_chan    = 0,            /* MAL tx channel number */
-	.wol_irq        = 61,   	/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-
-static struct ocp_func_emac_data ibm440gx_emac1_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx       = 0,            /* ZMII device index */
-	.zmii_mux       = 1,            /* ZMII input of this EMAC */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 1,            /* MAL rx channel number */
-	.mal_tx_chan    = 1,            /* MAL tx channel number */
-	.wol_irq        = 63,  		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-
-static struct ocp_func_emac_data ibm440gx_emac2_def = {
-	.rgmii_idx	= 0,		/* RGMII device index */
-	.rgmii_mux	= 0,		/* RGMII input of this EMAC */
-	.zmii_idx       = 0,            /* ZMII device index */
-	.zmii_mux       = 2,            /* ZMII input of this EMAC */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 2,            /* MAL rx channel number */
-	.mal_tx_chan    = 2,            /* MAL tx channel number */
-	.wol_irq        = 65,  		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= 0,		/* TAH device index */
-};
-
-static struct ocp_func_emac_data ibm440gx_emac3_def = {
-	.rgmii_idx	= 0,		/* RGMII device index */
-	.rgmii_mux	= 1,		/* RGMII input of this EMAC */
-	.zmii_idx       = 0,            /* ZMII device index */
-	.zmii_mux       = 3,            /* ZMII input of this EMAC */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 3,            /* MAL rx channel number */
-	.mal_tx_chan    = 3,            /* MAL tx channel number */
-	.wol_irq        = 67,  		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= 1,		/* TAH device index */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm440gx_mal0_def = {
-	.num_tx_chans   = 4,    	/* Number of TX channels */
-	.num_rx_chans   = 4,    	/* Number of RX channels */
-	.txeob_irq	= 10,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 11,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 33,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 34,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 32,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm440gx_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibm440gx_iic1_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_OPB,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000000ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= PPC440GX_UART0_ADDR,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= PPC440GX_UART1_ADDR,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000400ULL,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibm440gx_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 1,
-	  .paddr	= 0x0000000140000500ULL,
-	  .irq		= 3,
-	  .pm		= IBM_CPM_IIC1,
-	  .additions	= &ibm440gx_iic1_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000700ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440gx_mal0_def,
-	  .show		= &ocp_show_mal_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000800ULL,
-	  .irq		= 60,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440gx_emac0_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 1,
-	  .paddr	= 0x0000000140000900ULL,
-	  .irq		= 62,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440gx_emac1_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 2,
-	  .paddr	= 0x0000000140000C00ULL,
-	  .irq		= 64,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440gx_emac2_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 3,
-	  .paddr	= 0x0000000140000E00ULL,
-	  .irq		= 66,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440gx_emac3_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_RGMII,
-	  .paddr	= 0x0000000140000790ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_ZMII,
-	  .paddr	= 0x0000000140000780ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_TAH,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000b50ULL,
-	  .irq		= 68,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_TAH,
-	  .index	= 1,
-	  .paddr	= 0x0000000140000d50ULL,
-	  .irq		= 69,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity 	= 0xfffffe03,
-	  .triggering	= 0x01c00000,
-	  .ext_irq_mask	= 0x000001fc,	/* IRQ0 - IRQ6 */
-	},
-	{ .polarity 	= 0xffffc0ff,
-	  .triggering	= 0x00ff8000,
-	  .ext_irq_mask	= 0x00003f00,	/* IRQ7 - IRQ12 */
-	},
-	{ .polarity 	= 0xffff83ff,
-	  .triggering	= 0x000f83c0,
-	  .ext_irq_mask	= 0x00007c00,	/* IRQ13 - IRQ17 */
-	},
-};
diff --git a/arch/ppc/platforms/4xx/ibm440gx.h b/arch/ppc/platforms/4xx/ibm440gx.h
deleted file mode 100644
index 599c4289b9c..00000000000
--- a/arch/ppc/platforms/4xx/ibm440gx.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * PPC440GX definitions
- *
- * Matt Porter <mporter@mvista.com>
- *
- * Copyright 2002 Roland Dreier
- * Copyright 2003 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_IBM440GX_H
-#define __PPC_PLATFORMS_IBM440GX_H
-
-
-#include <asm/ibm44x.h>
-
-/* UART */
-#define PPC440GX_UART0_ADDR	0x0000000140000200ULL
-#define PPC440GX_UART1_ADDR	0x0000000140000300ULL
-#define UART0_INT		0
-#define UART1_INT		1
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
-#define IBM_CPM_IIC1		0x40000000	/* IIC interface */
-#define IBM_CPM_PCI		0x20000000	/* PCI bridge */
-#define IBM_CPM_RGMII		0x10000000	/* RGMII */
-#define IBM_CPM_TAHOE0		0x08000000	/* TAHOE 0 */
-#define IBM_CPM_TAHOE1		0x04000000	/* TAHOE 1 */
-#define IBM_CPM_CPU		    0x02000000	/* processor core */
-#define IBM_CPM_DMA		    0x01000000	/* DMA controller */
-#define IBM_CPM_BGO		    0x00800000	/* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI		    0x00400000	/* OPB to PLB bridge */
-#define IBM_CPM_EBC		    0x00200000	/* External Bux Controller */
-#define IBM_CPM_EBM		    0x00100000	/* Ext Bus Master Interface */
-#define IBM_CPM_DMC		    0x00080000	/* SDRAM peripheral controller */
-#define IBM_CPM_PLB		    0x00040000	/* PLB bus arbiter */
-#define IBM_CPM_SRAM		0x00020000	/* SRAM memory controller */
-#define IBM_CPM_PPM		    0x00002000	/* PLB Performance Monitor */
-#define IBM_CPM_UIC1		0x00001000	/* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0		0x00000800	/* General Purpose IO (??) */
-#define IBM_CPM_GPT		    0x00000400	/* General Purpose Timers  */
-#define IBM_CPM_UART0		0x00000200	/* serial port 0 */
-#define IBM_CPM_UART1		0x00000100	/* serial port 1 */
-#define IBM_CPM_UIC0		0x00000080	/* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK		0x00000040	/* CPU timers */
-#define IBM_CPM_EMAC0  		0x00000020	/* EMAC 0     */
-#define IBM_CPM_EMAC1  		0x00000010	/* EMAC 1     */
-#define IBM_CPM_EMAC2  		0x00000008	/* EMAC 2     */
-#define IBM_CPM_EMAC3  		0x00000004	/* EMAC 3     */
-
-#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
-				| IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
-				| IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
-				| IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
-				| IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
-				| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
-			  	| IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE	2
-
-#endif /* __PPC_PLATFORMS_IBM440GX_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibm440sp.c b/arch/ppc/platforms/4xx/ibm440sp.c
deleted file mode 100644
index de8f7ac5623..00000000000
--- a/arch/ppc/platforms/4xx/ibm440sp.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * PPC440SP I/O descriptions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <platforms/4xx/ibm440sp.h>
-#include <asm/ocp.h>
-
-static struct ocp_func_emac_data ibm440sp_emac0_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx       = -1,           /* No ZMII */
-	.zmii_mux       = -1,           /* No ZMII */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 0,            /* MAL rx channel number */
-	.mal_tx_chan    = 0,            /* MAL tx channel number */
-	.wol_irq        = 61,  		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibm440sp_mal0_def = {
-	.num_tx_chans   = 1,    	/* Number of TX channels */
-	.num_rx_chans   = 1,    	/* Number of RX channels */
-	.txeob_irq	= 38,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 39,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 34,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 35,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 33,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibm440sp_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibm440sp_iic1_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_OPB,
-	  .index	= 0,
-	  .paddr	= 0x0000000140000000ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= PPC440SP_UART0_ADDR,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= PPC440SP_UART1_ADDR,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 2,
-	  .paddr	= PPC440SP_UART2_ADDR,
-	  .irq		= UART2_INT,
-	  .pm		= IBM_CPM_UART2,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 0,
-	  .paddr	= 0x00000001f0000400ULL,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibm440sp_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 1,
-	  .paddr	= 0x00000001f0000500ULL,
-	  .irq		= 3,
-	  .pm		= IBM_CPM_IIC1,
-	  .additions	= &ibm440sp_iic1_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .index	= 0,
-	  .paddr	= 0x00000001f0000700ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440sp_mal0_def,
-	  .show		= &ocp_show_mal_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= 0x00000001f0000800ULL,
-	  .irq		= 60,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibm440sp_emac0_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
diff --git a/arch/ppc/platforms/4xx/ibm440sp.h b/arch/ppc/platforms/4xx/ibm440sp.h
deleted file mode 100644
index 2978682f172..00000000000
--- a/arch/ppc/platforms/4xx/ibm440sp.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * PPC440SP definitions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2004-2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_IBM440SP_H
-#define __PPC_PLATFORMS_IBM440SP_H
-
-
-#include <asm/ibm44x.h>
-
-/* UART */
-#define PPC440SP_UART0_ADDR	0x00000001f0000200ULL
-#define PPC440SP_UART1_ADDR	0x00000001f0000300ULL
-#define PPC440SP_UART2_ADDR	0x00000001f0000600ULL
-#define UART0_INT		0
-#define UART1_INT		1
-#define UART2_INT		2
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
-#define IBM_CPM_IIC1		0x40000000	/* IIC interface */
-#define IBM_CPM_PCI		0x20000000	/* PCI bridge */
-#define IBM_CPM_CPU		    0x02000000	/* processor core */
-#define IBM_CPM_DMA		    0x01000000	/* DMA controller */
-#define IBM_CPM_BGO		    0x00800000	/* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI		    0x00400000	/* OPB to PLB bridge */
-#define IBM_CPM_EBC		    0x00200000	/* External Bux Controller */
-#define IBM_CPM_EBM		    0x00100000	/* Ext Bus Master Interface */
-#define IBM_CPM_DMC		    0x00080000	/* SDRAM peripheral controller */
-#define IBM_CPM_PLB		    0x00040000	/* PLB bus arbiter */
-#define IBM_CPM_SRAM		0x00020000	/* SRAM memory controller */
-#define IBM_CPM_PPM		    0x00002000	/* PLB Performance Monitor */
-#define IBM_CPM_UIC1		0x00001000	/* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0		0x00000800	/* General Purpose IO (??) */
-#define IBM_CPM_GPT		    0x00000400	/* General Purpose Timers  */
-#define IBM_CPM_UART0		0x00000200	/* serial port 0 */
-#define IBM_CPM_UART1		0x00000100	/* serial port 1 */
-#define IBM_CPM_UART2		0x00000100	/* serial port 1 */
-#define IBM_CPM_UIC0		0x00000080	/* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK		0x00000040	/* CPU timers */
-#define IBM_CPM_EMAC0  		0x00000020	/* EMAC 0     */
-
-#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
-				| IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
-				| IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
-				| IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
-				| IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
-				| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
-			  	| IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
-#endif /* __PPC_PLATFORMS_IBM440SP_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.c b/arch/ppc/platforms/4xx/ibmnp405h.c
deleted file mode 100644
index 1afc3642e5b..00000000000
--- a/arch/ppc/platforms/4xx/ibmnp405h.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <asm/ocp.h>
-#include <platforms/4xx/ibmnp405h.h>
-
-static struct ocp_func_emac_data ibmnp405h_emac0_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx	= 0,		/* ZMII device index */
-	.zmii_mux	= 0,		/* ZMII input of this EMAC */
-	.mal_idx	= 0,		/* MAL device index */
-	.mal_rx_chan	= 0,		/* MAL rx channel number */
-	.mal_tx_chan	= 0,		/* MAL tx channel number */
-	.wol_irq	= 41,		/* WOL interrupt number */
-	.mdio_idx	= -1,		/* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-
-static struct ocp_func_emac_data ibmnp405h_emac1_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx	= 0,		/* ZMII device index */
-	.zmii_mux	= 1,		/* ZMII input of this EMAC */
-	.mal_idx	= 0,		/* MAL device index */
-	.mal_rx_chan	= 1,		/* MAL rx channel number */
-	.mal_tx_chan	= 2,		/* MAL tx channel number */
-	.wol_irq	= 41,		/* WOL interrupt number */
-	.mdio_idx	= -1,		/* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-static struct ocp_func_emac_data ibmnp405h_emac2_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx	= 0,		/* ZMII device index */
-	.zmii_mux	= 2,		/* ZMII input of this EMAC */
-	.mal_idx	= 0,		/* MAL device index */
-	.mal_rx_chan	= 2,		/* MAL rx channel number */
-	.mal_tx_chan	= 4,		/* MAL tx channel number */
-	.wol_irq	= 41,		/* WOL interrupt number */
-	.mdio_idx	= -1,		/* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-static struct ocp_func_emac_data ibmnp405h_emac3_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx	= 0,		/* ZMII device index */
-	.zmii_mux	= 3,		/* ZMII input of this EMAC */
-	.mal_idx	= 0,		/* MAL device index */
-	.mal_rx_chan	= 3,		/* MAL rx channel number */
-	.mal_tx_chan	= 6,		/* MAL tx channel number */
-	.wol_irq	= 41,		/* WOL interrupt number */
-	.mdio_idx	= -1,		/* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ibmnp405h_mal0_def = {
-	.num_tx_chans	= 8,		/* Number of TX channels */
-	.num_rx_chans	= 4,		/* Number of RX channels */
-	.txeob_irq	= 17,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 18,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 46,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 47,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 45,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ibmnp405h_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_OPB,
-	  .index	= 0,
-	  .paddr	= 0xEF600000,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= UART0_IO_BASE,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= UART1_IO_BASE,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .paddr	= 0xEF600500,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibmnp405h_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .paddr	= 0xEF600700,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ibmnp405h_mal0_def,
-	  .show		= &ocp_show_mal_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= EMAC0_BASE,
-	  .irq		= 37,
-	  .pm		= IBM_CPM_EMAC0,
-	  .additions	= &ibmnp405h_emac0_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 1,
-	  .paddr	= 0xEF600900,
-	  .irq		= 38,
-	  .pm		= IBM_CPM_EMAC1,
-	  .additions	= &ibmnp405h_emac1_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 2,
-	  .paddr	= 0xEF600a00,
-	  .irq		= 39,
-	  .pm		= IBM_CPM_EMAC2,
-	  .additions	= &ibmnp405h_emac2_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 3,
-	  .paddr	= 0xEF600b00,
-	  .irq		= 40,
-	  .pm		= IBM_CPM_EMAC3,
-	  .additions	= &ibmnp405h_emac3_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_ZMII,
-	  .paddr	= 0xEF600C10,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
diff --git a/arch/ppc/platforms/4xx/ibmnp405h.h b/arch/ppc/platforms/4xx/ibmnp405h.h
deleted file mode 100644
index 08a6a779190..00000000000
--- a/arch/ppc/platforms/4xx/ibmnp405h.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBMNP405H_H__
-#define __ASM_IBMNP405H_H__
-
-
-/* ibm405.h at bottom of this file */
-
-#define PPC405_PCI_CONFIG_ADDR	0xeec00000
-#define PPC405_PCI_CONFIG_DATA	0xeec00004
-#define PPC405_PCI_PHY_MEM_BASE	0x80000000	/* hose_a->pci_mem_offset */
-						/* setbat */
-#define PPC405_PCI_MEM_BASE	PPC405_PCI_PHY_MEM_BASE	/* setbat */
-#define PPC405_PCI_PHY_IO_BASE	0xe8000000	/* setbat */
-#define PPC405_PCI_IO_BASE	PPC405_PCI_PHY_IO_BASE	/* setbat */
-
-#define PPC405_PCI_LOWER_MEM	0x00000000	/* hose_a->mem_space.start */
-#define PPC405_PCI_UPPER_MEM	0xBfffffff	/* hose_a->mem_space.end */
-#define PPC405_PCI_LOWER_IO	0x00000000	/* hose_a->io_space.start */
-#define PPC405_PCI_UPPER_IO	0x0000ffff	/* hose_a->io_space.end */
-
-#define PPC405_ISA_IO_BASE	PPC405_PCI_IO_BASE
-
-#define PPC4xx_PCI_IO_ADDR	((uint)PPC405_PCI_PHY_IO_BASE)
-#define PPC4xx_PCI_IO_SIZE	((uint)64*1024)
-#define PPC4xx_PCI_CFG_ADDR	((uint)PPC405_PCI_CONFIG_ADDR)
-#define PPC4xx_PCI_CFG_SIZE	((uint)4*1024)
-#define PPC4xx_PCI_LCFG_ADDR	((uint)0xef400000)
-#define PPC4xx_PCI_LCFG_SIZE	((uint)4*1024)
-#define PPC4xx_ONB_IO_ADDR	((uint)0xef600000)
-#define PPC4xx_ONB_IO_SIZE	((uint)4*1024)
-
-/* serial port defines */
-#define RS_TABLE_SIZE	4
-
-#define UART0_INT	0
-#define UART1_INT	1
-#define PCIL0_BASE	0xEF400000
-#define UART0_IO_BASE	0xEF600300
-#define UART1_IO_BASE	0xEF600400
-#define OPB0_BASE	0xEF600600
-#define EMAC0_BASE	0xEF600800
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
-
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base:(u8 *) UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
-#define SERIAL_PORT_DFNS        \
-        STD_UART_OP(0)          \
-        STD_UART_OP(1)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
-#define SERIAL_PORT_DFNS        \
-        STD_UART_OP(1)          \
-        STD_UART_OP(0)
-#endif
-
-/* DCR defines */
-/* ------------------------------------------------------------------------- */
-
-#define DCRN_CHCR_BASE	0x0F1
-#define DCRN_CHPSR_BASE	0x0B4
-#define DCRN_CPMSR_BASE	0x0BA
-#define DCRN_CPMFR_BASE	0x0B9
-#define DCRN_CPMER_BASE	0x0B8
-
-/* CPM Clocking & Power Management defines */
-#define IBM_CPM_PCI		0x40000000	/* PCI */
-#define IBM_CPM_EMAC2	0x20000000	/* EMAC 2 MII */
-#define IBM_CPM_EMAC3	0x04000000	/* EMAC 3 MII */
-#define IBM_CPM_EMAC0	0x00800000	/* EMAC 0 MII */
-#define IBM_CPM_EMAC1	0x00100000	/* EMAC 1 MII */
-#define IBM_CPM_EMMII	0	/* Shift value for MII */
-#define IBM_CPM_EMRX	1	/* Shift value for recv */
-#define IBM_CPM_EMTX	2	/* Shift value for MAC */
-#define IBM_CPM_UIC1	0x00020000	/* Universal Interrupt Controller */
-#define IBM_CPM_UIC0	0x00010000	/* Universal Interrupt Controller */
-#define IBM_CPM_CPU	0x00008000	/* processor core */
-#define IBM_CPM_EBC	0x00004000	/* ROM/SRAM peripheral controller */
-#define IBM_CPM_SDRAM0	0x00002000	/* SDRAM memory controller */
-#define IBM_CPM_GPIO0	0x00001000	/* General Purpose IO (??) */
-#define IBM_CPM_HDLC	0x00000800	/* HDCL */
-#define IBM_CPM_TMRCLK	0x00000400	/* CPU timers */
-#define IBM_CPM_PLB	0x00000100	/* PLB bus arbiter */
-#define IBM_CPM_OPB	0x00000080	/* PLB to OPB bridge */
-#define IBM_CPM_DMA	0x00000040	/* DMA controller */
-#define IBM_CPM_IIC0	0x00000010	/* IIC interface */
-#define IBM_CPM_UART0	0x00000002	/* serial port 0 */
-#define IBM_CPM_UART1	0x00000001	/* serial port 1 */
-/* this is the default setting for devices put to sleep when booting */
-
-#define DFLT_IBM4xx_PM	~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU 	\
-			| IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB 	\
-			| IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA	\
-			| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2	\
-			| IBM_CPM_EMAC3 | IBM_CPM_PCI)
-
-#define DCRN_DMA0_BASE	0x100
-#define DCRN_DMA1_BASE	0x108
-#define DCRN_DMA2_BASE	0x110
-#define DCRN_DMA3_BASE	0x118
-#define DCRNCAP_DMA_SG	1	/* have DMA scatter/gather capability */
-#define DCRN_DMASR_BASE	0x120
-#define DCRN_EBC_BASE	0x012
-#define DCRN_DCP0_BASE	0x014
-#define DCRN_MAL_BASE	0x180
-#define DCRN_OCM0_BASE	0x018
-#define DCRN_PLB0_BASE	0x084
-#define DCRN_PLLMR_BASE	0x0B0
-#define DCRN_POB0_BASE	0x0A0
-#define DCRN_SDRAM0_BASE 0x010
-#define DCRN_UIC0_BASE	0x0C0
-#define DCRN_UIC1_BASE	0x0D0
-#define DCRN_CPC0_EPRCSR 0x0F3
-
-#define UIC0_UIC1NC	0x00000002
-
-#define CHR1_CETE	0x00000004	/* CPU external timer enable */
-#define UIC0	DCRN_UIC0_BASE
-#define UIC1	DCRN_UIC1_BASE
-
-#undef NR_UICS
-#define NR_UICS	2
-
-/* EMAC DCRN's FIXME: armin */
-#define DCRN_MALRXCTP2R(base)	((base) + 0x42)	/* Channel Rx 2 Channel Table Pointer */
-#define DCRN_MALRXCTP3R(base)	((base) + 0x43)	/* Channel Rx 3 Channel Table Pointer */
-#define DCRN_MALTXCTP4R(base)	((base) + 0x24)	/* Channel Tx 4 Channel Table Pointer */
-#define DCRN_MALTXCTP5R(base)	((base) + 0x25)	/* Channel Tx 5 Channel Table Pointer */
-#define DCRN_MALTXCTP6R(base)	((base) + 0x26)	/* Channel Tx 6 Channel Table Pointer */
-#define DCRN_MALTXCTP7R(base)	((base) + 0x27)	/* Channel Tx 7 Channel Table Pointer */
-#define DCRN_MALRCBS2(base)	((base) + 0x62)	/* Channel Rx 2 Channel Buffer Size */
-#define DCRN_MALRCBS3(base)	((base) + 0x63)	/* Channel Rx 3 Channel Buffer Size */
-
-#include <asm/ibm405.h>
-
-#endif				/* __ASM_IBMNP405H_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstb4.c b/arch/ppc/platforms/4xx/ibmstb4.c
deleted file mode 100644
index 799a2eccccc..00000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-#include <platforms/4xx/ibmstb4.h>
-
-static struct ocp_func_iic_data ibmstb4_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ibmstb4_iic1_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] __initdata = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= UART0_IO_BASE,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= UART1_IO_BASE,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 2,
-	  .paddr	= UART2_IO_BASE,
-	  .irq		= UART2_INT,
-	  .pm		= IBM_CPM_UART2,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .paddr	= IIC0_BASE,
-	  .irq		= IIC0_IRQ,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibmstb4_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .paddr	= IIC1_BASE,
-	  .irq		= IIC1_IRQ,
-	  .pm		= IBM_CPM_IIC1,
-	  .additions	= &ibmstb4_iic1_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .paddr	= GPIO0_BASE,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IDE,
-	  .paddr	= IDE0_BASE,
-	  .irq		= IDE0_IRQ,
-	  .pm		= OCP_CPM_NA,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID,
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity 	= 0x7fffff01,
-	  .triggering	= 0x00000000,
-	  .ext_irq_mask	= 0x0000007e,	/* IRQ0 - IRQ5 */
-	}
-};
-
-static struct resource ohci_usb_resources[] = {
-	[0] = {
-		.start	= USB0_BASE,
-		.end	= USB0_BASE + USB0_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= USB0_IRQ,
-		.end	= USB0_IRQ,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static u64 dma_mask = 0xffffffffULL;
-
-static struct platform_device ohci_usb_device = {
-	.name		= "ppc-soc-ohci",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(ohci_usb_resources),
-	.resource	= ohci_usb_resources,
-	.dev		= {
-		.dma_mask = &dma_mask,
-		.coherent_dma_mask = 0xffffffffULL,
-	}
-};
-
-static struct platform_device *ibmstb4_devs[] __initdata = {
-	&ohci_usb_device,
-};
-
-static int __init
-ibmstb4_platform_add_devices(void)
-{
-	return platform_add_devices(ibmstb4_devs, ARRAY_SIZE(ibmstb4_devs));
-}
-arch_initcall(ibmstb4_platform_add_devices);
diff --git a/arch/ppc/platforms/4xx/ibmstb4.h b/arch/ppc/platforms/4xx/ibmstb4.h
deleted file mode 100644
index 31a08abaa4a..00000000000
--- a/arch/ppc/platforms/4xx/ibmstb4.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBMSTB4_H__
-#define __ASM_IBMSTB4_H__
-
-
-/* serial port defines */
-#define STB04xxx_IO_BASE	((uint)0xe0000000)
-#define PPC4xx_PCI_IO_ADDR	STB04xxx_IO_BASE
-#define PPC4xx_ONB_IO_PADDR	STB04xxx_IO_BASE
-#define PPC4xx_ONB_IO_VADDR	((uint)0xe0000000)
-#define PPC4xx_ONB_IO_SIZE	((uint)14*64*1024)
-
-/*
- * map STB04xxx internal i/o address (0x400x00xx) to an address
- * which is below the 2GB limit...
- *
- * 4000 000x	uart1		-> 0xe000 000x
- * 4001 00xx	ppu
- * 4002 00xx	smart card
- * 4003 000x	iic
- * 4004 000x	uart0
- * 4005 0xxx	timer
- * 4006 00xx	gpio
- * 4007 00xx	smart card
- * 400b 000x	iic
- * 400c 000x	scp
- * 400d 000x	modem
- * 400e 000x	uart2
-*/
-#define STB04xxx_MAP_IO_ADDR(a)	(((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000))
-
-#define RS_TABLE_SIZE		3
-#define UART0_INT		20
-
-#ifdef __BOOTER__
-#define UART0_IO_BASE		0x40040000
-#else
-#define UART0_IO_BASE		0xe0040000
-#endif
-
-#define UART1_INT		21
-
-#ifdef __BOOTER__
-#define UART1_IO_BASE		0x40000000
-#else
-#define UART1_IO_BASE		0xe0000000
-#endif
-
-#define UART2_INT		31
-#ifdef __BOOTER__
-#define UART2_IO_BASE		0x400e0000
-#else
-#define UART2_IO_BASE		0xe00e0000
-#endif
-
-#define IDE0_BASE	0x400F0000
-#define IDE0_SIZE	0x200
-#define IDE0_IRQ	25
-#define IIC0_BASE	0x40030000
-#define IIC1_BASE	0x400b0000
-#define OPB0_BASE	0x40000000
-#define GPIO0_BASE	0x40060000
-
-#define USB0_BASE	0x40010000
-#define USB0_SIZE	0xA0
-#define USB0_IRQ	18
-
-#define IIC_NUMS 2
-#define UART_NUMS	3
-#define IIC0_IRQ	9
-#define IIC1_IRQ	10
-#define IIC_OWN		0x55
-#define IIC_CLOCK	50
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (u8 *)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)		\
-	STD_UART_OP(2)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(1)		\
-	STD_UART_OP(0)		\
-	STD_UART_OP(2)
-#endif
-
-#if defined(CONFIG_UART0_TTYS2)
-#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(2)		\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-#endif
-
-#define DCRN_BE_BASE		0x090
-#define DCRN_DMA0_BASE		0x0C0
-#define DCRN_DMA1_BASE		0x0C8
-#define DCRN_DMA2_BASE		0x0D0
-#define DCRN_DMA3_BASE		0x0D8
-#define DCRNCAP_DMA_CC		1	/* have DMA chained count capability */
-#define DCRN_DMASR_BASE		0x0E0
-#define DCRN_PLB0_BASE		0x054
-#define DCRN_PLB1_BASE		0x064
-#define DCRN_POB0_BASE		0x0B0
-#define DCRN_SCCR_BASE		0x120
-#define DCRN_UIC0_BASE		0x040
-#define DCRN_BE_BASE		0x090
-#define DCRN_DMA0_BASE		0x0C0
-#define DCRN_DMA1_BASE		0x0C8
-#define DCRN_DMA2_BASE		0x0D0
-#define DCRN_DMA3_BASE		0x0D8
-#define DCRN_CIC_BASE 		0x030
-#define DCRN_DMASR_BASE		0x0E0
-#define DCRN_EBIMC_BASE		0x070
-#define DCRN_DCRX_BASE		0x020
-#define DCRN_CPMFR_BASE		0x102
-#define DCRN_SCCR_BASE		0x120
-#define UIC0 DCRN_UIC0_BASE
-
-#define IBM_CPM_IIC0	0x80000000	/* IIC 0 interface */
-#define IBM_CPM_USB0	0x40000000	/* IEEE-1284 */
-#define IBM_CPM_IIC1	0x20000000	/* IIC 1 interface */
-#define IBM_CPM_CPU	0x10000000	/* PPC405B3 clock control */
-#define IBM_CPM_AUD	0x08000000	/* Audio Decoder */
-#define IBM_CPM_EBIU	0x04000000	/* External Bus Interface Unit */
-#define IBM_CPM_SDRAM1	0x02000000	/* SDRAM 1 memory controller */
-#define IBM_CPM_DMA	0x01000000	/* DMA controller */
-#define IBM_CPM_DMA1	0x00800000	/* reserved */
-#define IBM_CPM_XPT1	0x00400000	/* reserved */
-#define IBM_CPM_XPT2	0x00200000	/* reserved */
-#define IBM_CPM_UART1	0x00100000	/* Serial 1 / Infrared */
-#define IBM_CPM_UART0	0x00080000	/* Serial 0 / 16550 */
-#define IBM_CPM_EPI	0x00040000	/* DCR Extension */
-#define IBM_CPM_SC0	0x00020000	/* Smart Card 0 */
-#define IBM_CPM_VID	0x00010000	/* reserved */
-#define IBM_CPM_SC1	0x00008000	/* Smart Card 1 */
-#define IBM_CPM_USBSDRA	0x00004000	/* SDRAM 0 memory controller */
-#define IBM_CPM_XPT0	0x00002000	/* Transport - 54 Mhz */
-#define IBM_CPM_CBS	0x00001000	/* Cross Bar Switch */
-#define IBM_CPM_GPT	0x00000800	/* GPTPWM */
-#define IBM_CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
-#define IBM_CPM_DENC	0x00000200	/* Digital video Encoder */
-#define IBM_CPM_TMRCLK	0x00000100	/* CPU timers */
-#define IBM_CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
-#define IBM_CPM_UIC	0x00000040	/* Universal Interrupt Controller */
-#define IBM_CPM_SSP	0x00000010	/* Modem Serial Interface (SSP) */
-#define IBM_CPM_UART2	0x00000008	/* Serial Control Port */
-#define IBM_CPM_DDIO	0x00000004	/* Descrambler */
-#define IBM_CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
-
-#define DFLT_IBM4xx_PM	~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
-			| IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
-			| IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
-			| IBM_CPM_XPT27 | IBM_CPM_UIC )
-
-#define DCRN_BEAR	(DCRN_BE_BASE + 0x0)	/* Bus Error Address Register */
-#define DCRN_BESR	(DCRN_BE_BASE + 0x1)	/* Bus Error Syndrome Register */
-/* DCRN_BESR */
-#define BESR_DSES	0x80000000	/* Data-Side Error Status */
-#define BESR_DMES	0x40000000	/* DMA Error Status */
-#define BESR_RWS	0x20000000	/* Read/Write Status */
-#define BESR_ETMASK	0x1C000000	/* Error Type */
-#define ET_PROT		0
-#define ET_PARITY	1
-#define ET_NCFG		2
-#define ET_BUSERR	4
-#define ET_BUSTO	6
-
-#define CHR1_CETE	0x00800000	/* CPU external timer enable */
-#define CHR1_PCIPW	0x00008000	/* PCI Int enable/Peripheral Write enable */
-
-#define DCRN_CICCR	(DCRN_CIC_BASE + 0x0)	/* CIC Control Register */
-#define DCRN_DMAS1	(DCRN_CIC_BASE + 0x1)	/* DMA Select1 Register */
-#define DCRN_DMAS2	(DCRN_CIC_BASE + 0x2)	/* DMA Select2 Register */
-#define DCRN_CICVCR	(DCRN_CIC_BASE + 0x3)	/* CIC Video COntro Register */
-#define DCRN_CICSEL3	(DCRN_CIC_BASE + 0x5)	/* CIC Select 3 Register */
-#define DCRN_SGPO	(DCRN_CIC_BASE + 0x6)	/* CIC GPIO Output Register */
-#define DCRN_SGPOD	(DCRN_CIC_BASE + 0x7)	/* CIC GPIO OD Register */
-#define DCRN_SGPTC	(DCRN_CIC_BASE + 0x8)	/* CIC GPIO Tristate Ctrl Reg */
-#define DCRN_SGPI	(DCRN_CIC_BASE + 0x9)	/* CIC GPIO Input Reg */
-
-#define DCRN_DCRXICR	(DCRN_DCRX_BASE + 0x0)	/* Internal Control Register */
-#define DCRN_DCRXISR	(DCRN_DCRX_BASE + 0x1)	/* Internal Status Register */
-#define DCRN_DCRXECR	(DCRN_DCRX_BASE + 0x2)	/* External Control Register */
-#define DCRN_DCRXESR	(DCRN_DCRX_BASE + 0x3)	/* External Status Register */
-#define DCRN_DCRXTAR	(DCRN_DCRX_BASE + 0x4)	/* Target Address Register */
-#define DCRN_DCRXTDR	(DCRN_DCRX_BASE + 0x5)	/* Target Data Register */
-#define DCRN_DCRXIGR	(DCRN_DCRX_BASE + 0x6)	/* Interrupt Generation Register */
-#define DCRN_DCRXBCR	(DCRN_DCRX_BASE + 0x7)	/* Line Buffer Control Register */
-
-#define DCRN_BRCRH0	(DCRN_EBIMC_BASE + 0x0)	/* Bus Region Config High 0 */
-#define DCRN_BRCRH1	(DCRN_EBIMC_BASE + 0x1)	/* Bus Region Config High 1 */
-#define DCRN_BRCRH2	(DCRN_EBIMC_BASE + 0x2)	/* Bus Region Config High 2 */
-#define DCRN_BRCRH3	(DCRN_EBIMC_BASE + 0x3)	/* Bus Region Config High 3 */
-#define DCRN_BRCRH4	(DCRN_EBIMC_BASE + 0x4)	/* Bus Region Config High 4 */
-#define DCRN_BRCRH5	(DCRN_EBIMC_BASE + 0x5)	/* Bus Region Config High 5 */
-#define DCRN_BRCRH6	(DCRN_EBIMC_BASE + 0x6)	/* Bus Region Config High 6 */
-#define DCRN_BRCRH7	(DCRN_EBIMC_BASE + 0x7)	/* Bus Region Config High 7 */
-#define DCRN_BRCR0	(DCRN_EBIMC_BASE + 0x10)	/* BRC 0 */
-#define DCRN_BRCR1	(DCRN_EBIMC_BASE + 0x11)	/* BRC 1 */
-#define DCRN_BRCR2	(DCRN_EBIMC_BASE + 0x12)	/* BRC 2 */
-#define DCRN_BRCR3	(DCRN_EBIMC_BASE + 0x13)	/* BRC 3 */
-#define DCRN_BRCR4	(DCRN_EBIMC_BASE + 0x14)	/* BRC 4 */
-#define DCRN_BRCR5	(DCRN_EBIMC_BASE + 0x15)	/* BRC 5 */
-#define DCRN_BRCR6	(DCRN_EBIMC_BASE + 0x16)	/* BRC 6 */
-#define DCRN_BRCR7	(DCRN_EBIMC_BASE + 0x17)	/* BRC 7 */
-#define DCRN_BEAR0	(DCRN_EBIMC_BASE + 0x20)	/* Bus Error Address Register */
-#define DCRN_BESR0	(DCRN_EBIMC_BASE + 0x21)	/* Bus Error Status Register */
-#define DCRN_BIUCR	(DCRN_EBIMC_BASE + 0x2A)	/* Bus Interfac Unit Ctrl Reg */
-
-#include <asm/ibm405.h>
-
-#endif				/* __ASM_IBMSTB4_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.c b/arch/ppc/platforms/4xx/ibmstbx25.c
deleted file mode 100644
index 090ddcbecc5..00000000000
--- a/arch/ppc/platforms/4xx/ibmstbx25.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <asm/ocp.h>
-#include <platforms/4xx/ibmstbx25.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_iic_data ibmstbx25_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] __initdata = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index        = 0,
-	  .paddr	= UART0_IO_BASE,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= UART1_IO_BASE,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 2,
-	  .paddr	= UART2_IO_BASE,
-	  .irq		= UART2_INT,
-	  .pm		= IBM_CPM_UART2,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .paddr	= IIC0_BASE,
-	  .irq		= IIC0_IRQ,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ibmstbx25_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .paddr	= GPIO0_BASE,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity 	= 0xffff8f80,
-	  .triggering	= 0x00000000,
-	  .ext_irq_mask	= 0x0000707f,	/* IRQ7 - IRQ9, IRQ0 - IRQ6 */
-	}
-};
diff --git a/arch/ppc/platforms/4xx/ibmstbx25.h b/arch/ppc/platforms/4xx/ibmstbx25.h
deleted file mode 100644
index 31b63343e64..00000000000
--- a/arch/ppc/platforms/4xx/ibmstbx25.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IBMSTBX25_H__
-#define __ASM_IBMSTBX25_H__
-
-
-/* serial port defines */
-#define STBx25xx_IO_BASE	((uint)0xe0000000)
-#define PPC4xx_ONB_IO_PADDR	STBx25xx_IO_BASE
-#define PPC4xx_ONB_IO_VADDR	((uint)0xe0000000)
-#define PPC4xx_ONB_IO_SIZE	((uint)14*64*1024)
-
-/*
- * map STBxxxx internal i/o address (0x400x00xx) to an address
- * which is below the 2GB limit...
- *
- * 4000 000x	uart1		-> 0xe000 000x
- * 4001 00xx	uart2
- * 4002 00xx	smart card
- * 4003 000x	iic
- * 4004 000x	uart0
- * 4005 0xxx	timer
- * 4006 00xx	gpio
- * 4007 00xx	smart card
- * 400b 000x	iic
- * 400c 000x	scp
- * 400d 000x	modem
- * 400e 000x	uart2
-*/
-#define STBx25xx_MAP_IO_ADDR(a)	(((uint)(a)) + (STBx25xx_IO_BASE - 0x40000000))
-
-#define RS_TABLE_SIZE	3
-
-#define OPB_BASE_START	0x40000000
-#define EBIU_BASE_START	0xF0100000
-#define DCR_BASE_START  0x0000
-
-#ifdef __BOOTER__
-#define UART1_IO_BASE	0x40000000
-#define UART2_IO_BASE	0x40010000
-#else
-#define UART1_IO_BASE	0xe0000000
-#define UART2_IO_BASE	0xe0010000
-#endif
-#define SC0_BASE	0x40020000	/* smart card #0 */
-#define IIC0_BASE	0x40030000
-#ifdef __BOOTER__
-#define UART0_IO_BASE	0x40040000
-#else
-#define UART0_IO_BASE	0xe0040000
-#endif
-#define SCC0_BASE	0x40040000	/* Serial 0 controller IrdA */
-#define GPT0_BASE	0x40050000	/* General purpose timers */
-#define GPIO0_BASE	0x40060000
-#define SC1_BASE	0x40070000	/* smart card #1 */
-#define SCP0_BASE	0x400C0000	/* Serial Controller Port */
-#define SSP0_BASE	0x400D0000	/* Sync serial port */
-
-#define IDE0_BASE		0xf0100000
-#define REDWOOD_IDE_CTRL	0xf1100000
-
-#define RTCFPC_IRQ	0
-#define XPORT_IRQ	1
-#define AUD_IRQ		2
-#define AID_IRQ		3
-#define DMA0		4
-#define DMA1_IRQ	5
-#define DMA2_IRQ	6
-#define DMA3_IRQ	7
-#define SC0_IRQ		8
-#define IIC0_IRQ	9
-#define IIR0_IRQ	10
-#define GPT0_IRQ	11
-#define GPT1_IRQ	12
-#define SCP0_IRQ	13
-#define SSP0_IRQ	14
-#define GPT2_IRQ	15	/* count down timer */
-#define SC1_IRQ		16
-/* IRQ 17 - 19  external */
-#define UART0_INT	20
-#define UART1_INT	21
-#define UART2_INT	22
-#define XPTDMA_IRQ	23
-#define DCRIDE_IRQ	24
-/* IRQ 25 - 30 external */
-#define IDE0_IRQ	26
-
-#define IIC_NUMS	1
-#define UART_NUMS	3
-#define IIC_OWN		0x55
-#define IIC_CLOCK	50
-
-#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
-
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (u8 *)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)		\
-	STD_UART_OP(2)
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(1)		\
-	STD_UART_OP(0)		\
-	STD_UART_OP(2)
-#endif
-
-#if defined(CONFIG_UART0_TTYS2)
-#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(2)		\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-#endif
-
-#define DCRN_BE_BASE		0x090
-#define DCRN_DMA0_BASE		0x0C0
-#define DCRN_DMA1_BASE		0x0C8
-#define DCRN_DMA2_BASE		0x0D0
-#define DCRN_DMA3_BASE		0x0D8
-#define DCRNCAP_DMA_CC		1	/* have DMA chained count capability */
-#define DCRN_DMASR_BASE		0x0E0
-#define DCRN_PLB0_BASE		0x054
-#define DCRN_PLB1_BASE		0x064
-#define DCRN_POB0_BASE		0x0B0
-#define DCRN_SCCR_BASE		0x120
-#define DCRN_UIC0_BASE		0x040
-#define DCRN_BE_BASE		0x090
-#define DCRN_DMA0_BASE		0x0C0
-#define DCRN_DMA1_BASE		0x0C8
-#define DCRN_DMA2_BASE		0x0D0
-#define DCRN_DMA3_BASE		0x0D8
-#define DCRN_CIC_BASE 		0x030
-#define DCRN_DMASR_BASE		0x0E0
-#define DCRN_EBIMC_BASE		0x070
-#define DCRN_DCRX_BASE		0x020
-#define DCRN_CPMFR_BASE		0x102
-#define DCRN_SCCR_BASE		0x120
-#define DCRN_RTCFP_BASE		0x310
-
-#define UIC0 DCRN_UIC0_BASE
-
-#define IBM_CPM_IIC0	0x80000000	/* IIC 0 interface */
-#define IBM_CPM_CPU	0x10000000	/* PPC405B3 clock control */
-#define IBM_CPM_AUD	0x08000000	/* Audio Decoder */
-#define IBM_CPM_EBIU	0x04000000	/* External Bus Interface Unit */
-#define IBM_CPM_IRR	0x02000000	/* Infrared receiver */
-#define IBM_CPM_DMA	0x01000000	/* DMA controller */
-#define IBM_CPM_UART2	0x00200000	/* Serial Control Port */
-#define IBM_CPM_UART1	0x00100000	/* Serial 1 / Infrared */
-#define IBM_CPM_UART0	0x00080000	/* Serial 0 / 16550 */
-#define IBM_PM_DCRIDE	0x00040000	/* DCR timeout & IDE line Mode clock */
-#define IBM_CPM_SC0	0x00020000	/* Smart Card 0 */
-#define IBM_CPM_VID	0x00010000	/* reserved */
-#define IBM_CPM_SC1	0x00008000	/* Smart Card 0 */
-#define IBM_CPM_XPT0	0x00002000	/* Transport - 54 Mhz */
-#define IBM_CPM_CBS	0x00001000	/* Cross Bar Switch */
-#define IBM_CPM_GPT	0x00000800	/* GPTPWM */
-#define IBM_CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
-#define IBM_CPM_DENC	0x00000200	/* Digital video Encoder */
-#define IBM_CPM_C405T	0x00000100	/* CPU timers */
-#define IBM_CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
-#define IBM_CPM_UIC	0x00000040	/* Universal Interrupt Controller */
-#define IBM_CPM_RTCFPC	0x00000020	/* Realtime clock and front panel */
-#define IBM_CPM_SSP	0x00000010	/* Modem Serial Interface (SSP) */
-#define IBM_CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
-#define DFLT_IBM4xx_PM	~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_DMA	\
-			| IBM_CPM_CBS | IBM_CPM_XPT0 | IBM_CPM_C405T 	\
-			| IBM_CPM_XPT27 | IBM_CPM_UIC)
-
-#define DCRN_BEAR	(DCRN_BE_BASE + 0x0)	/* Bus Error Address Register */
-#define DCRN_BESR	(DCRN_BE_BASE + 0x1)	/* Bus Error Syndrome Register */
-/* DCRN_BESR */
-#define BESR_DSES	0x80000000	/* Data-Side Error Status */
-#define BESR_DMES	0x40000000	/* DMA Error Status */
-#define BESR_RWS	0x20000000	/* Read/Write Status */
-#define BESR_ETMASK	0x1C000000	/* Error Type */
-#define ET_PROT		0
-#define ET_PARITY	1
-#define ET_NCFG		2
-#define ET_BUSERR	4
-#define ET_BUSTO	6
-
-#define CHR1_CETE	0x00800000	/* CPU external timer enable */
-#define CHR1_PCIPW	0x00008000	/* PCI Int enable/Peripheral Write enable */
-
-#define DCRN_CICCR	(DCRN_CIC_BASE + 0x0)	/* CIC Control Register */
-#define DCRN_DMAS1	(DCRN_CIC_BASE + 0x1)	/* DMA Select1 Register */
-#define DCRN_DMAS2	(DCRN_CIC_BASE + 0x2)	/* DMA Select2 Register */
-#define DCRN_CICVCR	(DCRN_CIC_BASE + 0x3)	/* CIC Video COntro Register */
-#define DCRN_CICSEL3	(DCRN_CIC_BASE + 0x5)	/* CIC Select 3 Register */
-#define DCRN_SGPO	(DCRN_CIC_BASE + 0x6)	/* CIC GPIO Output Register */
-#define DCRN_SGPOD	(DCRN_CIC_BASE + 0x7)	/* CIC GPIO OD Register */
-#define DCRN_SGPTC	(DCRN_CIC_BASE + 0x8)	/* CIC GPIO Tristate Ctrl Reg */
-#define DCRN_SGPI	(DCRN_CIC_BASE + 0x9)	/* CIC GPIO Input Reg */
-
-#define DCRN_DCRXICR	(DCRN_DCRX_BASE + 0x0)	/* Internal Control Register */
-#define DCRN_DCRXISR	(DCRN_DCRX_BASE + 0x1)	/* Internal Status Register */
-#define DCRN_DCRXECR	(DCRN_DCRX_BASE + 0x2)	/* External Control Register */
-#define DCRN_DCRXESR	(DCRN_DCRX_BASE + 0x3)	/* External Status Register */
-#define DCRN_DCRXTAR	(DCRN_DCRX_BASE + 0x4)	/* Target Address Register */
-#define DCRN_DCRXTDR	(DCRN_DCRX_BASE + 0x5)	/* Target Data Register */
-#define DCRN_DCRXIGR	(DCRN_DCRX_BASE + 0x6)	/* Interrupt Generation Register */
-#define DCRN_DCRXBCR	(DCRN_DCRX_BASE + 0x7)	/* Line Buffer Control Register */
-
-#define DCRN_BRCRH0	(DCRN_EBIMC_BASE + 0x0)	/* Bus Region Config High 0 */
-#define DCRN_BRCRH1	(DCRN_EBIMC_BASE + 0x1)	/* Bus Region Config High 1 */
-#define DCRN_BRCRH2	(DCRN_EBIMC_BASE + 0x2)	/* Bus Region Config High 2 */
-#define DCRN_BRCRH3	(DCRN_EBIMC_BASE + 0x3)	/* Bus Region Config High 3 */
-#define DCRN_BRCRH4	(DCRN_EBIMC_BASE + 0x4)	/* Bus Region Config High 4 */
-#define DCRN_BRCRH5	(DCRN_EBIMC_BASE + 0x5)	/* Bus Region Config High 5 */
-#define DCRN_BRCRH6	(DCRN_EBIMC_BASE + 0x6)	/* Bus Region Config High 6 */
-#define DCRN_BRCRH7	(DCRN_EBIMC_BASE + 0x7)	/* Bus Region Config High 7 */
-#define DCRN_BRCR0	(DCRN_EBIMC_BASE + 0x10)	/* BRC 0 */
-#define DCRN_BRCR1	(DCRN_EBIMC_BASE + 0x11)	/* BRC 1 */
-#define DCRN_BRCR2	(DCRN_EBIMC_BASE + 0x12)	/* BRC 2 */
-#define DCRN_BRCR3	(DCRN_EBIMC_BASE + 0x13)	/* BRC 3 */
-#define DCRN_BRCR4	(DCRN_EBIMC_BASE + 0x14)	/* BRC 4 */
-#define DCRN_BRCR5	(DCRN_EBIMC_BASE + 0x15)	/* BRC 5 */
-#define DCRN_BRCR6	(DCRN_EBIMC_BASE + 0x16)	/* BRC 6 */
-#define DCRN_BRCR7	(DCRN_EBIMC_BASE + 0x17)	/* BRC 7 */
-#define DCRN_BEAR0	(DCRN_EBIMC_BASE + 0x20)	/* Bus Error Address Register */
-#define DCRN_BESR0	(DCRN_EBIMC_BASE + 0x21)	/* Bus Error Status Register */
-#define DCRN_BIUCR	(DCRN_EBIMC_BASE + 0x2A)	/* Bus Interfac Unit Ctrl Reg */
-
-#define DCRN_RTC_FPC0_CNTL 	(DCRN_RTCFP_BASE + 0x00)	/* RTC cntl */
-#define DCRN_RTC_FPC0_INT 	(DCRN_RTCFP_BASE + 0x01)	/* RTC Interrupt */
-#define DCRN_RTC_FPC0_TIME 	(DCRN_RTCFP_BASE + 0x02)	/* RTC time reg */
-#define DCRN_RTC_FPC0_ALRM 	(DCRN_RTCFP_BASE + 0x03)	/* RTC Alarm reg */
-#define DCRN_RTC_FPC0_D1 	(DCRN_RTCFP_BASE + 0x04)	/* LED Data 1 */
-#define DCRN_RTC_FPC0_D2 	(DCRN_RTCFP_BASE + 0x05)	/* LED Data 2 */
-#define DCRN_RTC_FPC0_D3 	(DCRN_RTCFP_BASE + 0x06)	/* LED Data 3 */
-#define DCRN_RTC_FPC0_D4 	(DCRN_RTCFP_BASE + 0x07)	/* LED Data 4 */
-#define DCRN_RTC_FPC0_D5 	(DCRN_RTCFP_BASE + 0x08)	/* LED Data 5 */
-#define DCRN_RTC_FPC0_FCNTL 	(DCRN_RTCFP_BASE + 0x09)	/* LED control */
-#define DCRN_RTC_FPC0_BRT 	(DCRN_RTCFP_BASE + 0x0A)	/* Brightness cntl */
-
-#include <asm/ibm405.h>
-
-#endif				/* __ASM_IBMSTBX25_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/luan.c b/arch/ppc/platforms/4xx/luan.c
deleted file mode 100644
index f6d8c2e8b6b..00000000000
--- a/arch/ppc/platforms/4xx/luan.c
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * Luan board specific routines
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2004-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-
-#include <syslib/ibm44x_common.h>
-#include <syslib/ibm440gx_common.h>
-#include <syslib/ibm440sp_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-static void __init
-luan_calibrate_decr(void)
-{
-	unsigned int freq;
-
-	if (mfspr(SPRN_CCR1) & CCR1_TCS)
-		freq = LUAN_TMR_CLK;
-	else
-		freq = clocks.cpu;
-
-	ibm44x_calibrate_decr(freq);
-}
-
-static int
-luan_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: IBM\n");
-	seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
-
-	return 0;
-}
-
-static inline int
-luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
-
-	/* PCIX0 in adapter mode, no host interrupt routing */
-
-	/* PCIX1 */
-	if (hose->index == 0) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 *	  A   B   C   D
-		 */
-		{
-			{ 49, 49, 49, 49 },	/* IDSEL 1 - PCIX1 Slot 0 */
-			{ 49, 49, 49, 49 },	/* IDSEL 2 - PCIX1 Slot 1 */
-			{ 49, 49, 49, 49 },	/* IDSEL 3 - PCIX1 Slot 2 */
-			{ 49, 49, 49, 49 },	/* IDSEL 4 - PCIX1 Slot 3 */
-		};
-		const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	/* PCIX2 */
-	} else if (hose->index == 1) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 *	  A   B   C   D
-		 */
-		{
-			{ 50, 50, 50, 50 },	/* IDSEL 1 - PCIX2 Slot 0 */
-			{ 50, 50, 50, 50 },	/* IDSEL 2 - PCIX2 Slot 1 */
-			{ 50, 50, 50, 50 },	/* IDSEL 3 - PCIX2 Slot 2 */
-			{ 50, 50, 50, 50 },	/* IDSEL 4 - PCIX2 Slot 3 */
-		};
-		const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-	return -1;
-}
-
-static void __init luan_set_emacdata(void)
-{
-	struct ocp_def *def;
-	struct ocp_func_emac_data *emacdata;
-
-	/* Set phy_map, phy_mode, and mac_addr for the EMAC */
-	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
-	emacdata = def->additions;
-	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
-	emacdata->phy_mode = PHY_MODE_GMII;
-	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-}
-
-#define PCIX_READW(offset) \
-	(readw((void *)((u32)pcix_reg_base+offset)))
-
-#define PCIX_WRITEW(value, offset) \
-	(writew(value, (void *)((u32)pcix_reg_base+offset)))
-
-#define PCIX_WRITEL(value, offset) \
-	(writel(value, (void *)((u32)pcix_reg_base+offset)))
-
-static void __init
-luan_setup_pcix(void)
-{
-	int i;
-	void *pcix_reg_base;
-
-	for (i=0;i<3;i++) {
-		pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
-
-		/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
-		PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
-
-		/* Disable all windows */
-		PCIX_WRITEL(0, PCIX0_POM0SA);
-		PCIX_WRITEL(0, PCIX0_POM1SA);
-		PCIX_WRITEL(0, PCIX0_POM2SA);
-		PCIX_WRITEL(0, PCIX0_PIM0SA);
-		PCIX_WRITEL(0, PCIX0_PIM0SAH);
-		PCIX_WRITEL(0, PCIX0_PIM1SA);
-		PCIX_WRITEL(0, PCIX0_PIM2SA);
-		PCIX_WRITEL(0, PCIX0_PIM2SAH);
-
-		/*
-		 * Setup 512MB PLB->PCI outbound mem window
-		 * (a_n000_0000->0_n000_0000)
-		 * */
-		PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
-		PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
-		PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
-		PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
-		PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
-
-		/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
-		PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
-		PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
-		PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
-		PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
-
-		iounmap(pcix_reg_base);
-	}
-
-	eieio();
-}
-
-static void __init
-luan_setup_hose(struct pci_controller *hose,
-		int lower_mem,
-		int upper_mem,
-		int cfga,
-		int cfgd,
-		u64 pcix_io_base)
-{
-	char name[20];
-
-	sprintf(name, "PCIX%d host bridge", hose->index);
-
-	hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
-
-	pci_init_resource(&hose->io_resource,
-			LUAN_PCIX_LOWER_IO,
-			LUAN_PCIX_UPPER_IO,
-			IORESOURCE_IO,
-			name);
-
-	pci_init_resource(&hose->mem_resources[0],
-			lower_mem,
-			upper_mem,
-			IORESOURCE_MEM,
-			name);
-
-	hose->io_space.start = LUAN_PCIX_LOWER_IO;
-	hose->io_space.end = LUAN_PCIX_UPPER_IO;
-	hose->mem_space.start = lower_mem;
-	hose->mem_space.end = upper_mem;
-	hose->io_base_virt = ioremap64(pcix_io_base, PCIX_IO_SIZE);
-	isa_io_base = (unsigned long) hose->io_base_virt;
-
-	setup_indirect_pci(hose, cfga, cfgd);
-	hose->set_cfg_type = 1;
-}
-
-static void __init
-luan_setup_hoses(void)
-{
-	struct pci_controller *hose1, *hose2;
-
-	/* Configure windows on the PCI-X host bridge */
-	luan_setup_pcix();
-
-	/* Allocate hoses for PCIX1 and PCIX2 */
-	hose1 = pcibios_alloc_controller();
-	if (!hose1)
-		return;
-
-	hose2 = pcibios_alloc_controller();
-	if (!hose2) {
-		pcibios_free_controller(hose1);
-		return;
-	}
-
-	/* Setup PCIX1 */
-	hose1->first_busno = 0;
-	hose1->last_busno = 0xff;
-
-	luan_setup_hose(hose1,
-			LUAN_PCIX1_LOWER_MEM,
-			LUAN_PCIX1_UPPER_MEM,
-			PCIX1_CFGA,
-			PCIX1_CFGD,
-			PCIX1_IO_BASE);
-
-	hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
-
-	/* Setup PCIX2 */
-	hose2->first_busno = hose1->last_busno + 1;
-	hose2->last_busno = 0xff;
-
-	luan_setup_hose(hose2,
-			LUAN_PCIX2_LOWER_MEM,
-			LUAN_PCIX2_UPPER_MEM,
-			PCIX2_CFGA,
-			PCIX2_CFGD,
-			PCIX2_IO_BASE);
-
-	hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
-
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = luan_map_irq;
-}
-
-TODC_ALLOC();
-
-static void __init
-luan_early_serial_map(void)
-{
-	struct uart_port port;
-
-	/* Setup ioremapped serial port access */
-	memset(&port, 0, sizeof(port));
-	port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
-	port.irq = UART0_INT;
-	port.uartclk = clocks.uart0;
-	port.regshift = 0;
-	port.iotype = UPIO_MEM;
-	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	port.line = 0;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 0 failed\n");
-	}
-
-	port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
-	port.irq = UART1_INT;
-	port.uartclk = clocks.uart1;
-	port.line = 1;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 1 failed\n");
-	}
-
-	port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
-	port.irq = UART2_INT;
-	port.uartclk = BASE_BAUD;
-	port.line = 2;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 2 failed\n");
-	}
-}
-
-static void __init
-luan_setup_arch(void)
-{
-	luan_set_emacdata();
-
-#if !defined(CONFIG_BDI_SWITCH)
-	/*
-	 * The Abatron BDI JTAG debugger does not tolerate others
-	 * mucking with the debug registers.
-	 */
-        mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
-#endif
-
-	/*
-	 * Determine various clocks.
-	 * To be completely correct we should get SysClk
-	 * from FPGA, because it can be changed by on-board switches
-	 * --ebs
-	 */
-	/* 440GX and 440SP clocking is the same -mdp */
-	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
-	ocp_sys_info.opb_bus_freq = clocks.opb;
-
-	/* init to some ~sane value until calibrate_delay() runs */
-        loops_per_jiffy = 50000000/HZ;
-
-	/* Setup PCIXn host bridges */
-	luan_setup_hoses();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_HDA1;
-#endif
-
-	luan_early_serial_map();
-
-	/* Identify the system */
-	printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
-		unsigned long r5, unsigned long r6, unsigned long r7)
-{
-	ibm44x_platform_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = luan_setup_arch;
-	ppc_md.show_cpuinfo = luan_show_cpuinfo;
-	ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
-	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
-
-	ppc_md.calibrate_decr = luan_calibrate_decr;
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = luan_early_serial_map;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/luan.h b/arch/ppc/platforms/4xx/luan.h
deleted file mode 100644
index 68dd46b0a5c..00000000000
--- a/arch/ppc/platforms/4xx/luan.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Luan board definitions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2004-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_LUAN_H__
-#define __ASM_LUAN_H__
-
-#include <platforms/4xx/ibm440sp.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0	0xa0000800
-
-/* Location of MAC addresses in PIBS image */
-#define PIBS_FLASH_BASE		0xffe00000
-#define PIBS_MAC_BASE		(PIBS_FLASH_BASE+0x1b0400)
-
-/* External timer clock frequency */
-#define LUAN_TMR_CLK		25000000
-
-/* Flash */
-#define LUAN_FPGA_REG_0			0x0000000148300000ULL
-#define LUAN_BOOT_LARGE_FLASH(x)	(x & 0x40)
-#define LUAN_SMALL_FLASH_LOW		0x00000001ff900000ULL
-#define LUAN_SMALL_FLASH_HIGH		0x00000001ffe00000ULL
-#define LUAN_SMALL_FLASH_SIZE		0x100000
-#define LUAN_LARGE_FLASH_LOW		0x00000001ff800000ULL
-#define LUAN_LARGE_FLASH_HIGH		0x00000001ffc00000ULL
-#define LUAN_LARGE_FLASH_SIZE		0x400000
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE	3
-
-/* PIBS defined UART mappings, used before early_serial_setup */
-#define UART0_IO_BASE	0xa0000200
-#define UART1_IO_BASE	0xa0000300
-#define UART2_IO_BASE	0xa0000600
-
-#define BASE_BAUD	11059200
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (void*)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)		\
-	STD_UART_OP(2)
-
-/* PCI support */
-#define LUAN_PCIX_LOWER_IO	0x00000000
-#define LUAN_PCIX_UPPER_IO	0x0000ffff
-#define LUAN_PCIX0_LOWER_MEM	0x80000000
-#define LUAN_PCIX0_UPPER_MEM	0x9fffffff
-#define LUAN_PCIX1_LOWER_MEM	0xa0000000
-#define LUAN_PCIX1_UPPER_MEM	0xbfffffff
-#define LUAN_PCIX2_LOWER_MEM	0xc0000000
-#define LUAN_PCIX2_UPPER_MEM	0xdfffffff
-
-#define LUAN_PCIX_MEM_SIZE	0x20000000
-#define LUAN_PCIX_MEM_OFFSET	0x00000000
-
-#endif				/* __ASM_LUAN_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ocotea.c b/arch/ppc/platforms/4xx/ocotea.c
deleted file mode 100644
index 308386ef6f7..00000000000
--- a/arch/ppc/platforms/4xx/ocotea.c
+++ /dev/null
@@ -1,350 +0,0 @@
-/*
- * Ocotea board specific routines
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2003-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-#include <asm/tlbflush.h>
-
-#include <syslib/gen550.h>
-#include <syslib/ibm440gx_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-static void __init
-ocotea_calibrate_decr(void)
-{
-	unsigned int freq;
-
-	if (mfspr(SPRN_CCR1) & CCR1_TCS)
-		freq = OCOTEA_TMR_CLK;
-	else
-		freq = clocks.cpu;
-
-	ibm44x_calibrate_decr(freq);
-}
-
-static int
-ocotea_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: IBM\n");
-	seq_printf(m, "machine\t\t: PPC440GX EVB (Ocotea)\n");
-	ibm440gx_show_cpuinfo(m);
-	return 0;
-}
-
-static inline int
-ocotea_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *	PCI IDSEL/INTPIN->INTLINE
-	 * 	   A   B   C   D
-	 */
-	{
-		{ 23, 23, 23, 23 },	/* IDSEL 1 - PCI Slot 0 */
-		{ 24, 24, 24, 24 },	/* IDSEL 2 - PCI Slot 1 */
-		{ 25, 25, 25, 25 },	/* IDSEL 3 - PCI Slot 2 */
-		{ 26, 26, 26, 26 },	/* IDSEL 4 - PCI Slot 3 */
-	};
-
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __init ocotea_set_emacdata(void)
-{
-	struct ocp_def *def;
-	struct ocp_func_emac_data *emacdata;
-	int i;
-
-	/*
-	 * Note: Current rev. board only operates in Group 4a
-	 * mode, so we always set EMAC0-1 for SMII and EMAC2-3
-	 * for RGMII (though these could run in RTBI just the same).
-	 *
-	 * The FPGA reg 3 information isn't even suitable for
-	 * determining the phy_mode, so if the board becomes
-	 * usable in !4a, it will be necessary to parse an environment
-	 * variable from the firmware or similar to properly configure
-	 * the phy_map/phy_mode.
-	 */
-	/* Set phy_map, phy_mode, and mac_addr for each EMAC */
-	for (i=0; i<4; i++) {
-		def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
-		emacdata = def->additions;
-		if (i < 2) {
-			emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
-			emacdata->phy_mode = PHY_MODE_SMII;
-		}
-		else {
-			emacdata->phy_map = 0x0000ffff; /* Skip 0x00-0x0f */
-			emacdata->phy_mode = PHY_MODE_RGMII;
-		}
-		if (i == 0)
-			memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-		else if (i == 1)
-			memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
-		else if (i == 2)
-			memcpy(emacdata->mac_addr, __res.bi_enet2addr, 6);
-		else if (i == 3)
-			memcpy(emacdata->mac_addr, __res.bi_enet3addr, 6);
-	}
-}
-
-#define PCIX_READW(offset) \
-	(readw(pcix_reg_base+offset))
-
-#define PCIX_WRITEW(value, offset) \
-	(writew(value, pcix_reg_base+offset))
-
-#define PCIX_WRITEL(value, offset) \
-	(writel(value, pcix_reg_base+offset))
-
-/*
- * FIXME: This is only here to "make it work".  This will move
- * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
- * configuration library. -Matt
- */
-static void __init
-ocotea_setup_pcix(void)
-{
-	void *pcix_reg_base;
-
-	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
-
-	/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
-	PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
-
-	/* Disable all windows */
-	PCIX_WRITEL(0, PCIX0_POM0SA);
-	PCIX_WRITEL(0, PCIX0_POM1SA);
-	PCIX_WRITEL(0, PCIX0_POM2SA);
-	PCIX_WRITEL(0, PCIX0_PIM0SA);
-	PCIX_WRITEL(0, PCIX0_PIM0SAH);
-	PCIX_WRITEL(0, PCIX0_PIM1SA);
-	PCIX_WRITEL(0, PCIX0_PIM2SA);
-	PCIX_WRITEL(0, PCIX0_PIM2SAH);
-
-	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
-	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
-	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
-	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
-	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
-	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
-
-	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
-	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
-	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
-	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
-
-	eieio();
-}
-
-static void __init
-ocotea_setup_hose(void)
-{
-	struct pci_controller *hose;
-
-	/* Configure windows on the PCI-X host bridge */
-	ocotea_setup_pcix();
-
-	hose = pcibios_alloc_controller();
-
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	hose->pci_mem_offset = OCOTEA_PCI_MEM_OFFSET;
-
-	pci_init_resource(&hose->io_resource,
-			OCOTEA_PCI_LOWER_IO,
-			OCOTEA_PCI_UPPER_IO,
-			IORESOURCE_IO,
-			"PCI host bridge");
-
-	pci_init_resource(&hose->mem_resources[0],
-			OCOTEA_PCI_LOWER_MEM,
-			OCOTEA_PCI_UPPER_MEM,
-			IORESOURCE_MEM,
-			"PCI host bridge");
-
-	hose->io_space.start = OCOTEA_PCI_LOWER_IO;
-	hose->io_space.end = OCOTEA_PCI_UPPER_IO;
-	hose->mem_space.start = OCOTEA_PCI_LOWER_MEM;
-	hose->mem_space.end = OCOTEA_PCI_UPPER_MEM;
-	hose->io_base_virt = ioremap64(OCOTEA_PCI_IO_BASE, OCOTEA_PCI_IO_SIZE);
-	isa_io_base = (unsigned long) hose->io_base_virt;
-
-	setup_indirect_pci(hose,
-			OCOTEA_PCI_CFGA_PLB32,
-			OCOTEA_PCI_CFGD_PLB32);
-	hose->set_cfg_type = 1;
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = ocotea_map_irq;
-}
-
-
-TODC_ALLOC();
-
-static void __init
-ocotea_early_serial_map(void)
-{
-	struct uart_port port;
-
-	/* Setup ioremapped serial port access */
-	memset(&port, 0, sizeof(port));
-	port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
-	port.irq = UART0_INT;
-	port.uartclk = clocks.uart0;
-	port.regshift = 0;
-	port.iotype = UPIO_MEM;
-	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	port.line = 0;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 0 failed\n");
-	}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(0, &port);
-
-	/* Purge TLB entry added in head_44x.S for early serial access */
-	_tlbie(UART0_IO_BASE, 0);
-#endif
-
-	port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
-	port.irq = UART1_INT;
-	port.uartclk = clocks.uart1;
-	port.line = 1;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 1 failed\n");
-	}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(1, &port);
-#endif
-}
-
-static void __init
-ocotea_setup_arch(void)
-{
-	ocotea_set_emacdata();
-
-	ibm440gx_tah_enable();
-
-	/*
-	 * Determine various clocks.
-	 * To be completely correct we should get SysClk
-	 * from FPGA, because it can be changed by on-board switches
-	 * --ebs
-	 */
-	ibm440gx_get_clocks(&clocks, 33300000, 6 * 1843200);
-	ocp_sys_info.opb_bus_freq = clocks.opb;
-
-	/* Setup TODC access */
-	TODC_INIT(TODC_TYPE_DS1743,
-			0,
-			0,
-			ioremap64(OCOTEA_RTC_ADDR, OCOTEA_RTC_SIZE),
-			8);
-
-	/* init to some ~sane value until calibrate_delay() runs */
-        loops_per_jiffy = 50000000/HZ;
-
-	/* Setup PCI host bridge */
-	ocotea_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_HDA1;
-#endif
-
-	ocotea_early_serial_map();
-
-	/* Identify the system */
-	printk("IBM Ocotea port (MontaVista Software, Inc. <source@mvista.com>)\n");
-}
-
-static void __init ocotea_init(void)
-{
-	ibm440gx_l2c_setup(&clocks);
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
-		unsigned long r5, unsigned long r6, unsigned long r7)
-{
-	ibm440gx_platform_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = ocotea_setup_arch;
-	ppc_md.show_cpuinfo = ocotea_show_cpuinfo;
-	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
-
-	ppc_md.calibrate_decr = ocotea_calibrate_decr;
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = ocotea_early_serial_map;
-#endif
-	ppc_md.init = ocotea_init;
-}
diff --git a/arch/ppc/platforms/4xx/ocotea.h b/arch/ppc/platforms/4xx/ocotea.h
deleted file mode 100644
index 89730ce2322..00000000000
--- a/arch/ppc/platforms/4xx/ocotea.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Ocotea board definitions
- *
- * Matt Porter <mporter@kernel.crashing.org>
- *
- * Copyright 2003-2005 MontaVista Software Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_OCOTEA_H__
-#define __ASM_OCOTEA_H__
-
-#include <platforms/4xx/ibm440gx.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0	0xe0000800
-
-/* Location of MAC addresses in PIBS image */
-#define PIBS_FLASH_BASE		0xfff00000
-#define PIBS_MAC_BASE		(PIBS_FLASH_BASE+0xb0500)
-#define PIBS_MAC_SIZE		0x200
-#define PIBS_MAC_OFFSET		0x100
-
-/* External timer clock frequency */
-#define OCOTEA_TMR_CLK	25000000
-
-/* RTC/NVRAM location */
-#define OCOTEA_RTC_ADDR		0x0000000148000000ULL
-#define OCOTEA_RTC_SIZE		0x2000
-
-/* Flash */
-#define OCOTEA_FPGA_REG_0		0x0000000148300000ULL
-#define OCOTEA_BOOT_LARGE_FLASH(x)	(x & 0x40)
-#define OCOTEA_SMALL_FLASH_LOW		0x00000001ff900000ULL
-#define OCOTEA_SMALL_FLASH_HIGH		0x00000001fff00000ULL
-#define OCOTEA_SMALL_FLASH_SIZE		0x100000
-#define OCOTEA_LARGE_FLASH_LOW		0x00000001ff800000ULL
-#define OCOTEA_LARGE_FLASH_HIGH		0x00000001ffc00000ULL
-#define OCOTEA_LARGE_FLASH_SIZE		0x400000
-
-/* FPGA_REG_3 (Ethernet Groups) */
-#define OCOTEA_FPGA_REG_3		0x0000000148300003ULL
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE	2
-
-#if defined(__BOOTER__)
-/* OpenBIOS defined UART mappings, used by bootloader shim */
-#define UART0_IO_BASE	0xE0000200
-#define UART1_IO_BASE	0xE0000300
-#else
-/* head_44x.S created UART mapping, used before early_serial_setup.
- * We cannot use default OpenBIOS UART mappings because they
- * don't work for configurations with more than 512M RAM.    --ebs
- */
-#define UART0_IO_BASE	0xF0000200
-#define UART1_IO_BASE	0xF0000300
-#endif
-
-#define BASE_BAUD	11059200/16
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (void*)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-
-/* PCI support */
-#define OCOTEA_PCI_LOWER_IO	0x00000000
-#define OCOTEA_PCI_UPPER_IO	0x0000ffff
-#define OCOTEA_PCI_LOWER_MEM	0x80000000
-#define OCOTEA_PCI_UPPER_MEM	0xffffefff
-
-#define OCOTEA_PCI_CFGREGS_BASE	0x000000020ec00000ULL
-#define OCOTEA_PCI_CFGA_PLB32	0x0ec00000
-#define OCOTEA_PCI_CFGD_PLB32	0x0ec00004
-
-#define OCOTEA_PCI_IO_BASE	0x0000000208000000ULL
-#define OCOTEA_PCI_IO_SIZE	0x00010000
-#define OCOTEA_PCI_MEM_OFFSET	0x00000000
-
-#endif				/* __ASM_OCOTEA_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/ppc440spe.c b/arch/ppc/platforms/4xx/ppc440spe.c
deleted file mode 100644
index 1be5d1c8e26..00000000000
--- a/arch/ppc/platforms/4xx/ppc440spe.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * PPC440SPe I/O descriptions
- *
- * Roland Dreier <rolandd@cisco.com>
- * Copyright (c) 2005 Cisco Systems.  All rights reserved.
- *
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2002-2005 MontaVista Software Inc.
- *
- * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
- * Copyright (c) 2003, 2004 Zultys Technologies
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-#include <linux/init.h>
-#include <linux/module.h>
-#include <platforms/4xx/ppc440spe.h>
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-
-static struct ocp_func_emac_data ppc440spe_emac0_def = {
-	.rgmii_idx	= -1,		/* No RGMII */
-	.rgmii_mux	= -1,		/* No RGMII */
-	.zmii_idx       = -1,           /* No ZMII */
-	.zmii_mux       = -1,           /* No ZMII */
-	.mal_idx        = 0,            /* MAL device index */
-	.mal_rx_chan    = 0,            /* MAL rx channel number */
-	.mal_tx_chan    = 0,            /* MAL tx channel number */
-	.wol_irq        = 61,  		/* WOL interrupt number */
-	.mdio_idx       = -1,           /* No shared MDIO */
-	.tah_idx	= -1,		/* No TAH */
-};
-OCP_SYSFS_EMAC_DATA()
-
-static struct ocp_func_mal_data ppc440spe_mal0_def = {
-	.num_tx_chans   = 1,    	/* Number of TX channels */
-	.num_rx_chans   = 1,    	/* Number of RX channels */
-	.txeob_irq	= 38,		/* TX End Of Buffer IRQ  */
-	.rxeob_irq	= 39,		/* RX End Of Buffer IRQ  */
-	.txde_irq	= 34,		/* TX Descriptor Error IRQ */
-	.rxde_irq	= 35,		/* RX Descriptor Error IRQ */
-	.serr_irq	= 33,		/* MAL System Error IRQ    */
-	.dcr_base	= DCRN_MAL_BASE /* MAL0_CFG DCR number */
-};
-OCP_SYSFS_MAL_DATA()
-
-static struct ocp_func_iic_data ppc440spe_iic0_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-
-static struct ocp_func_iic_data ppc440spe_iic1_def = {
-	.fast_mode	= 0,		/* Use standad mode (100Khz) */
-};
-OCP_SYSFS_IIC_DATA()
-
-struct ocp_def core_ocp[] = {
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= PPC440SPE_UART0_ADDR,
-	  .irq		= UART0_INT,
-	  .pm		= IBM_CPM_UART0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= PPC440SPE_UART1_ADDR,
-	  .irq		= UART1_INT,
-	  .pm		= IBM_CPM_UART1,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 2,
-	  .paddr	= PPC440SPE_UART2_ADDR,
-	  .irq		= UART2_INT,
-	  .pm		= IBM_CPM_UART2,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 0,
-	  .paddr	= 0x00000004f0000400ULL,
-	  .irq		= 2,
-	  .pm		= IBM_CPM_IIC0,
-	  .additions	= &ppc440spe_iic0_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_IIC,
-	  .index	= 1,
-	  .paddr	= 0x00000004f0000500ULL,
-	  .irq		= 3,
-	  .pm		= IBM_CPM_IIC1,
-	  .additions	= &ppc440spe_iic1_def,
-	  .show		= &ocp_show_iic_data
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_GPIO,
-	  .index	= 0,
-	  .paddr	= 0x00000004f0000700ULL,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= IBM_CPM_GPIO0,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_MAL,
-	  .paddr	= OCP_PADDR_NA,
-	  .irq		= OCP_IRQ_NA,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ppc440spe_mal0_def,
-	  .show		= &ocp_show_mal_data,
-	},
-	{ .vendor	= OCP_VENDOR_IBM,
-	  .function	= OCP_FUNC_EMAC,
-	  .index	= 0,
-	  .paddr	= 0x00000004f0000800ULL,
-	  .irq		= 60,
-	  .pm		= OCP_CPM_NA,
-	  .additions	= &ppc440spe_emac0_def,
-	  .show		= &ocp_show_emac_data,
-	},
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
-
-/* Polarity and triggering settings for internal interrupt sources */
-struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
-	{ .polarity     = 0xffffffff,
-	  .triggering   = 0x010f0004,
-	  .ext_irq_mask = 0x00000000,
-	},
-	{ .polarity     = 0xffffffff,
-	  .triggering   = 0x001f8040,
-	  .ext_irq_mask = 0x00007c30,   /* IRQ6 - IRQ7, IRQ8 - IRQ12 */
-	},
-	{ .polarity     = 0xffffffff,
-	  .triggering   = 0x00000000,
-	  .ext_irq_mask = 0x000000fc,   /* IRQ0 - IRQ5 */
-	},
-	{ .polarity     = 0xffffffff,
-	  .triggering   = 0x00000000,
-	  .ext_irq_mask = 0x00000000,
-	},
-};
diff --git a/arch/ppc/platforms/4xx/ppc440spe.h b/arch/ppc/platforms/4xx/ppc440spe.h
deleted file mode 100644
index f1e867c4c9f..00000000000
--- a/arch/ppc/platforms/4xx/ppc440spe.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * PPC440SPe definitions
- *
- * Roland Dreier <rolandd@cisco.com>
- * Copyright (c) 2005 Cisco Systems.  All rights reserved.
- *
- * Matt Porter <mporter@kernel.crashing.org>
- * Copyright 2004-2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifdef __KERNEL__
-#ifndef __PPC_PLATFORMS_PPC440SPE_H
-#define __PPC_PLATFORMS_PPC440SPE_H
-
-
-#include <asm/ibm44x.h>
-
-/* UART */
-#define PPC440SPE_UART0_ADDR	0x00000004f0000200ULL
-#define PPC440SPE_UART1_ADDR	0x00000004f0000300ULL
-#define PPC440SPE_UART2_ADDR	0x00000004f0000600ULL
-#define UART0_INT		0
-#define UART1_INT		1
-#define UART2_INT		37
-
-/* Clock and Power Management */
-#define IBM_CPM_IIC0		0x80000000	/* IIC interface */
-#define IBM_CPM_IIC1		0x40000000	/* IIC interface */
-#define IBM_CPM_PCI		0x20000000	/* PCI bridge */
-#define IBM_CPM_CPU		    0x02000000	/* processor core */
-#define IBM_CPM_DMA		    0x01000000	/* DMA controller */
-#define IBM_CPM_BGO		    0x00800000	/* PLB to OPB bus arbiter */
-#define IBM_CPM_BGI		    0x00400000	/* OPB to PLB bridge */
-#define IBM_CPM_EBC		    0x00200000	/* External Bux Controller */
-#define IBM_CPM_EBM		    0x00100000	/* Ext Bus Master Interface */
-#define IBM_CPM_DMC		    0x00080000	/* SDRAM peripheral controller */
-#define IBM_CPM_PLB		    0x00040000	/* PLB bus arbiter */
-#define IBM_CPM_SRAM		0x00020000	/* SRAM memory controller */
-#define IBM_CPM_PPM		    0x00002000	/* PLB Performance Monitor */
-#define IBM_CPM_UIC1		0x00001000	/* Universal Interrupt Controller */
-#define IBM_CPM_GPIO0		0x00000800	/* General Purpose IO (??) */
-#define IBM_CPM_GPT		    0x00000400	/* General Purpose Timers  */
-#define IBM_CPM_UART0		0x00000200	/* serial port 0 */
-#define IBM_CPM_UART1		0x00000100	/* serial port 1 */
-#define IBM_CPM_UART2		0x00000100	/* serial port 1 */
-#define IBM_CPM_UIC0		0x00000080	/* Universal Interrupt Controller */
-#define IBM_CPM_TMRCLK		0x00000040	/* CPU timers */
-#define IBM_CPM_EMAC0  		0x00000020	/* EMAC 0     */
-
-#define DFLT_IBM4xx_PM		~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
-				| IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
-				| IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
-				| IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
-				| IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
-				| IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
-			  	| IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
-#endif /* __PPC_PLATFORMS_PPC440SP_H */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood5.c b/arch/ppc/platforms/4xx/redwood5.c
deleted file mode 100644
index edf4d37d1a5..00000000000
--- a/arch/ppc/platforms/4xx/redwood5.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Support for the IBM redwood5 eval board file
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/pagemap.h>
-#include <linux/platform_device.h>
-#include <linux/ioport.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ppc4xx_pic.h>
-
-/*
- * Define external IRQ senses and polarities.
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 0 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 3 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 4 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 5 */
-};
-
-static struct resource smc91x_resources[] = {
-	[0] = {
-		.start	= SMC91111_BASE_ADDR,
-		.end	= SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= SMC91111_IRQ,
-		.end	= SMC91111_IRQ,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smc91x_device = {
-	.name		= "smc91x",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(smc91x_resources),
-	.resource	= smc91x_resources,
-};
-
-static struct platform_device *redwood5_devs[] __initdata = {
-	&smc91x_device,
-};
-
-static int __init
-redwood5_platform_add_devices(void)
-{
-	return platform_add_devices(redwood5_devs, ARRAY_SIZE(redwood5_devs));
-}
-
-void __init
-redwood5_setup_arch(void)
-{
-	ppc4xx_setup_arch();
-
-#ifdef CONFIG_DEBUG_BRINGUP
-	printk("\n");
-	printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
-	printk("\n");
-	printk("bi_s_version\t %s\n",      bip->bi_s_version);
-	printk("bi_r_version\t %s\n",      bip->bi_r_version);
-	printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,bip->bi_memsize/(1024*1000));
-	printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
-	bip->bi_enetaddr[0], bip->bi_enetaddr[1],
-	bip->bi_enetaddr[2], bip->bi_enetaddr[3],
-	bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
-
-	printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
-	       bip->bi_intfreq, bip->bi_intfreq/ 1000000);
-
-	printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
-		bip->bi_busfreq, bip->bi_busfreq / 1000000 );
-	printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
-	       bip->bi_tbfreq, bip->bi_tbfreq/1000000);
-
-	printk("\n");
-#endif
-	device_initcall(redwood5_platform_add_devices);
-}
-
-void __init
-redwood5_map_io(void)
-{
-	int i;
-
-	ppc4xx_map_io();
-	for (i = 0; i < 16; i++) {
-	 unsigned long v, p;
-
-	/* 0x400x0000 -> 0xe00x0000 */
-	p = 0x40000000 | (i << 16);
-	v = STB04xxx_IO_BASE | (i << 16);
-
-	io_block_mapping(v, p, PAGE_SIZE,
-		 _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) | _PAGE_GUARDED);
-	}
-
-
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = redwood5_setup_arch;
-	ppc_md.setup_io_mappings = redwood5_map_io;
-}
diff --git a/arch/ppc/platforms/4xx/redwood5.h b/arch/ppc/platforms/4xx/redwood5.h
deleted file mode 100644
index 49edd481897..00000000000
--- a/arch/ppc/platforms/4xx/redwood5.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Macros, definitions, and data structures specific to the IBM PowerPC
- * STB03xxx "Redwood" evaluation board.
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_REDWOOD5_H__
-#define __ASM_REDWOOD5_H__
-
-/* Redwood5 has an STB04xxx core */
-#include <platforms/4xx/ibmstb4.h>
-
-#ifndef __ASSEMBLY__
-typedef struct board_info {
-	unsigned char	bi_s_version[4];	/* Version of this structure */
-	unsigned char	bi_r_version[30];	/* Version of the IBM ROM */
-	unsigned int	bi_memsize;		/* DRAM installed, in bytes */
-	unsigned int	bi_dummy;		/* field shouldn't exist */
-	unsigned char	bi_enetaddr[6];		/* Ethernet MAC address */
-	unsigned int	bi_intfreq;		/* Processor speed, in Hz */
-	unsigned int	bi_busfreq;		/* Bus speed, in Hz */
-	unsigned int	bi_tbfreq;		/* Software timebase freq */
-} bd_t;
-#endif /* !__ASSEMBLY__ */
-
-
-#define SMC91111_BASE_ADDR	0xf2000300
-#define SMC91111_REG_SIZE	16
-#define SMC91111_IRQ		28
-
-#ifdef MAX_HWIFS
-#undef MAX_HWIFS
-#endif
-#define MAX_HWIFS		1
-
-#define _IO_BASE	0
-#define _ISA_MEM_BASE	0
-#define PCI_DRAM_OFFSET	0
-
-#define BASE_BAUD		(378000000 / 18 / 16)
-
-#define PPC4xx_MACHINE_NAME	"IBM Redwood5"
-
-#endif /* __ASM_REDWOOD5_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/redwood6.c b/arch/ppc/platforms/4xx/redwood6.c
deleted file mode 100644
index 006e29f83a1..00000000000
--- a/arch/ppc/platforms/4xx/redwood6.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/init.h>
-#include <linux/pagemap.h>
-#include <linux/platform_device.h>
-#include <linux/ioport.h>
-#include <asm/io.h>
-#include <asm/ppc4xx_pic.h>
-#include <linux/delay.h>
-#include <asm/machdep.h>
-
-/*
- * Define external IRQ senses and polarities.
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 7 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 8 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 9 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 0 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 3 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 4 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 5 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 6 */
-};
-
-static struct resource smc91x_resources[] = {
-	[0] = {
-		.start	= SMC91111_BASE_ADDR,
-		.end	= SMC91111_BASE_ADDR + SMC91111_REG_SIZE - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= SMC91111_IRQ,
-		.end	= SMC91111_IRQ,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smc91x_device = {
-	.name		= "smc91x",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(smc91x_resources),
-	.resource	= smc91x_resources,
-};
-
-static struct platform_device *redwood6_devs[] __initdata = {
-	&smc91x_device,
-};
-
-static int __init
-redwood6_platform_add_devices(void)
-{
-	return platform_add_devices(redwood6_devs, ARRAY_SIZE(redwood6_devs));
-}
-
-
-void __init
-redwood6_setup_arch(void)
-{
-#ifdef CONFIG_IDE
-	void *xilinx, *xilinx_1, *xilinx_2;
-	unsigned short us_reg5;
-#endif
-
-	ppc4xx_setup_arch();
-
-#ifdef CONFIG_IDE
-	xilinx = (unsigned long) ioremap(IDE_XLINUX_MUX_BASE, 0x10);
-	/* init xilinx control registers - enable ide mux, clear reset bit */
-	if (!xilinx) {
-		printk(KERN_CRIT
-		       "redwood6_setup_arch() xilinxi ioremap failed\n");
-		return;
-	}
-	xilinx_1 = xilinx + 0xa;
-	xilinx_2 = xilinx + 0xe;
-
-	us_reg5 = readb(xilinx_1);
-	writeb(0x01d1, xilinx_1);
-	writeb(0x0008, xilinx_2);
-
-	udelay(10 * 1000);
-
-	writeb(0x01d1, xilinx_1);
-	writeb(0x0008, xilinx_2);
-#endif
-
-#ifdef DEBUG_BRINGUP
-	bd_t *bip = (bd_t *) __res;
-	printk("\n");
-	printk("machine\t: %s\n", PPC4xx_MACHINE_NAME);
-	printk("\n");
-	printk("bi_s_version\t %s\n", bip->bi_s_version);
-	printk("bi_r_version\t %s\n", bip->bi_r_version);
-	printk("bi_memsize\t 0x%8.8x\t %dMBytes\n", bip->bi_memsize,
-	       bip->bi_memsize / (1024 * 1000));
-	printk("bi_enetaddr %d\t %2.2x%2.2x%2.2x-%2.2x%2.2x%2.2x\n", 0,
-	       bip->bi_enetaddr[0], bip->bi_enetaddr[1], bip->bi_enetaddr[2],
-	       bip->bi_enetaddr[3], bip->bi_enetaddr[4], bip->bi_enetaddr[5]);
-
-	printk("bi_intfreq\t 0x%8.8x\t clock:\t %dMhz\n",
-	       bip->bi_intfreq, bip->bi_intfreq / 1000000);
-
-	printk("bi_busfreq\t 0x%8.8x\t plb bus clock:\t %dMHz\n",
-	       bip->bi_busfreq, bip->bi_busfreq / 1000000);
-	printk("bi_tbfreq\t 0x%8.8x\t TB freq:\t %dMHz\n",
-	       bip->bi_tbfreq, bip->bi_tbfreq / 1000000);
-
-	printk("\n");
-#endif
-
-	/* Identify the system */
-	printk(KERN_INFO "IBM Redwood6 (STBx25XX) Platform\n");
-	printk(KERN_INFO
-	       "Port by MontaVista Software, Inc. (source@mvista.com)\n");
-
-	device_initcall(redwood6_platform_add_devices);
-}
-
-void __init
-redwood6_map_io(void)
-{
-	int i;
-
-	ppc4xx_map_io();
-	for (i = 0; i < 16; i++) {
-		unsigned long v, p;
-
-		/* 0x400x0000 -> 0xe00x0000 */
-		p = 0x40000000 | (i << 16);
-		v = STBx25xx_IO_BASE | (i << 16);
-
-		io_block_mapping(v, p, PAGE_SIZE,
-				 _PAGE_NO_CACHE | pgprot_val(PAGE_KERNEL) |
-				 _PAGE_GUARDED);
-	}
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = redwood6_setup_arch;
-	ppc_md.setup_io_mappings = redwood6_map_io;
-}
diff --git a/arch/ppc/platforms/4xx/redwood6.h b/arch/ppc/platforms/4xx/redwood6.h
deleted file mode 100644
index 1edcbe5c51c..00000000000
--- a/arch/ppc/platforms/4xx/redwood6.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Macros, definitions, and data structures specific to the IBM PowerPC
- * STBx25xx "Redwood6" evaluation board.
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_REDWOOD5_H__
-#define __ASM_REDWOOD5_H__
-
-/* Redwood6 has an STBx25xx core */
-#include <platforms/4xx/ibmstbx25.h>
-
-#ifndef __ASSEMBLY__
-typedef struct board_info {
-	unsigned char bi_s_version[4];	/* Version of this structure */
-	unsigned char bi_r_version[30];	/* Version of the IBM ROM */
-	unsigned int bi_memsize;	/* DRAM installed, in bytes */
-	unsigned int bi_dummy;	/* field shouldn't exist */
-	unsigned char bi_enetaddr[6];	/* Ethernet MAC address */
-	unsigned int bi_intfreq;	/* Processor speed, in Hz */
-	unsigned int bi_busfreq;	/* Bus speed, in Hz */
-	unsigned int bi_tbfreq;	/* Software timebase freq */
-} bd_t;
-#endif				/* !__ASSEMBLY__ */
-
-#define SMC91111_BASE_ADDR	0xf2030300
-#define SMC91111_REG_SIZE	16
-#define SMC91111_IRQ		27
-#define IDE_XLINUX_MUX_BASE        0xf2040000
-#define IDE_DMA_ADDR	0xfce00000
-
-#ifdef MAX_HWIFS
-#undef MAX_HWIFS
-#endif
-#define MAX_HWIFS		1
-
-#define _IO_BASE	0
-#define _ISA_MEM_BASE	0
-#define PCI_DRAM_OFFSET	0
-
-#define BASE_BAUD		(378000000 / 18 / 16)
-
-#define PPC4xx_MACHINE_NAME	"IBM Redwood6"
-
-#endif				/* __ASM_REDWOOD5_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/sycamore.c b/arch/ppc/platforms/4xx/sycamore.c
deleted file mode 100644
index 8689f3e8ef3..00000000000
--- a/arch/ppc/platforms/4xx/sycamore.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * Architecture- / platform-specific boot-time initialization code for
- * IBM PowerPC 4xx based boards.
- *
- * Author: Armin Kuster <akuster@mvista.com>
- *
- * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/rtc.h>
-
-#include <asm/ocp.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/ibm_ocp_pci.h>
-#include <asm/todc.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-void *kb_cs;
-void *kb_data;
-void *sycamore_rtc_base;
-
-/*
- * Define external IRQ senses and polarities.
- */
-unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 7 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 8 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 9 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 10 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 11 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 12 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 0 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 3 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 4 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 5 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 6 */
-};
-
-
-/* Some IRQs unique to Sycamore.
- * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
- */
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	    /*
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *      A       B       C       D
-	     */
-	{
-		{28, 28, 28, 28},	/* IDSEL 1 - PCI slot 1 */
-		{29, 29, 29, 29},	/* IDSEL 2 - PCI slot 2 */
-		{30, 30, 30, 30},	/* IDSEL 3 - PCI slot 3 */
-		{31, 31, 31, 31},	/* IDSEL 4 - PCI slot 4 */
-	};
-
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-};
-
-void __init
-sycamore_setup_arch(void)
-{
-	void *fpga_brdc;
-	unsigned char fpga_brdc_data;
-	void *fpga_enable;
-	void *fpga_polarity;
-	void *fpga_status;
-	void *fpga_trigger;
-
-	ppc4xx_setup_arch();
-
-	ibm_ocp_set_emac(0, 0);
-
-	kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
-	if (!kb_data) {
-		printk(KERN_CRIT
-		       "sycamore_setup_arch() kb_data ioremap failed\n");
-		return;
-	}
-
-	kb_cs = kb_data + 1;
-
-	fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
-	if (!fpga_status) {
-		printk(KERN_CRIT
-		       "sycamore_setup_arch() fpga_status ioremap failed\n");
-		return;
-	}
-
-	fpga_enable = fpga_status + 1;
-	fpga_polarity = fpga_status + 2;
-	fpga_trigger = fpga_status + 3;
-	fpga_brdc = fpga_status + 4;
-
-	/* split the keyboard and mouse interrupts */
-	fpga_brdc_data = readb(fpga_brdc);
-	fpga_brdc_data |= 0x80;
-	writeb(fpga_brdc_data, fpga_brdc);
-
-	writeb(0x3, fpga_enable);
-
-	writeb(0x3, fpga_polarity);
-
-	writeb(0x3, fpga_trigger);
-
-	/* RTC step for the sycamore */
-	sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
-	TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
-		  sycamore_rtc_base, 8);
-
-	/* Identify the system */
-	printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
-	printk(KERN_INFO
-	       "Port by MontaVista Software, Inc. (source@mvista.com)\n");
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
-	unsigned int bar_response, bar;
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 * The following code is simplified by assuming that the bootrom
-	 * has been well behaved in following this mapping.
-	 */
-
-#ifdef DEBUG
-	int i;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
-	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
-
-	/* Disable region first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Enable inbound region one - 1GB size */
-	out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
-
-	/* Disable outbound region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-
-	/* Disable inbound region two */
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* Disable outbound region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-	/* end workaround */
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-#endif
-
-}
-
-void __init
-sycamore_map_io(void)
-{
-	ppc4xx_map_io();
-	io_block_mapping(SYCAMORE_RTC_VADDR,
-			 SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = sycamore_setup_arch;
-	ppc_md.setup_io_mappings = sycamore_map_io;
-
-#ifdef CONFIG_GEN_RTC
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/sycamore.h b/arch/ppc/platforms/4xx/sycamore.h
deleted file mode 100644
index 69b169eac05..00000000000
--- a/arch/ppc/platforms/4xx/sycamore.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Sycamore board definitions
- *
- * Copyright (c) 2005 DENX Software Engineering
- * Stefan Roese <sr@denx.de>
- *
- * Based on original work by
- * 	Armin Kuster <akuster@mvista.com>
- *	2000 (c) MontaVista, Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_SYCAMORE_H__
-#define __ASM_SYCAMORE_H__
-
-#include <platforms/4xx/ibm405gpr.h>
-#include <asm/ppcboot.h>
-
-/* Memory map for the IBM "Sycamore" 405GPr evaluation board.
- * Generic 4xx plus RTC.
- */
-
-#define SYCAMORE_RTC_PADDR	((uint)0xf0000000)
-#define SYCAMORE_RTC_VADDR	SYCAMORE_RTC_PADDR
-#define SYCAMORE_RTC_SIZE	((uint)8*1024)
-
-#define BASE_BAUD		691200
-
-#define SYCAMORE_PS2_BASE	0xF0100000
-
-/* Flash */
-#define PPC40x_FPGA_BASE	0xF0300000
-#define PPC40x_FPGA_REG_OFFS	5	/* offset to flash map reg */
-#define PPC40x_FLASH_ONBD_N(x)	(x & 0x02)
-#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
-#define PPC40x_FLASH_LOW	0xFFF00000
-#define PPC40x_FLASH_HIGH	0xFFF80000
-#define PPC40x_FLASH_SIZE	0x80000
-
-#define PPC4xx_MACHINE_NAME	"IBM Sycamore"
-
-#endif /* __ASM_SYCAMORE_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/taishan.c b/arch/ppc/platforms/4xx/taishan.c
deleted file mode 100644
index 11569427508..00000000000
--- a/arch/ppc/platforms/4xx/taishan.c
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/taishan.c
- *
- * AMCC Taishan board specific routines
- *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/ndfc.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/bootinfo.h>
-#include <asm/ppcboot.h>
-
-#include <syslib/gen550.h>
-#include <syslib/ibm440gx_common.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-/*
- * NOR FLASH configuration (using mtd physmap driver)
- */
-
-/* start will be added dynamically, end is always fixed */
-static struct resource taishan_nor_resource = {
-	.start = TAISHAN_FLASH_ADDR,
-	.end   = 0x1ffffffffULL,
-	.flags = IORESOURCE_MEM,
-};
-
-#define RW_PART0_OF	0
-#define RW_PART0_SZ	0x180000
-#define RW_PART1_SZ	0x200000
-/* Partition 2 will be autosized dynamically... */
-#define RW_PART3_SZ	0x80000
-#define RW_PART4_SZ	0x40000
-
-static struct mtd_partition taishan_nor_parts[] = {
-	{
-		.name = "kernel",
-		.offset = 0,
-		.size = RW_PART0_SZ
-	},
-	{
-		.name = "root",
-		.offset = MTDPART_OFS_APPEND,
-		.size = RW_PART1_SZ,
-	},
-	{
-		.name = "user",
-		.offset = MTDPART_OFS_APPEND,
-/*		.size = RW_PART2_SZ */ /* will be adjusted dynamically */
-	},
-	{
-		.name = "env",
-		.offset = MTDPART_OFS_APPEND,
-		.size = RW_PART3_SZ,
-	},
-	{
-		.name = "u-boot",
-		.offset = MTDPART_OFS_APPEND,
-		.size = RW_PART4_SZ,
-	}
-};
-
-static struct physmap_flash_data taishan_nor_data = {
-	.width		= 4,
-	.parts		= taishan_nor_parts,
-	.nr_parts	= ARRAY_SIZE(taishan_nor_parts),
-};
-
-static struct platform_device taishan_nor_device = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev = {
-			.platform_data = &taishan_nor_data,
-		},
-	.num_resources	= 1,
-	.resource	= &taishan_nor_resource,
-};
-
-static int taishan_setup_flash(void)
-{
-	/*
-	 * Adjust partition 2 to flash size
-	 */
-	taishan_nor_parts[2].size = __res.bi_flashsize -
-		RW_PART0_SZ - RW_PART1_SZ - RW_PART3_SZ - RW_PART4_SZ;
-
-	platform_device_register(&taishan_nor_device);
-
-	return 0;
-}
-arch_initcall(taishan_setup_flash);
-
-static void __init
-taishan_calibrate_decr(void)
-{
-	unsigned int freq;
-
-	if (mfspr(SPRN_CCR1) & CCR1_TCS)
-		freq = TAISHAN_TMR_CLK;
-	else
-		freq = clocks.cpu;
-
-	ibm44x_calibrate_decr(freq);
-}
-
-static int
-taishan_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: AMCC\n");
-	seq_printf(m, "machine\t\t: PPC440GX EVB (Taishan)\n");
-	ibm440gx_show_cpuinfo(m);
-	return 0;
-}
-
-static inline int
-taishan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *	PCI IDSEL/INTPIN->INTLINE
-	 * 	   A   B   C   D
-	 */
-	{
-		{ 23, 24, 25, 26 },	/* IDSEL 1 - PCI Slot 0 */
-		{ 24, 25, 26, 23 },	/* IDSEL 2 - PCI Slot 1 */
-	};
-
-	const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __init taishan_set_emacdata(void)
-{
-	struct ocp_def *def;
-	struct ocp_func_emac_data *emacdata;
-	int i;
-
-	/* Set phy_map, phy_mode, and mac_addr for each EMAC */
-	for (i=2; i<4; i++) {
-		def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
-		emacdata = def->additions;
-		if (i < 2) {
-			emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
-			emacdata->phy_mode = PHY_MODE_SMII;
-		} else {
-			emacdata->phy_map = 0x00000001; /* Skip 0x00 */
-			emacdata->phy_mode = PHY_MODE_RGMII;
-		}
-		if (i == 0)
-			memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
-		else if (i == 1)
-			memcpy(emacdata->mac_addr, "\0\0\0\0\0\0", 6);
-		else if (i == 2)
-			memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-		else if (i == 3)
-			memcpy(emacdata->mac_addr, __res.bi_enet1addr, 6);
-	}
-}
-
-#define PCIX_READW(offset) \
-	(readw(pcix_reg_base+offset))
-
-#define PCIX_WRITEW(value, offset) \
-	(writew(value, pcix_reg_base+offset))
-
-#define PCIX_WRITEL(value, offset) \
-	(writel(value, pcix_reg_base+offset))
-
-/*
- * FIXME: This is only here to "make it work".  This will move
- * to a ibm_pcix.c which will contain a generic IBM PCIX bridge
- * configuration library. -Matt
- */
-static void __init
-taishan_setup_pcix(void)
-{
-	void *pcix_reg_base;
-
-	pcix_reg_base = ioremap64(PCIX0_REG_BASE, PCIX_REG_SIZE);
-
-	/* Enable PCIX0 I/O, Mem, and Busmaster cycles */
-	PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
-
-	/* Disable all windows */
-	PCIX_WRITEL(0, PCIX0_POM0SA);
-	PCIX_WRITEL(0, PCIX0_POM1SA);
-	PCIX_WRITEL(0, PCIX0_POM2SA);
-	PCIX_WRITEL(0, PCIX0_PIM0SA);
-	PCIX_WRITEL(0, PCIX0_PIM0SAH);
-	PCIX_WRITEL(0, PCIX0_PIM1SA);
-	PCIX_WRITEL(0, PCIX0_PIM2SA);
-	PCIX_WRITEL(0, PCIX0_PIM2SAH);
-
-	/* Setup 2GB PLB->PCI outbound mem window (3_8000_0000->0_8000_0000) */
-	PCIX_WRITEL(0x00000003, PCIX0_POM0LAH);
-	PCIX_WRITEL(0x80000000, PCIX0_POM0LAL);
-	PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
-	PCIX_WRITEL(0x80000000, PCIX0_POM0PCIAL);
-	PCIX_WRITEL(0x80000001, PCIX0_POM0SA);
-
-	/* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
-	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
-	PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
-	PCIX_WRITEL(0x80000007, PCIX0_PIM0SA);
-	PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
-
-	iounmap(pcix_reg_base);
-
-	eieio();
-}
-
-static void __init
-taishan_setup_hose(void)
-{
-	struct pci_controller *hose;
-
-	/* Configure windows on the PCI-X host bridge */
-	taishan_setup_pcix();
-
-	hose = pcibios_alloc_controller();
-
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	hose->pci_mem_offset = TAISHAN_PCI_MEM_OFFSET;
-
-	pci_init_resource(&hose->io_resource,
-			TAISHAN_PCI_LOWER_IO,
-			TAISHAN_PCI_UPPER_IO,
-			IORESOURCE_IO,
-			"PCI host bridge");
-
-	pci_init_resource(&hose->mem_resources[0],
-			TAISHAN_PCI_LOWER_MEM,
-			TAISHAN_PCI_UPPER_MEM,
-			IORESOURCE_MEM,
-			"PCI host bridge");
-
-	hose->io_space.start = TAISHAN_PCI_LOWER_IO;
-	hose->io_space.end = TAISHAN_PCI_UPPER_IO;
-	hose->mem_space.start = TAISHAN_PCI_LOWER_MEM;
-	hose->mem_space.end = TAISHAN_PCI_UPPER_MEM;
-	hose->io_base_virt = ioremap64(TAISHAN_PCI_IO_BASE, TAISHAN_PCI_IO_SIZE);
-	isa_io_base = (unsigned long) hose->io_base_virt;
-
-	setup_indirect_pci(hose,
-			TAISHAN_PCI_CFGA_PLB32,
-			TAISHAN_PCI_CFGD_PLB32);
-	hose->set_cfg_type = 1;
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = taishan_map_irq;
-}
-
-
-static void __init
-taishan_early_serial_map(void)
-{
-	struct uart_port port;
-
-	/* Setup ioremapped serial port access */
-	memset(&port, 0, sizeof(port));
-	port.membase = ioremap64(PPC440GX_UART0_ADDR, 8);
-	port.irq = UART0_INT;
-	port.uartclk = clocks.uart0;
-	port.regshift = 0;
-	port.iotype = UPIO_MEM;
-	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	port.line = 0;
-
-	if (early_serial_setup(&port) != 0)
-		printk("Early serial init of port 0 failed\n");
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(0, &port);
-
-	/* Purge TLB entry added in head_44x.S for early serial access */
-	_tlbie(UART0_IO_BASE, 0);
-#endif
-
-	port.membase = ioremap64(PPC440GX_UART1_ADDR, 8);
-	port.irq = UART1_INT;
-	port.uartclk = clocks.uart1;
-	port.line = 1;
-
-	if (early_serial_setup(&port) != 0)
-		printk("Early serial init of port 1 failed\n");
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	/* Configure debug serial access */
-	gen550_init(1, &port);
-#endif
-}
-
-static void __init
-taishan_setup_arch(void)
-{
-	taishan_set_emacdata();
-
-	ibm440gx_tah_enable();
-
-	/*
-	 * Determine various clocks.
-	 * To be completely correct we should get SysClk
-	 * from FPGA, because it can be changed by on-board switches
-	 * --ebs
-	 */
-	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
-	ocp_sys_info.opb_bus_freq = clocks.opb;
-
-	/* init to some ~sane value until calibrate_delay() runs */
-        loops_per_jiffy = 50000000/HZ;
-
-	/* Setup PCI host bridge */
-	taishan_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_HDA1;
-#endif
-
-	taishan_early_serial_map();
-
-	/* Identify the system */
-	printk("AMCC PowerPC 440GX Taishan Platform\n");
-}
-
-static void __init taishan_init(void)
-{
-	ibm440gx_l2c_setup(&clocks);
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
-		unsigned long r5, unsigned long r6, unsigned long r7)
-{
-	ibm44x_platform_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = taishan_setup_arch;
-	ppc_md.show_cpuinfo = taishan_show_cpuinfo;
-	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
-
-	ppc_md.calibrate_decr = taishan_calibrate_decr;
-
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = taishan_early_serial_map;
-#endif
-	ppc_md.init = taishan_init;
-}
-
diff --git a/arch/ppc/platforms/4xx/taishan.h b/arch/ppc/platforms/4xx/taishan.h
deleted file mode 100644
index ea7561a8045..00000000000
--- a/arch/ppc/platforms/4xx/taishan.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/taishan.h
- *
- * AMCC Taishan board definitions
- *
- * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_TAISHAN_H__
-#define __ASM_TAISHAN_H__
-
-#include <platforms/4xx/ibm440gx.h>
-
-/* External timer clock frequency */
-#define TAISHAN_TMR_CLK	25000000
-
-/* Flash */
-#define TAISHAN_FPGA_ADDR		0x0000000141000000ULL
-#define TAISHAN_LCM_ADDR		0x0000000142000000ULL
-#define TAISHAN_FLASH_ADDR		0x00000001fc000000ULL
-#define TAISHAN_FLASH_SIZE		0x4000000
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE	2
-
-/* head_44x.S created UART mapping, used before early_serial_setup.
- * We cannot use default OpenBIOS UART mappings because they
- * don't work for configurations with more than 512M RAM.    --ebs
- */
-#define UART0_IO_BASE	0xF0000200
-#define UART1_IO_BASE	0xF0000300
-
-#define BASE_BAUD	11059200/16
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (void*)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-
-/* PCI support */
-#define TAISHAN_PCI_LOWER_IO	0x00000000
-#define TAISHAN_PCI_UPPER_IO	0x0000ffff
-#define TAISHAN_PCI_LOWER_MEM	0x80000000
-#define TAISHAN_PCI_UPPER_MEM	0xffffefff
-
-#define TAISHAN_PCI_CFGA_PLB32	0x0ec00000
-#define TAISHAN_PCI_CFGD_PLB32	0x0ec00004
-
-#define TAISHAN_PCI_IO_BASE	0x0000000208000000ULL
-#define TAISHAN_PCI_IO_SIZE	0x00010000
-#define TAISHAN_PCI_MEM_OFFSET	0x00000000
-
-#endif				/* __ASM_TAISHAN_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h
deleted file mode 100644
index 738280420be..00000000000
--- a/arch/ppc/platforms/4xx/virtex.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Basic Virtex platform defines, included by <asm/ibm4xx.h>
- *
- * 2005-2007 (c) Secret Lab Technologies Ltd.
- * 2002-2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_VIRTEX_H__
-#define __ASM_VIRTEX_H__
-
-#include <asm/ibm405.h>
-#include <asm/ppcboot.h>
-
-/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */
-#if !defined(BASE_BAUD)
- #define BASE_BAUD		(0) /* dummy value; not used */
-#endif
-
-#ifndef __ASSEMBLY__
-extern const char* virtex_machine_name;
-#define PPC4xx_MACHINE_NAME (virtex_machine_name)
-#endif /* !__ASSEMBLY__ */
-
-/* We don't need anything mapped.  Size of zero will accomplish that. */
-#define PPC4xx_ONB_IO_PADDR	0u
-#define PPC4xx_ONB_IO_VADDR	0u
-#define PPC4xx_ONB_IO_SIZE	0u
-
-#endif				/* __ASM_VIRTEX_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/walnut.c b/arch/ppc/platforms/4xx/walnut.c
deleted file mode 100644
index 2f977234085..00000000000
--- a/arch/ppc/platforms/4xx/walnut.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * Architecture- / platform-specific boot-time initialization code for
- * IBM PowerPC 4xx based boards. Adapted from original
- * code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
- * <dan@net4x.com>.
- *
- * Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/init.h>
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <linux/rtc.h>
-
-#include <asm/system.h>
-#include <asm/pci-bridge.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/io.h>
-#include <asm/ocp.h>
-#include <asm/ibm_ocp_pci.h>
-#include <asm/todc.h>
-
-#undef DEBUG
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-void *kb_cs;
-void *kb_data;
-void *walnut_rtc_base;
-
-/* Some IRQs unique to Walnut.
- * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
- */
-int __init
-ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	    /*
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *      A       B       C       D
-	     */
-	{
-		{28, 28, 28, 28},	/* IDSEL 1 - PCI slot 1 */
-		{29, 29, 29, 29},	/* IDSEL 2 - PCI slot 2 */
-		{30, 30, 30, 30},	/* IDSEL 3 - PCI slot 3 */
-		{31, 31, 31, 31},	/* IDSEL 4 - PCI slot 4 */
-	};
-
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-};
-
-void __init
-walnut_setup_arch(void)
-{
-
-	void *fpga_brdc;
-	unsigned char fpga_brdc_data;
-	void *fpga_enable;
-	void *fpga_polarity;
-	void *fpga_status;
-	void *fpga_trigger;
-
-	ppc4xx_setup_arch();
-
-	ibm_ocp_set_emac(0, 0);
-
-	kb_data = ioremap(WALNUT_PS2_BASE, 8);
-	if (!kb_data) {
-		printk(KERN_CRIT
-		       "walnut_setup_arch() kb_data ioremap failed\n");
-		return;
-	}
-
-	kb_cs = kb_data + 1;
-
-	fpga_status = ioremap(PPC40x_FPGA_BASE, 8);
-	if (!fpga_status) {
-		printk(KERN_CRIT
-		       "walnut_setup_arch() fpga_status ioremap failed\n");
-		return;
-	}
-
-	fpga_enable = fpga_status + 1;
-	fpga_polarity = fpga_status + 2;
-	fpga_trigger = fpga_status + 3;
-	fpga_brdc = fpga_status + 4;
-
-	/* split the keyboard and mouse interrupts */
-	fpga_brdc_data = readb(fpga_brdc);
-	fpga_brdc_data |= 0x80;
-	writeb(fpga_brdc_data, fpga_brdc);
-
-	writeb(0x3, fpga_enable);
-
-	writeb(0x3, fpga_polarity);
-
-	writeb(0x3, fpga_trigger);
-
-	/* RTC step for the walnut */
-	walnut_rtc_base = (void *) WALNUT_RTC_VADDR;
-	TODC_INIT(TODC_TYPE_DS1743, walnut_rtc_base, walnut_rtc_base,
-		  walnut_rtc_base, 8);
-	/* Identify the system */
-	printk("IBM Walnut port (C) 2000-2002 MontaVista Software, Inc. (source@mvista.com)\n");
-}
-
-void __init
-bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
-{
-#ifdef CONFIG_PCI
-	unsigned int bar_response, bar;
-	/*
-	 * Expected PCI mapping:
-	 *
-	 *  PLB addr             PCI memory addr
-	 *  ---------------------       ---------------------
-	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
-	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
-	 *
-	 *  PLB addr             PCI io addr
-	 *  ---------------------       ---------------------
-	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
-	 *
-	 * The following code is simplified by assuming that the bootrom
-	 * has been well behaved in following this mapping.
-	 */
-
-#ifdef DEBUG
-	int i;
-
-	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
-	printk("PCI bridge regs before fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-
-	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
-
-	/* Disable region first */
-	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
-	/* PLB starting addr, PCI: 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
-	/* PCI start addr, 0x80000000 */
-	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
-	/* 512MB range of PLB to PCI */
-	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
-	/* Enable no pre-fetch, enable region */
-	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
-						(PPC405_PCI_UPPER_MEM -
-						 PPC405_PCI_MEM_BASE)) | 0x01));
-
-	/* Disable region one */
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm1ms), 0x00000000);
-
-	/* Disable region two */
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
-	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
-	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
-
-	/* Zero config bars */
-	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
-		early_write_config_dword(hose, hose->first_busno,
-					 PCI_FUNC(hose->first_busno), bar,
-					 0x00000000);
-		early_read_config_dword(hose, hose->first_busno,
-					PCI_FUNC(hose->first_busno), bar,
-					&bar_response);
-		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
-		    hose->first_busno, PCI_SLOT(hose->first_busno),
-		    PCI_FUNC(hose->first_busno), bar, bar_response);
-	}
-	/* end work around */
-
-#ifdef DEBUG
-	printk("PCI bridge regs after fixup \n");
-	for (i = 0; i <= 3; i++) {
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
-		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
-	}
-	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
-	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
-	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
-	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
-
-#endif
-#endif
-}
-
-void __init
-walnut_map_io(void)
-{
-	ppc4xx_map_io();
-	io_block_mapping(WALNUT_RTC_VADDR,
-			 WALNUT_RTC_PADDR, WALNUT_RTC_SIZE, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = walnut_setup_arch;
-	ppc_md.setup_io_mappings = walnut_map_io;
-
-#ifdef CONFIG_GEN_RTC
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/walnut.h b/arch/ppc/platforms/4xx/walnut.h
deleted file mode 100644
index d9c4eb78894..00000000000
--- a/arch/ppc/platforms/4xx/walnut.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Walnut board definitions
- *
- * Copyright (c) 2005 DENX Software Engineering
- * Stefan Roese <sr@denx.de>
- *
- * Based on original work by
- * 	Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
- *	Frank Rowand <frank_rowand@mvista.com>
- *	Debbie Chu <debbie_chu@mvista.com>
- *	2000 (c) MontaVista, Software, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_WALNUT_H__
-#define __ASM_WALNUT_H__
-
-#include <platforms/4xx/ibm405gp.h>
-#include <asm/ppcboot.h>
-
-/* Memory map for the IBM "Walnut" 405GP evaluation board.
- * Generic 4xx plus RTC.
- */
-
-#define WALNUT_RTC_PADDR	((uint)0xf0000000)
-#define WALNUT_RTC_VADDR	WALNUT_RTC_PADDR
-#define WALNUT_RTC_SIZE		((uint)8*1024)
-
-#define BASE_BAUD		691200
-
-#define WALNUT_PS2_BASE		0xF0100000
-
-/* Flash */
-#define PPC40x_FPGA_BASE	0xF0300000
-#define PPC40x_FPGA_REG_OFFS	5	/* offset to flash map reg */
-#define PPC40x_FLASH_ONBD_N(x)	(x & 0x02)
-#define PPC40x_FLASH_SRAM_SEL(x) (x & 0x01)
-#define PPC40x_FLASH_LOW	0xFFF00000
-#define PPC40x_FLASH_HIGH	0xFFF80000
-#define PPC40x_FLASH_SIZE	0x80000
-#define WALNUT_FPGA_BASE	PPC40x_FPGA_BASE
-
-#define PPC4xx_MACHINE_NAME	"IBM Walnut"
-
-#endif /* __ASM_WALNUT_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c
deleted file mode 100644
index 6e522fefc26..00000000000
--- a/arch/ppc/platforms/4xx/xilinx_ml300.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Xilinx ML300 evaluation board initialization
- *
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * 2002-2004 (c) MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/serialP.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-
-#include <syslib/gen550.h>
-#include <syslib/virtex_devices.h>
-#include <platforms/4xx/xparameters/xparameters.h>
-
-/*
- * As an overview of how the following functions (platform_init,
- * ml300_map_io, ml300_setup_arch and ml300_init_IRQ) fit into the
- * kernel startup procedure, here's a call tree:
- *
- * start_here					arch/ppc/kernel/head_4xx.S
- *  early_init					arch/ppc/kernel/setup.c
- *  machine_init				arch/ppc/kernel/setup.c
- *    platform_init				this file
- *      ppc4xx_init				arch/ppc/syslib/ppc4xx_setup.c
- *        parse_bootinfo
- *          find_bootinfo
- *        "setup some default ppc_md pointers"
- *  MMU_init					arch/ppc/mm/init.c
- *    *ppc_md.setup_io_mappings == ml300_map_io	this file
- *      ppc4xx_map_io				arch/ppc/syslib/ppc4xx_setup.c
- *  start_kernel				init/main.c
- *    setup_arch				arch/ppc/kernel/setup.c
- * #if defined(CONFIG_KGDB)
- *      *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
- * #endif
- *      *ppc_md.setup_arch == ml300_setup_arch	this file
- *        ppc4xx_setup_arch			arch/ppc/syslib/ppc4xx_setup.c
- *          ppc4xx_find_bridges			arch/ppc/syslib/ppc405_pci.c
- *    init_IRQ					arch/ppc/kernel/irq.c
- *      *ppc_md.init_IRQ == ml300_init_IRQ	this file
- *        ppc4xx_init_IRQ			arch/ppc/syslib/ppc4xx_setup.c
- *          ppc4xx_pic_init			arch/ppc/syslib/xilinx_pic.c
- */
-
-const char* virtex_machine_name = "ML300 Reference Design";
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
-static volatile unsigned *powerdown_base =
-    (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
-
-static void
-xilinx_power_off(void)
-{
-	local_irq_disable();
-	out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
-	while (1) ;
-}
-#endif
-
-void __init
-ml300_map_io(void)
-{
-	ppc4xx_map_io();
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
-	powerdown_base = ioremap((unsigned long) powerdown_base,
-				 XPAR_POWER_0_POWERDOWN_HIGHADDR -
-				 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
-#endif
-}
-
-void __init
-ml300_setup_arch(void)
-{
-	virtex_early_serial_map();
-	ppc4xx_setup_arch();	/* calls ppc4xx_find_bridges() */
-
-	/* Identify the system */
-	printk(KERN_INFO "Xilinx ML300 Reference System (Virtex-II Pro)\n");
-}
-
-/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
-void __init
-ml300_init_irq(void)
-{
-	ppc4xx_init_IRQ();
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = ml300_setup_arch;
-	ppc_md.setup_io_mappings = ml300_map_io;
-	ppc_md.init_IRQ = ml300_init_irq;
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
-	ppc_md.power_off = xilinx_power_off;
-#endif
-
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = virtex_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c
deleted file mode 100644
index bc3ace3762e..00000000000
--- a/arch/ppc/platforms/4xx/xilinx_ml403.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Xilinx ML403 evaluation board initialization
- *
- * Author: Grant Likely <grant.likely@secretlab.ca>
- *
- * 2005-2007 (c) Secret Lab Technologies Ltd.
- * 2002-2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/serialP.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-
-#include <syslib/gen550.h>
-#include <syslib/virtex_devices.h>
-#include <platforms/4xx/xparameters/xparameters.h>
-
-/*
- * As an overview of how the following functions (platform_init,
- * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the
- * kernel startup procedure, here's a call tree:
- *
- * start_here					arch/ppc/kernel/head_4xx.S
- *  early_init					arch/ppc/kernel/setup.c
- *  machine_init				arch/ppc/kernel/setup.c
- *    platform_init				this file
- *      ppc4xx_init				arch/ppc/syslib/ppc4xx_setup.c
- *        parse_bootinfo
- *          find_bootinfo
- *        "setup some default ppc_md pointers"
- *  MMU_init					arch/ppc/mm/init.c
- *    *ppc_md.setup_io_mappings == ml403_map_io	this file
- *      ppc4xx_map_io				arch/ppc/syslib/ppc4xx_setup.c
- *  start_kernel				init/main.c
- *    setup_arch				arch/ppc/kernel/setup.c
- * #if defined(CONFIG_KGDB)
- *      *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
- * #endif
- *      *ppc_md.setup_arch == ml403_setup_arch	this file
- *        ppc4xx_setup_arch			arch/ppc/syslib/ppc4xx_setup.c
- *          ppc4xx_find_bridges			arch/ppc/syslib/ppc405_pci.c
- *    init_IRQ					arch/ppc/kernel/irq.c
- *      *ppc_md.init_IRQ == ml403_init_IRQ	this file
- *        ppc4xx_init_IRQ			arch/ppc/syslib/ppc4xx_setup.c
- *          ppc4xx_pic_init			arch/ppc/syslib/xilinx_pic.c
- */
-
-const char* virtex_machine_name = "ML403 Reference Design";
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
-static volatile unsigned *powerdown_base =
-    (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
-
-static void
-xilinx_power_off(void)
-{
-	local_irq_disable();
-	out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
-	while (1) ;
-}
-#endif
-
-void __init
-ml403_map_io(void)
-{
-	ppc4xx_map_io();
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
-	powerdown_base = ioremap((unsigned long) powerdown_base,
-				 XPAR_POWER_0_POWERDOWN_HIGHADDR -
-				 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
-#endif
-}
-
-void __init
-ml403_setup_arch(void)
-{
-	virtex_early_serial_map();
-	ppc4xx_setup_arch();	/* calls ppc4xx_find_bridges() */
-
-	/* Identify the system */
-	printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n");
-}
-
-/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
-void __init
-ml403_init_irq(void)
-{
-	ppc4xx_init_IRQ();
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	ppc4xx_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = ml403_setup_arch;
-	ppc_md.setup_io_mappings = ml403_map_io;
-	ppc_md.init_IRQ = ml403_init_irq;
-
-#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
-	ppc_md.power_off = xilinx_power_off;
-#endif
-
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = virtex_early_serial_map;
-#endif
-}
-
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h
deleted file mode 100644
index 650888b00fb..00000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/xparameters/xparameters.h
- *
- * This file includes the correct xparameters.h for the CONFIG'ed board plus
- * fixups to translate board specific XPAR values to a common set of names
- *
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * 2004 (c) MontaVista Software, Inc.  This file is licensed under the terms
- * of the GNU General Public License version 2.  This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-
-#if defined(CONFIG_XILINX_ML300)
-  #include "xparameters_ml300.h"
-  #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
-	XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
-  #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
-	XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
-#elif defined(CONFIG_XILINX_ML403)
-  #include "xparameters_ml403.h"
-  #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_PLAYBACK_VEC_ID \
-	XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR
-  #define XPAR_INTC_0_AC97_CONTROLLER_REF_0_RECORD_VEC_ID \
-	XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR
-#else
-  /* Add other board xparameter includes here before the #else */
-  #error No xparameters_*.h file included
-#endif
-
-#ifndef SERIAL_PORT_DFNS
-  /* zImage serial port definitions */
-  #define RS_TABLE_SIZE 1
-  #define SERIAL_PORT_DFNS {						\
-	.baud_base	 = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16,		\
-	.irq		 = XPAR_INTC_0_UARTNS550_0_VEC_ID,		\
-	.flags		 = ASYNC_BOOT_AUTOCONF,				\
-	.iomem_base	 = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3,		\
-	.iomem_reg_shift = 2,						\
-	.io_type	 = SERIAL_IO_MEM,				\
-  },
-#endif
-
-/*
- * A few reasonable defaults for the #defines which could be missing depending
- * on the IP version or variant (e.g. OPB vs PLB)
- */
-
-#ifndef XPAR_EMAC_0_CAM_EXIST
-#define XPAR_EMAC_0_CAM_EXIST 0
-#endif
-#ifndef XPAR_EMAC_0_JUMBO_EXIST
-#define XPAR_EMAC_0_JUMBO_EXIST 0
-#endif
-#ifndef XPAR_EMAC_0_TX_DRE_TYPE
-#define XPAR_EMAC_0_TX_DRE_TYPE 0
-#endif
-#ifndef XPAR_EMAC_0_RX_DRE_TYPE
-#define XPAR_EMAC_0_RX_DRE_TYPE 0
-#endif
-#ifndef XPAR_EMAC_0_TX_INCLUDE_CSUM
-#define XPAR_EMAC_0_TX_INCLUDE_CSUM 0
-#endif
-#ifndef XPAR_EMAC_0_RX_INCLUDE_CSUM
-#define XPAR_EMAC_0_RX_INCLUDE_CSUM 0
-#endif
-
-#ifndef XPAR_EMAC_1_CAM_EXIST
-#define XPAR_EMAC_1_CAM_EXIST 0
-#endif
-#ifndef XPAR_EMAC_1_JUMBO_EXIST
-#define XPAR_EMAC_1_JUMBO_EXIST 0
-#endif
-#ifndef XPAR_EMAC_1_TX_DRE_TYPE
-#define XPAR_EMAC_1_TX_DRE_TYPE 0
-#endif
-#ifndef XPAR_EMAC_1_RX_DRE_TYPE
-#define XPAR_EMAC_1_RX_DRE_TYPE 0
-#endif
-#ifndef XPAR_EMAC_1_TX_INCLUDE_CSUM
-#define XPAR_EMAC_1_TX_INCLUDE_CSUM 0
-#endif
-#ifndef XPAR_EMAC_1_RX_INCLUDE_CSUM
-#define XPAR_EMAC_1_RX_INCLUDE_CSUM 0
-#endif
-
-#ifndef XPAR_GPIO_0_IS_DUAL
-#define XPAR_GPIO_0_IS_DUAL 0
-#endif
-#ifndef XPAR_GPIO_1_IS_DUAL
-#define XPAR_GPIO_1_IS_DUAL 0
-#endif
-#ifndef XPAR_GPIO_2_IS_DUAL
-#define XPAR_GPIO_2_IS_DUAL 0
-#endif
-#ifndef XPAR_GPIO_3_IS_DUAL
-#define XPAR_GPIO_3_IS_DUAL 0
-#endif
-#ifndef XPAR_GPIO_4_IS_DUAL
-#define XPAR_GPIO_4_IS_DUAL 0
-#endif
-
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
deleted file mode 100644
index 97e3f4d4bd5..00000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml300.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*******************************************************************
-*
-*     Author: Xilinx, Inc.
-*
-*
-*     This program is free software; you can redistribute it and/or modify it
-*     under the terms of the GNU General Public License as published by the
-*     Free Software Foundation; either version 2 of the License, or (at your
-*     option) any later version.
-*
-*
-*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
-*     COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-*     ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD,
-*     XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-*     FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING
-*     ANY THIRD PARTY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
-*     XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
-*     THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY
-*     WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM
-*     CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND
-*     FITNESS FOR A PARTICULAR PURPOSE.
-*
-*
-*     Xilinx hardware products are not intended for use in life support
-*     appliances, devices, or systems. Use in such applications is
-*     expressly prohibited.
-*
-*
-*     (c) Copyright 2002-2004 Xilinx Inc.
-*     All rights reserved.
-*
-*
-*     You should have received a copy of the GNU General Public License along
-*     with this program; if not, write to the Free Software Foundation, Inc.,
-*     675 Mass Ave, Cambridge, MA 02139, USA.
-*
-* Description: Driver parameters
-*
-*******************************************************************/
-
-#define XPAR_XPCI_NUM_INSTANCES 1
-#define XPAR_XPCI_CLOCK_HZ 33333333
-#define XPAR_OPB_PCI_REF_0_DEVICE_ID 0
-#define XPAR_OPB_PCI_REF_0_BASEADDR 0x20000000
-#define XPAR_OPB_PCI_REF_0_HIGHADDR 0x3FFFFFFF
-#define XPAR_OPB_PCI_REF_0_CONFIG_ADDR 0x3C000000
-#define XPAR_OPB_PCI_REF_0_CONFIG_DATA 0x3C000004
-#define XPAR_OPB_PCI_REF_0_LCONFIG_ADDR 0x3E000000
-#define XPAR_OPB_PCI_REF_0_MEM_BASEADDR 0x20000000
-#define XPAR_OPB_PCI_REF_0_MEM_HIGHADDR 0x37FFFFFF
-#define XPAR_OPB_PCI_REF_0_IO_BASEADDR 0x38000000
-#define XPAR_OPB_PCI_REF_0_IO_HIGHADDR 0x3BFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XEMAC_NUM_INSTANCES 1
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
-
-/******************************************************************/
-
-#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_0 0
-#define XPAR_MY_OPB_GPIO_0_BASEADDR_0 0x90000000
-#define XPAR_MY_OPB_GPIO_0_HIGHADDR_0 (0x90000000+0x7)
-#define XPAR_MY_OPB_GPIO_0_DEVICE_ID_1 1
-#define XPAR_MY_OPB_GPIO_0_BASEADDR_1 (0x90000000+0x8)
-#define XPAR_MY_OPB_GPIO_0_HIGHADDR_1 (0x90000000+0x1F)
-#define XPAR_XGPIO_NUM_INSTANCES 2
-
-/******************************************************************/
-
-#define XPAR_XIIC_NUM_INSTANCES 1
-#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
-#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
-#define XPAR_OPB_IIC_0_DEVICE_ID 0
-#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
-
-/******************************************************************/
-
-#define XPAR_XUARTNS550_NUM_INSTANCES 2
-#define XPAR_XUARTNS550_CLOCK_HZ 100000000
-#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
-#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
-#define XPAR_OPB_UART16550_0_DEVICE_ID 0
-#define XPAR_OPB_UART16550_1_BASEADDR 0xA0010000
-#define XPAR_OPB_UART16550_1_HIGHADDR 0xA0011FFF
-#define XPAR_OPB_UART16550_1_DEVICE_ID 1
-
-/******************************************************************/
-
-#define XPAR_XSPI_NUM_INSTANCES 1
-#define XPAR_OPB_SPI_0_BASEADDR 0xA4000000
-#define XPAR_OPB_SPI_0_HIGHADDR 0xA400007F
-#define XPAR_OPB_SPI_0_DEVICE_ID 0
-#define XPAR_OPB_SPI_0_FIFO_EXIST 1
-#define XPAR_OPB_SPI_0_SPI_SLAVE_ONLY 0
-#define XPAR_OPB_SPI_0_NUM_SS_BITS 1
-
-/******************************************************************/
-
-#define XPAR_XPS2_NUM_INSTANCES 2
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
-
-/******************************************************************/
-
-#define XPAR_XTOUCHSCREEN_NUM_INSTANCES 1
-#define XPAR_OPB_TSD_REF_0_BASEADDR 0xAA000000
-#define XPAR_OPB_TSD_REF_0_HIGHADDR 0xAA000007
-#define XPAR_OPB_TSD_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
-#define XPAR_OPB_PAR_PORT_REF_0_BASEADDR 0x90010000
-#define XPAR_OPB_PAR_PORT_REF_0_HIGHADDR 0x900100FF
-#define XPAR_PLB_DDR_0_BASEADDR 0x00000000
-#define XPAR_PLB_DDR_0_HIGHADDR 0x0FFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 18
-#define XPAR_XINTC_USE_DCR 0
-#define XPAR_XINTC_NUM_INSTANCES 1
-#define XPAR_DCR_INTC_0_BASEADDR 0xD0000FC0
-#define XPAR_DCR_INTC_0_HIGHADDR 0xD0000FDF
-#define XPAR_DCR_INTC_0_DEVICE_ID 0
-#define XPAR_DCR_INTC_0_KIND_OF_INTR 0x00038000
-
-/******************************************************************/
-
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 0
-#define XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 1
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_TEMP_CRIT_INTR 2
-#define XPAR_DCR_INTC_0_MISC_LOGIC_0_IIC_IRQ_INTR 3
-#define XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 4
-#define XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 5
-#define XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 6
-#define XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR 7
-#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
-#define XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 9
-#define XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR 10
-#define XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR 11
-#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 12
-#define XPAR_DCR_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 13
-#define XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR 14
-#define XPAR_DCR_INTC_0_PLB2OPB_BRIDGE_0_BUS_ERROR_DET_INTR 15
-#define XPAR_DCR_INTC_0_PLB_V34_0_BUS_ERROR_DET_INTR 16
-#define XPAR_DCR_INTC_0_OPB2PLB_BRIDGE_0_BUS_ERROR_DET_INTR 17
-
-/******************************************************************/
-
-#define XPAR_XTFT_NUM_INSTANCES 1
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
-#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_XSYSACE_MEM_WIDTH 8
-#define XPAR_XSYSACE_NUM_INSTANCES 1
-#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
-#define XPAR_OPB_SYSACE_0_MEM_WIDTH 8
-
-/******************************************************************/
-
-#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
-
-/******************************************************************/
-
-/******************************************************************/
-
-/* Linux Redefines */
-
-/******************************************************************/
-
-#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
-#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
-#define XPAR_UARTNS550_1_BASEADDR (XPAR_OPB_UART16550_1_BASEADDR+0x1000)
-#define XPAR_UARTNS550_1_HIGHADDR XPAR_OPB_UART16550_1_HIGHADDR
-#define XPAR_UARTNS550_1_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_1_DEVICE_ID XPAR_OPB_UART16550_1_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_GPIO_0_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_0
-#define XPAR_GPIO_0_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_0
-#define XPAR_GPIO_0_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_0
-#define XPAR_GPIO_1_BASEADDR XPAR_MY_OPB_GPIO_0_BASEADDR_1
-#define XPAR_GPIO_1_HIGHADDR XPAR_MY_OPB_GPIO_0_HIGHADDR_1
-#define XPAR_GPIO_1_DEVICE_ID XPAR_MY_OPB_GPIO_0_DEVICE_ID_1
-
-/******************************************************************/
-
-#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
-#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
-#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
-#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
-#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
-#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_INTC_0_BASEADDR XPAR_DCR_INTC_0_BASEADDR
-#define XPAR_INTC_0_HIGHADDR XPAR_DCR_INTC_0_HIGHADDR
-#define XPAR_INTC_0_KIND_OF_INTR XPAR_DCR_INTC_0_KIND_OF_INTR
-#define XPAR_INTC_0_DEVICE_ID XPAR_DCR_INTC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_DCR_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_DCR_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_DCR_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
-#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_UARTNS550_1_VEC_ID XPAR_DCR_INTC_0_OPB_UART16550_1_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
-#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_DCR_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
-#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_DCR_INTC_0_OPB_SPI_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_TOUCHSCREEN_0_VEC_ID XPAR_DCR_INTC_0_OPB_TSD_REF_0_INTR_INTR
-#define XPAR_INTC_0_PCI_0_VEC_ID_A XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
-#define XPAR_INTC_0_PCI_0_VEC_ID_B XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
-#define XPAR_INTC_0_PCI_0_VEC_ID_C XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
-#define XPAR_INTC_0_PCI_0_VEC_ID_D XPAR_DCR_INTC_0_OPB_PCI_REF_0_INTR_OUT_INTR
-
-/******************************************************************/
-
-#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
-#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
-#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
-#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
-#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
-#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_SPI_0_BASEADDR XPAR_OPB_SPI_0_BASEADDR
-#define XPAR_SPI_0_HIGHADDR XPAR_OPB_SPI_0_HIGHADDR
-#define XPAR_SPI_0_DEVICE_ID XPAR_OPB_SPI_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_TOUCHSCREEN_0_BASEADDR XPAR_OPB_TSD_REF_0_BASEADDR
-#define XPAR_TOUCHSCREEN_0_HIGHADDR XPAR_OPB_TSD_REF_0_HIGHADDR
-#define XPAR_TOUCHSCREEN_0_DEVICE_ID XPAR_OPB_TSD_REF_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
-
-/******************************************************************/
-
-#define XPAR_PCI_0_BASEADDR XPAR_OPB_PCI_REF_0_BASEADDR
-#define XPAR_PCI_0_HIGHADDR XPAR_OPB_PCI_REF_0_HIGHADDR
-#define XPAR_PCI_0_CONFIG_ADDR XPAR_OPB_PCI_REF_0_CONFIG_ADDR
-#define XPAR_PCI_0_CONFIG_DATA XPAR_OPB_PCI_REF_0_CONFIG_DATA
-#define XPAR_PCI_0_LCONFIG_ADDR XPAR_OPB_PCI_REF_0_LCONFIG_ADDR
-#define XPAR_PCI_0_MEM_BASEADDR XPAR_OPB_PCI_REF_0_MEM_BASEADDR
-#define XPAR_PCI_0_MEM_HIGHADDR XPAR_OPB_PCI_REF_0_MEM_HIGHADDR
-#define XPAR_PCI_0_IO_BASEADDR XPAR_OPB_PCI_REF_0_IO_BASEADDR
-#define XPAR_PCI_0_IO_HIGHADDR XPAR_OPB_PCI_REF_0_IO_HIGHADDR
-#define XPAR_PCI_0_CLOCK_FREQ_HZ XPAR_XPCI_CLOCK_HZ
-#define XPAR_PCI_0_DEVICE_ID XPAR_OPB_PCI_REF_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
-#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
-#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
-#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
-#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
-#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
-
-/******************************************************************/
-
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
-#define XPAR_DDR_0_SIZE 0x08000000
-
-/******************************************************************/
-
-#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
-#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
-#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
-
-/******************************************************************/
-
-#define XPAR_POWER_0_POWERDOWN_BASEADDR 0x90000004
-#define XPAR_POWER_0_POWERDOWN_HIGHADDR 0x90000007
-#define XPAR_POWER_0_POWERDOWN_VALUE 0xFF
-
-/******************************************************************/
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
deleted file mode 100644
index 5cacdcb3964..00000000000
--- a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
+++ /dev/null
@@ -1,243 +0,0 @@
-
-/*******************************************************************
-*
-* CAUTION: This file is automatically generated by libgen.
-* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
-* DO NOT EDIT.
-*
-* Copyright (c) 2005 Xilinx, Inc.  All rights reserved. 
-* 
-* Description: Driver parameters
-*
-*******************************************************************/
-
-#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
-#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
-
-/******************************************************************/
-
-#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000
-#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF
-#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000
-#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
-#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000
-#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF
-#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000
-#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF
-
-/******************************************************************/
-
-#define XPAR_XEMAC_NUM_INSTANCES 1
-#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
-#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
-#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
-#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
-#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
-
-/******************************************************************/
-
-#define XPAR_XUARTNS550_NUM_INSTANCES 1
-#define XPAR_XUARTNS550_CLOCK_HZ 100000000
-#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
-#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
-#define XPAR_OPB_UART16550_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_XGPIO_NUM_INSTANCES 3
-#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000
-#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF
-#define XPAR_OPB_GPIO_0_DEVICE_ID 0
-#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_0_IS_DUAL 1
-#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000
-#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF
-#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1
-#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1
-#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000
-#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF
-#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2
-#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0
-#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0
-
-/******************************************************************/
-
-#define XPAR_XPS2_NUM_INSTANCES 2
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
-#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
-#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
-#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
-
-/******************************************************************/
-
-#define XPAR_XIIC_NUM_INSTANCES 1
-#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
-#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
-#define XPAR_OPB_IIC_0_DEVICE_ID 0
-#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
-#define XPAR_OPB_IIC_0_GPO_WIDTH 1
-
-/******************************************************************/
-
-#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10
-#define XPAR_XINTC_HAS_IPR 1
-#define XPAR_XINTC_USE_DCR 0
-#define XPAR_XINTC_NUM_INSTANCES 1
-#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0
-#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF
-#define XPAR_OPB_INTC_0_DEVICE_ID 0
-#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
-
-/******************************************************************/
-
-#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0
-#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF
-#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
-#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001
-#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0
-#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002
-#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1
-#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004
-#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2
-#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008
-#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010
-#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4
-#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020
-#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5
-#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040
-#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6
-#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080
-#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7
-#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100
-#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
-#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200
-#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9
-
-/******************************************************************/
-
-#define XPAR_XTFT_NUM_INSTANCES 1
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
-#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
-#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
-
-/******************************************************************/
-
-#define XPAR_XSYSACE_MEM_WIDTH 16
-#define XPAR_XSYSACE_NUM_INSTANCES 1
-#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
-#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
-#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
-#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16
-
-/******************************************************************/
-
-#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
-
-/******************************************************************/
-
-
-/******************************************************************/
-
-/* Linux Redefines */
-
-/******************************************************************/
-
-#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
-#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
-#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
-#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
-#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
-#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
-#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
-#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
-#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
-#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
-#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
-
-/******************************************************************/
-
-#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
-
-/******************************************************************/
-
-#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
-#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
-#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
-#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
-#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
-#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0
-#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0
-#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0
-#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1
-#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1
-#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1
-#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0
-#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0
-#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0
-#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1
-#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1
-#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1
-#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR
-#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR
-#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
-#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
-#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
-#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
-#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
-#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
-
-/******************************************************************/
-
-#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
-#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
-#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
-#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
-#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
-#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
-
-/******************************************************************/
-
-#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
-#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
-#define XPAR_DDR_0_SIZE 0x4000000
-
-/******************************************************************/
-
-#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
-#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
-#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
-
-/******************************************************************/
-
-#define XPAR_PCI_0_CLOCK_FREQ_HZ    0
-
-/******************************************************************/
-
diff --git a/arch/ppc/platforms/4xx/yucca.c b/arch/ppc/platforms/4xx/yucca.c
deleted file mode 100644
index f6cfd44281f..00000000000
--- a/arch/ppc/platforms/4xx/yucca.c
+++ /dev/null
@@ -1,393 +0,0 @@
-/*
- * Yucca board specific routines
- *
- * Roland Dreier <rolandd@cisco.com> (based on luan.c by Matt Porter)
- *
- * Copyright 2004-2005 MontaVista Software Inc.
- * Copyright (c) 2005 Cisco Systems.  All rights reserved.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/tty.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/ocp.h>
-#include <asm/pci-bridge.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppc4xx_pic.h>
-#include <asm/ppcboot.h>
-
-#include <syslib/ibm44x_common.h>
-#include <syslib/ibm440gx_common.h>
-#include <syslib/ibm440sp_common.h>
-#include <syslib/ppc440spe_pcie.h>
-
-extern bd_t __res;
-
-static struct ibm44x_clocks clocks __initdata;
-
-static void __init
-yucca_calibrate_decr(void)
-{
-	unsigned int freq;
-
-	if (mfspr(SPRN_CCR1) & CCR1_TCS)
-		freq = YUCCA_TMR_CLK;
-	else
-		freq = clocks.cpu;
-
-	ibm44x_calibrate_decr(freq);
-}
-
-static int
-yucca_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: AMCC\n");
-	seq_printf(m, "machine\t\t: PPC440SPe EVB (Yucca)\n");
-
-	return 0;
-}
-
-static enum {
-	HOSE_UNKNOWN,
-	HOSE_PCIX,
-	HOSE_PCIE0,
-	HOSE_PCIE1,
-	HOSE_PCIE2
-} hose_type[4];
-
-static inline int
-yucca_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
-
-	if (hose_type[hose->index] == HOSE_PCIX) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 *	  A   B   C   D
-		 */
-		{
-			{ 81, -1, -1, -1 },	/* IDSEL 1 - PCIX0 Slot 0 */
-		};
-		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	} else if (hose_type[hose->index] == HOSE_PCIE0) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 *	  A   B   C   D
-		 */
-		{
-			{ 96, 97, 98, 99 },
-		};
-		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	} else if (hose_type[hose->index] == HOSE_PCIE1) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 *	  A   B   C   D
-		 */
-		{
-			{ 100, 101, 102, 103 },
-		};
-		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	} else if (hose_type[hose->index] == HOSE_PCIE2) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 *	  A   B   C   D
-		 */
-		{
-			{ 104, 105, 106, 107 },
-		};
-		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-	return -1;
-}
-
-static void __init yucca_set_emacdata(void)
-{
-	struct ocp_def *def;
-	struct ocp_func_emac_data *emacdata;
-
-	/* Set phy_map, phy_mode, and mac_addr for the EMAC */
-	def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
-	emacdata = def->additions;
-	emacdata->phy_map = 0x00000001;	/* Skip 0x00 */
-	emacdata->phy_mode = PHY_MODE_GMII;
-	memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
-}
-
-static int __init yucca_pcie_card_present(int port)
-{
-   void __iomem *pcie_fpga_base;
-   u16 reg;
-
-   pcie_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
-   reg = in_be16(pcie_fpga_base + FPGA_REG1C);
-   iounmap(pcie_fpga_base);
-
-   switch(port) {
-   case 0: return !(reg & FPGA_REG1C_PE0_PRSNT);
-   case 1: return !(reg & FPGA_REG1C_PE1_PRSNT);
-   case 2: return !(reg & FPGA_REG1C_PE2_PRSNT);
-   default: return 0;
-   }
-}
-
-/*
- * For the given slot, set rootpoint mode, send power to the slot,
- * turn on the green LED and turn off the yellow LED, enable the clock
- * and turn off reset.
- */
-static void __init yucca_setup_pcie_fpga_rootpoint(int port)
-{
-	void __iomem *pcie_reg_fpga_base;
-	u16 power, clock, green_led, yellow_led, reset_off, rootpoint, endpoint;
-
-	pcie_reg_fpga_base = ioremap64(YUCCA_FPGA_REG_BASE, YUCCA_FPGA_REG_SIZE);
-
-	switch(port) {
-	case 0:
-		rootpoint   = FPGA_REG1C_PE0_ROOTPOINT;
-		endpoint    = 0;
-		power 	    = FPGA_REG1A_PE0_PWRON;
-		green_led   = FPGA_REG1A_PE0_GLED;
-		clock 	    = FPGA_REG1A_PE0_REFCLK_ENABLE;
-		yellow_led  = FPGA_REG1A_PE0_YLED;
-		reset_off   = FPGA_REG1C_PE0_PERST;
-		break;
-	case 1:
-		rootpoint   = 0;
-		endpoint    = FPGA_REG1C_PE1_ENDPOINT;
-		power 	    = FPGA_REG1A_PE1_PWRON;
-		green_led   = FPGA_REG1A_PE1_GLED;
-		clock 	    = FPGA_REG1A_PE1_REFCLK_ENABLE;
-		yellow_led  = FPGA_REG1A_PE1_YLED;
-		reset_off   = FPGA_REG1C_PE1_PERST;
-		break;
-	case 2:
-		rootpoint   = 0;
-		endpoint    = FPGA_REG1C_PE2_ENDPOINT;
-		power 	    = FPGA_REG1A_PE2_PWRON;
-		green_led   = FPGA_REG1A_PE2_GLED;
-		clock 	    = FPGA_REG1A_PE2_REFCLK_ENABLE;
-		yellow_led  = FPGA_REG1A_PE2_YLED;
-		reset_off   = FPGA_REG1C_PE2_PERST;
-		break;
-
-	default:
-		iounmap(pcie_reg_fpga_base);
-		return;
-	}
-
-	out_be16(pcie_reg_fpga_base + FPGA_REG1A,
-		 ~(power | clock | green_led) &
-		 (yellow_led | in_be16(pcie_reg_fpga_base + FPGA_REG1A)));
-	out_be16(pcie_reg_fpga_base + FPGA_REG1C,
-		 ~(endpoint | reset_off) &
-		 (rootpoint | in_be16(pcie_reg_fpga_base + FPGA_REG1C)));
-
-	/*
-	 * Leave device in reset for a while after powering on the
-	 * slot to give it a chance to initialize.
-	 */
-	mdelay(250);
-
-	out_be16(pcie_reg_fpga_base + FPGA_REG1C,
-		 reset_off | in_be16(pcie_reg_fpga_base + FPGA_REG1C));
-
-	iounmap(pcie_reg_fpga_base);
-}
-
-static void __init
-yucca_setup_hoses(void)
-{
-	struct pci_controller *hose;
-	char name[20];
-	int i;
-
-	if (0 && ppc440spe_init_pcie()) {
-		printk(KERN_WARNING "PPC440SPe PCI Express initialization failed\n");
-		return;
-	}
-
-	for (i = 0; i <= 2; ++i) {
-		if (!yucca_pcie_card_present(i))
-			continue;
-
-		printk(KERN_INFO "PCIE%d: card present\n", i);
-		yucca_setup_pcie_fpga_rootpoint(i);
-		if (ppc440spe_init_pcie_rootport(i)) {
-			printk(KERN_WARNING "PCIE%d: initialization failed\n", i);
-			continue;
-		}
-
-		hose = pcibios_alloc_controller();
-		if (!hose)
-			return;
-
-		sprintf(name, "PCIE%d host bridge", i);
-		pci_init_resource(&hose->io_resource,
-				  YUCCA_PCIX_LOWER_IO,
-				  YUCCA_PCIX_UPPER_IO,
-				  IORESOURCE_IO,
-				  name);
-
-		hose->mem_space.start = YUCCA_PCIE_LOWER_MEM +
-			i * YUCCA_PCIE_MEM_SIZE;
-		hose->mem_space.end   = hose->mem_space.start +
-			YUCCA_PCIE_MEM_SIZE - 1;
-
-		pci_init_resource(&hose->mem_resources[0],
-				  hose->mem_space.start,
-				  hose->mem_space.end,
-				  IORESOURCE_MEM,
-				  name);
-
-		hose->first_busno = 0;
-		hose->last_busno  = 15;
-		hose_type[hose->index] = HOSE_PCIE0 + i;
-
-		ppc440spe_setup_pcie(hose, i);
-		hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-	}
-
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = yucca_map_irq;
-}
-
-TODC_ALLOC();
-
-static void __init
-yucca_early_serial_map(void)
-{
-	struct uart_port port;
-
-	/* Setup ioremapped serial port access */
-	memset(&port, 0, sizeof(port));
-	port.membase = ioremap64(PPC440SPE_UART0_ADDR, 8);
-	port.irq = UART0_INT;
-	port.uartclk = clocks.uart0;
-	port.regshift = 0;
-	port.iotype = UPIO_MEM;
-	port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
-	port.line = 0;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 0 failed\n");
-	}
-
-	port.membase = ioremap64(PPC440SPE_UART1_ADDR, 8);
-	port.irq = UART1_INT;
-	port.uartclk = clocks.uart1;
-	port.line = 1;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 1 failed\n");
-	}
-
-	port.membase = ioremap64(PPC440SPE_UART2_ADDR, 8);
-	port.irq = UART2_INT;
-	port.uartclk = BASE_BAUD;
-	port.line = 2;
-
-	if (early_serial_setup(&port) != 0) {
-		printk("Early serial init of port 2 failed\n");
-	}
-}
-
-static void __init
-yucca_setup_arch(void)
-{
-	yucca_set_emacdata();
-
-#if !defined(CONFIG_BDI_SWITCH)
-	/*
-	 * The Abatron BDI JTAG debugger does not tolerate others
-	 * mucking with the debug registers.
-	 */
-	mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
-#endif
-
-	/*
-	 * Determine various clocks.
-	 * To be completely correct we should get SysClk
-	 * from FPGA, because it can be changed by on-board switches
-	 * --ebs
-	 */
-	/* 440GX and 440SPe clocking is the same - rd */
-	ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
-	ocp_sys_info.opb_bus_freq = clocks.opb;
-
-	/* init to some ~sane value until calibrate_delay() runs */
-	loops_per_jiffy = 50000000/HZ;
-
-	/* Setup PCIXn host bridges */
-	yucca_setup_hoses();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_HDA1;
-#endif
-
-	yucca_early_serial_map();
-
-	/* Identify the system */
-	printk("Yucca port (Roland Dreier <rolandd@cisco.com>)\n");
-}
-
-void __init platform_init(unsigned long r3, unsigned long r4,
-		unsigned long r5, unsigned long r6, unsigned long r7)
-{
-	ibm44x_platform_init(r3, r4, r5, r6, r7);
-
-	ppc_md.setup_arch = yucca_setup_arch;
-	ppc_md.show_cpuinfo = yucca_show_cpuinfo;
-	ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
-	ppc_md.get_irq = NULL;		/* Set in ppc4xx_pic_init() */
-
-	ppc_md.calibrate_decr = yucca_calibrate_decr;
-#ifdef CONFIG_KGDB
-	ppc_md.early_serial_map = yucca_early_serial_map;
-#endif
-}
diff --git a/arch/ppc/platforms/4xx/yucca.h b/arch/ppc/platforms/4xx/yucca.h
deleted file mode 100644
index bc9684e66a8..00000000000
--- a/arch/ppc/platforms/4xx/yucca.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Yucca board definitions
- *
- * Roland Dreier <rolandd@cisco.com> (based on luan.h by Matt Porter)
- *
- * Copyright 2004-2005 MontaVista Software Inc.
- * Copyright (c) 2005 Cisco Systems.  All rights reserved.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_YUCCA_H__
-#define __ASM_YUCCA_H__
-
-#include <platforms/4xx/ppc440spe.h>
-
-/* F/W TLB mapping used in bootloader glue to reset EMAC */
-#define PPC44x_EMAC0_MR0	0xa0000800
-
-/* Location of MAC addresses in PIBS image */
-#define PIBS_FLASH_BASE		0xffe00000
-#define PIBS_MAC_BASE		(PIBS_FLASH_BASE+0x1b0400)
-
-/* External timer clock frequency */
-#define YUCCA_TMR_CLK		25000000
-
-/*
- * FPGA registers
- */
-#define YUCCA_FPGA_REG_BASE			0x00000004e2000000ULL
-#define YUCCA_FPGA_REG_SIZE			0x24
-
-#define FPGA_REG1A				0x1a
-
-#define FPGA_REG1A_PE0_GLED			0x8000
-#define FPGA_REG1A_PE1_GLED			0x4000
-#define FPGA_REG1A_PE2_GLED			0x2000
-#define FPGA_REG1A_PE0_YLED			0x1000
-#define FPGA_REG1A_PE1_YLED			0x0800
-#define FPGA_REG1A_PE2_YLED			0x0400
-#define FPGA_REG1A_PE0_PWRON			0x0200
-#define FPGA_REG1A_PE1_PWRON			0x0100
-#define FPGA_REG1A_PE2_PWRON			0x0080
-#define FPGA_REG1A_PE0_REFCLK_ENABLE		0x0040
-#define FPGA_REG1A_PE1_REFCLK_ENABLE		0x0020
-#define FPGA_REG1A_PE2_REFCLK_ENABLE		0x0010
-#define FPGA_REG1A_PE_SPREAD0			0x0008
-#define FPGA_REG1A_PE_SPREAD1			0x0004
-#define FPGA_REG1A_PE_SELSOURCE_0		0x0002
-#define FPGA_REG1A_PE_SELSOURCE_1		0x0001
-
-#define FPGA_REG1C				0x1c
-
-#define FPGA_REG1C_PE0_ROOTPOINT		0x8000
-#define FPGA_REG1C_PE1_ENDPOINT			0x4000
-#define FPGA_REG1C_PE2_ENDPOINT			0x2000
-#define FPGA_REG1C_PE0_PRSNT			0x1000
-#define FPGA_REG1C_PE1_PRSNT			0x0800
-#define FPGA_REG1C_PE2_PRSNT			0x0400
-#define FPGA_REG1C_PE0_WAKE			0x0080
-#define FPGA_REG1C_PE1_WAKE			0x0040
-#define FPGA_REG1C_PE2_WAKE			0x0020
-#define FPGA_REG1C_PE0_PERST			0x0010
-#define FPGA_REG1C_PE1_PERST			0x0008
-#define FPGA_REG1C_PE2_PERST			0x0004
-
-/*
- * Serial port defines
- */
-#define RS_TABLE_SIZE	3
-
-/* PIBS defined UART mappings, used before early_serial_setup */
-#define UART0_IO_BASE	0xa0000200
-#define UART1_IO_BASE	0xa0000300
-#define UART2_IO_BASE	0xa0000600
-
-#define BASE_BAUD	11059200
-#define STD_UART_OP(num)					\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
-		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
-		iomem_base: (void*)UART##num##_IO_BASE,		\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)		\
-	STD_UART_OP(2)
-
-/* PCI support */
-#define YUCCA_PCIX_LOWER_IO	0x00000000
-#define YUCCA_PCIX_UPPER_IO	0x0000ffff
-#define YUCCA_PCIX_LOWER_MEM	0x80000000
-#define YUCCA_PCIX_UPPER_MEM	0x8fffffff
-#define YUCCA_PCIE_LOWER_MEM	0x90000000
-#define YUCCA_PCIE_MEM_SIZE	0x10000000
-
-#define YUCCA_PCIX_MEM_SIZE	0x10000000
-#define YUCCA_PCIX_MEM_OFFSET	0x00000000
-#define YUCCA_PCIE_MEM_SIZE	0x10000000
-#define YUCCA_PCIE_MEM_OFFSET	0x00000000
-
-#endif				/* __ASM_YUCCA_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/Makefile b/arch/ppc/platforms/Makefile
deleted file mode 100644
index 6260231987c..00000000000
--- a/arch/ppc/platforms/Makefile
+++ /dev/null
@@ -1,25 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-$(CONFIG_PPC_PREP)		+= prep_pci.o prep_setup.o
-obj-$(CONFIG_PREP_RESIDUAL)	+= residual.o
-obj-$(CONFIG_TQM8260)		+= tqm8260_setup.o
-obj-$(CONFIG_CPCI690)		+= cpci690.o
-obj-$(CONFIG_EV64260)		+= ev64260.o
-obj-$(CONFIG_CHESTNUT)		+= chestnut.o
-obj-$(CONFIG_LOPEC)		+= lopec.o
-obj-$(CONFIG_KATANA)		+= katana.o
-obj-$(CONFIG_HDPU)		+= hdpu.o
-obj-$(CONFIG_MVME5100)		+= mvme5100.o
-obj-$(CONFIG_PAL4)		+= pal4_setup.o pal4_pci.o
-obj-$(CONFIG_POWERPMC250)	+= powerpmc250.o
-obj-$(CONFIG_PPLUS)		+= pplus.o
-obj-$(CONFIG_PRPMC750)		+= prpmc750.o
-obj-$(CONFIG_PRPMC800)		+= prpmc800.o
-obj-$(CONFIG_RADSTONE_PPC7D)	+= radstone_ppc7d.o
-obj-$(CONFIG_SANDPOINT)		+= sandpoint.o
-obj-$(CONFIG_SBC82xx)		+= sbc82xx.o
-obj-$(CONFIG_SPRUCE)		+= spruce.o
-obj-$(CONFIG_LITE5200)		+= lite5200.o
-obj-$(CONFIG_EV64360)		+= ev64360.o
diff --git a/arch/ppc/platforms/bseip.h b/arch/ppc/platforms/bseip.h
deleted file mode 100644
index 691f4a52b0a..00000000000
--- a/arch/ppc/platforms/bseip.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * A collection of structures, addresses, and values associated with
- * the Bright Star Engineering ip-Engine board.  Copied from the MBX stuff.
- *
- * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
- */
-#ifndef __MACH_BSEIP_DEFS
-#define __MACH_BSEIP_DEFS
-
-#ifndef __ASSEMBLY__
-/* A Board Information structure that is given to a program when
- * prom starts it up.
- */
-typedef struct bd_info {
-	unsigned int	bi_memstart;	/* Memory start address */
-	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
-	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
-	unsigned int	bi_busfreq;	/* Bus Freq, in Hz */
-	unsigned char	bi_enetaddr[6];
-	unsigned int	bi_baudrate;
-} bd_t;
-
-extern bd_t m8xx_board_info;
-
-/* Memory map is configured by the PROM startup.
- * All we need to get started is the IMMR.
- */
-#define IMAP_ADDR		((uint)0xff000000)
-#define IMAP_SIZE		((uint)(64 * 1024))
-#define PCMCIA_MEM_ADDR		((uint)0x04000000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
-#endif	/* !__ASSEMBLY__ */
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif
diff --git a/arch/ppc/platforms/ccm.h b/arch/ppc/platforms/ccm.h
deleted file mode 100644
index 69000b1c7a4..00000000000
--- a/arch/ppc/platforms/ccm.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Siemens Card Controller Module specific definitions
- *
- * Copyright (C) 2001-2002 Wolfgang Denk (wd@denx.de)
- */
-
-#ifndef __MACH_CCM_H
-#define __MACH_CCM_H
-
-
-#include <asm/ppcboot.h>
-
-#define	CCM_IMMR_BASE    0xF0000000	/* phys. addr of IMMR			*/
-#define	CCM_IMAP_SIZE   (64 * 1024)	/* size of mapped area			*/
-
-#define	IMAP_ADDR     CCM_IMMR_BASE	/* physical base address of IMMR area	*/
-#define IMAP_SIZE     CCM_IMAP_SIZE	/* mapped size of IMMR area		*/
-
-#define	FEC_INTERRUPT	13		/* = SIU_LEVEL6				*/
-#define	DEC_INTERRUPT	11		/* = SIU_LEVEL5				*/
-#define	CPM_INTERRUPT	 9		/* = SIU_LEVEL4				*/
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif	/* __MACH_CCM_H */
diff --git a/arch/ppc/platforms/chestnut.c b/arch/ppc/platforms/chestnut.c
deleted file mode 100644
index 27c140f218e..00000000000
--- a/arch/ppc/platforms/chestnut.c
+++ /dev/null
@@ -1,574 +0,0 @@
-/*
- * Board setup routines for IBM Chestnut
- *
- * Author: <source@mvista.com>
- *
- * <2004> (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/blkdev.h>
-#include <linux/console.h>
-#include <linux/root_dev.h>
-#include <linux/initrd.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/mtd/physmap.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/hw_irq.h>
-#include <asm/machdep.h>
-#include <asm/kgdb.h>
-#include <asm/bootinfo.h>
-#include <asm/mv64x60.h>
-#include <platforms/chestnut.h>
-
-static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
-static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
-
-static mv64x60_handle_t	bh;
-
-extern void gen550_progress(char *, unsigned short);
-extern void gen550_init(int, struct uart_port *);
-extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
-
-#define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
-				BIT(MV64x60_CPU2DEV_1_WIN) | \
-				BIT(MV64x60_CPU2DEV_2_WIN) | \
-				BIT(MV64x60_CPU2DEV_3_WIN) | \
-				BIT(MV64x60_CPU2BOOT_WIN))
-/**************************************************************************
- * FUNCTION: chestnut_calibrate_decr
- *
- * DESCRIPTION: initialize decrementer interrupt frequency (used as system
- *              timer)
- *
- ****/
-static void __init
-chestnut_calibrate_decr(void)
-{
-	ulong freq;
-
-	freq = CHESTNUT_BUS_SPEED / 4;
-
-	printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
-		freq/1000000, freq%1000000);
-
-	tb_ticks_per_jiffy = freq / HZ;
-	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-}
-
-static int
-chestnut_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: IBM\n");
-	seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
-
-	return 0;
-}
-
-/**************************************************************************
- * FUNCTION: chestnut_find_end_of_memory
- *
- * DESCRIPTION: ppc_md memory size callback
- *
- ****/
-unsigned long __init
-chestnut_find_end_of_memory(void)
-{
-   	static int  mem_size = 0;
-
-   	if (mem_size == 0) {
-      		mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
-				MV64x60_TYPE_MV64460);
-   	}
-   	return mem_size;
-}
-
-#if defined(CONFIG_SERIAL_8250)
-static void __init
-chestnut_early_serial_map(void)
-{
-	struct uart_port port;
-
-	/* Setup serial port access */
-	memset(&port, 0, sizeof(port));
-	port.uartclk = BASE_BAUD * 16;
-	port.irq = UART0_INT;
-	port.flags = STD_COM_FLAGS | UPF_IOREMAP;
-	port.iotype = UPIO_MEM;
-	port.mapbase = CHESTNUT_UART0_IO_BASE;
-	port.regshift = 0;
-
-	if (early_serial_setup(&port) != 0)
-		printk("Early serial init of port 0 failed\n");
-
-	/* Assume early_serial_setup() doesn't modify serial_req */
-	port.line = 1;
-	port.irq = UART1_INT;
-	port.mapbase = CHESTNUT_UART1_IO_BASE;
-
-	if (early_serial_setup(&port) != 0)
-		printk("Early serial init of port 1 failed\n");
-}
-#endif
-
-/**************************************************************************
- * FUNCTION: chestnut_map_irq
- *
- * DESCRIPTION: 0 return since PCI IRQs not needed
- *
- ****/
-static int __init
-chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] = {
-		{CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
-		 CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
-		{CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
-		 CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
-		{CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
-		 CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
-		{CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
-		 CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
-	};
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-
-/**************************************************************************
- * FUNCTION: chestnut_setup_bridge
- *
- * DESCRIPTION: initalize board-specific settings on the MV64360
- *
- ****/
-static void __init
-chestnut_setup_bridge(void)
-{
-	struct mv64x60_setup_info	si;
-	int i;
-
-   	if ( ppc_md.progress )
-		ppc_md.progress("chestnut_setup_bridge: enter", 0);
-
-	memset(&si, 0, sizeof(si));
-
-	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
-
-	/* setup only PCI bus 0 (bus 1 not used) */
-	si.pci_0.enable_bus = 1;
-	si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
-	si.pci_0.pci_io.pci_base_hi = 0;
-	si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
-	si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
-	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
-	si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
-	si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
-	si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
-	si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
-	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
-	si.pci_0.pci_cmd_bits = 0;
-	si.pci_0.latency_timer = 0x80;
-
-	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
-
-		si.pci_1.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-#else
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
-
-		si.pci_1.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
-#endif
-	}
-
-   	/* Lookup host bridge - on CPU 0 - no SMP support */
-   	if (mv64x60_init(&bh, &si)) {
-        	printk("\n\nPCI Bridge initialization failed!\n");
-   	}
-
-	pci_dram_offset = 0;
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = chestnut_map_irq;
-	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
-
-	mv64x60_set_bus(&bh, 0, 0);
-	bh.hose_a->first_busno = 0;
-	bh.hose_a->last_busno = 0xff;
-	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
-}
-
-void __init
-chestnut_setup_peripherals(void)
-{
-   	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
-			CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
-			CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
-			CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
-	cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
-			CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
-			CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
-
-   	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
-			CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-
-#ifdef CONFIG_NOT_COHERENT_CACHE
-   	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
-#else
-   	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
-#endif
-	sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
-   	memset(sram_base, 0, MV64360_SRAM_SIZE);
-
-	/*
-	 * Configure MPP pins for PCI DMA
-	 *
-	 * PCI Slot	GNT pin		REQ pin
-	 *	0	MPP16		MPP17
-	 *	1	MPP18		MPP19
-	 *	2	MPP20		MPP21
-	 *	3	MPP22		MPP23
-	 */
-	mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
-			(0x1 << 0)  |	/* MPPSel16 PCI0_GNT[0] */
-			(0x1 << 4)  |	/* MPPSel17 PCI0_REQ[0] */
-			(0x1 << 8)  |	/* MPPSel18 PCI0_GNT[1] */
-			(0x1 << 12) |	/* MPPSel19 PCI0_REQ[1] */
-			(0x1 << 16) |	/* MPPSel20 PCI0_GNT[2] */
-			(0x1 << 20) |	/* MPPSel21 PCI0_REQ[2] */
-			(0x1 << 24) |	/* MPPSel22 PCI0_GNT[3] */
-			(0x1 << 28));	/* MPPSel23 PCI0_REQ[3] */
-	/*
-	 * Set unused MPP pins for output, as per schematic note
-	 *
-	 * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
-	 *		MPP09, MPP10, MPP13, MPP14, MPP15
-	 */
-	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
-			(0xf << 4)  |	/* MPPSel01 GPIO[1] */
-			(0xf << 8)  |	/* MPPSel02 GPIO[2] */
-			(0xf << 16) |	/* MPPSel04 GPIO[4] */
-			(0xf << 20) |	/* MPPSel05 GPIO[5] */
-			(0xf << 24));	/* MPPSel06 GPIO[6] */
-	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
-			(0xf << 4)  |	/* MPPSel09 GPIO[9] */
-			(0xf << 8)  |	/* MPPSel10 GPIO[10] */
-			(0xf << 20) |	/* MPPSel13 GPIO[13] */
-			(0xf << 24) |	/* MPPSel14 GPIO[14] */
-			(0xf << 28));	/* MPPSel15 GPIO[15] */
-	mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
-			BIT(1)  | BIT(2)  | BIT(4)  | BIT(5)  | BIT(6)  |
-			BIT(9)  | BIT(10) | BIT(13) | BIT(14) | BIT(15));
-
-   	/*
-    	 * Configure the following MPP pins to indicate a level
-    	 * triggered interrupt
-    	 *
-       	 * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
-       	 * MPP25 - UART A  (high)
-       	 * MPP26 - UART B  (high)
-	 * MPP28 - PCI Slot 3 (low)
-	 * MPP29 - PCI Slot 2 (low)
-	 * MPP30 - PCI Slot 1 (low)
-	 * MPP31 - PCI Slot 0 (low)
-    	 */
-        mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
-                        BIT(3) | BIT(2) | BIT(1) | BIT(0)	 | /* MPP 24 */
-                        BIT(7) | BIT(6) | BIT(5) | BIT(4)	 | /* MPP 25 */
-                        BIT(11) | BIT(10) | BIT(9) | BIT(8)	 | /* MPP 26 */
-			BIT(19) | BIT(18) | BIT(17) | BIT(16)	 | /* MPP 28 */
-			BIT(23) | BIT(22) | BIT(21) | BIT(20)	 | /* MPP 29 */
-			BIT(27) | BIT(26) | BIT(25) | BIT(24)	 | /* MPP 30 */
-			BIT(31) | BIT(30) | BIT(29) | BIT(28));    /* MPP 31 */
-
-   	/*
-	 * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
-	 * 31 (low) interrupt polarity input signal and level triggered
-    	 */
-   	mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
-   	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
-			BIT(28) | BIT(29) | BIT(30) | BIT(31));
-   	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
-			BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
-			BIT(31));
-
-   	/* Config GPP interrupt controller to respond to level trigger */
-   	mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
-
-   	/*
-    	 * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
-    	 */
-   	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
-			~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
-			  BIT(31)));
-   	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
-			BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
-			BIT(31));
-
-   	/*
-    	 * Dismiss and then enable interrupt on CPU #0 high cause register
-    	 * BIT27 summarizes GPP interrupts 24-31
-    	 */
-   	mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
-
-   	if (ppc_md.progress)
-		ppc_md.progress("chestnut_setup_bridge: exit", 0);
-}
-
-/**************************************************************************
- * FUNCTION: chestnut_setup_arch
- *
- * DESCRIPTION: ppc_md machine configuration callback
- *
- ****/
-static void __init
-chestnut_setup_arch(void)
-{
-	if (ppc_md.progress)
-      		ppc_md.progress("chestnut_setup_arch: enter", 0);
-
-	/* init to some ~sane value until calibrate_delay() runs */
-	loops_per_jiffy = 50000000 / HZ;
-
-   	/* if the time base value is greater than bus freq/4 (the TB and
-    	* decrementer tick rate) + signed integer rollover value, we
-    	* can spend a fair amount of time waiting for the rollover to
-    	* happen.  To get around this, initialize the time base register
-    	* to a "safe" value.
-    	*/
-   	set_tb(0, 0);
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-   	/*
-    	* Set up the L2CR register.
-    	*/
- 	_set_L2CR(_get_L2CR() | L2CR_L2E);
-
-	chestnut_setup_bridge();
-	chestnut_setup_peripherals();
-
-#ifdef CONFIG_DUMMY_CONSOLE
-	conswitchp = &dummy_con;
-#endif
-
-#if defined(CONFIG_SERIAL_8250)
-	chestnut_early_serial_map();
-#endif
-
-	/* Identify the system */
-	printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
-	printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
-		" (source@mvista.com)\n");
-
-	if (ppc_md.progress)
-      		ppc_md.progress("chestnut_setup_arch: exit", 0);
-}
-
-#ifdef CONFIG_MTD_PHYSMAP
-static struct mtd_partition ptbl;
-
-static int __init
-chestnut_setup_mtd(void)
-{
-	memset(&ptbl, 0, sizeof(ptbl));
-
-	ptbl.name = "User FS";
-	ptbl.size = CHESTNUT_32BIT_SIZE;
-
-	physmap_map.size = CHESTNUT_32BIT_SIZE;
-	physmap_set_partitions(&ptbl, 1);
-	return 0;
-}
-
-arch_initcall(chestnut_setup_mtd);
-#endif
-
-/**************************************************************************
- * FUNCTION: chestnut_restart
- *
- * DESCRIPTION: ppc_md machine reset callback
- *              reset the board via the CPLD command register
- *
- ****/
-static void
-chestnut_restart(char *cmd)
-{
-	volatile ulong i = 10000000;
-
-	local_irq_disable();
-
-        /*
-         * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
-         *
-         * MPP24 - board reset
-         */
-   	writeb(0x1, cpld_base + 3);
-
-	/* GPP pin tied to MPP earlier */
-        mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
-
-   	while (i-- > 0);
-   	panic("restart failed\n");
-}
-
-static void
-chestnut_halt(void)
-{
-	local_irq_disable();
-	for (;;);
-	/* NOTREACHED */
-}
-
-static void
-chestnut_power_off(void)
-{
-	chestnut_halt();
-	/* NOTREACHED */
-}
-
-/**************************************************************************
- * FUNCTION: chestnut_map_io
- *
- * DESCRIPTION: configure fixed memory-mapped IO
- *
- ****/
-static void __init
-chestnut_map_io(void)
-{
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-	io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
-		_PAGE_IO);
-#endif
-}
-
-/**************************************************************************
- * FUNCTION: chestnut_set_bat
- *
- * DESCRIPTION: configures a (temporary) bat mapping for early access to
- *              device I/O
- *
- ****/
-static __inline__ void
-chestnut_set_bat(void)
-{
-        mb();
-        mtspr(SPRN_DBAT3U, 0xf0001ffe);
-        mtspr(SPRN_DBAT3L, 0xf000002a);
-        mb();
-}
-
-/**************************************************************************
- * FUNCTION: platform_init
- *
- * DESCRIPTION: main entry point for configuring board-specific machine
- *              callbacks
- *
- ****/
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-        /* Copy the kernel command line arguments to a safe place. */
-
-        if (r6) {
-                *(char *) (r7 + KERNELBASE) = 0;
-                strcpy(cmd_line, (char *) (r6 + KERNELBASE));
-        }
-
-	isa_mem_base = 0;
-
-	ppc_md.setup_arch = chestnut_setup_arch;
-	ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
-	ppc_md.init_IRQ = mv64360_init_irq;
-	ppc_md.get_irq = mv64360_get_irq;
-	ppc_md.init = NULL;
-
-	ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
-	ppc_md.setup_io_mappings  = chestnut_map_io;
-
-	ppc_md.restart = chestnut_restart;
-   	ppc_md.power_off = chestnut_power_off;
-   	ppc_md.halt = chestnut_halt;
-
-	ppc_md.time_init = NULL;
-	ppc_md.set_rtc_time = NULL;
-	ppc_md.get_rtc_time = NULL;
-	ppc_md.calibrate_decr = chestnut_calibrate_decr;
-
-	ppc_md.nvram_read_val = NULL;
-	ppc_md.nvram_write_val = NULL;
-
-	ppc_md.heartbeat = NULL;
-
-	bh.p_base = CONFIG_MV64X60_NEW_BASE;
-
-	chestnut_set_bat();
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG)
-	ppc_md.progress = gen550_progress;
-#endif
-#if defined(CONFIG_KGDB)
-	ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
-#endif
-
-	if (ppc_md.progress)
-                ppc_md.progress("chestnut_init(): exit", 0);
-}
diff --git a/arch/ppc/platforms/chestnut.h b/arch/ppc/platforms/chestnut.h
deleted file mode 100644
index e00fd9f8bbd..00000000000
--- a/arch/ppc/platforms/chestnut.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Definitions for IBM 750FXGX Eval (Chestnut)
- *
- * Author: <source@mvista.com>
- *
- * Based on Artesyn Katana code done by Tim Montgomery <timm@artesyncp.com>
- * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
- * Based on code done by Mark A. Greer <mgreer@mvista.com>
- *
- * <2004> (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * This is the CPU physical memory map (windows must be at least 1MB and start
- * on a boundary that is a multiple of the window size):
- *
- * Seems on the IBM 750FXGX Eval board, the MV64460 Registers can be in
- * only 2 places per switch U17 0x14000000 or 0xf1000000 easily - chose to
- * implement at 0xf1000000 only at this time
- *
- *    0xfff00000-0xffffffff      - 8 Flash
- *    0xffe00000-0xffefffff      - BOOT SRAM
- *    0xffd00000-0xffd00004      - CPLD
- *    0xffc00000-0xffc0000f      - UART
- *    0xffb00000-0xffb07fff      - FRAM
- *    0xff840000-0xffafffff      - *** HOLE ***
- *    0xff800000-0xff83ffff      - MV64460 Integrated SRAM
- *    0xfe000000-0xff8fffff      - *** HOLE ***
- *    0xfc000000-0xfdffffff      - 32bit Flash
- *    0xf1010000-0xfbffffff      - *** HOLE ***
- *    0xf1000000-0xf100ffff      - MV64460 Registers
- */
-
-#ifndef __PPC_PLATFORMS_CHESTNUT_H__
-#define __PPC_PLATFORMS_CHESTNUT_H__
-
-#define CHESTNUT_BOOT_8BIT_BASE			0xfff00000
-#define CHESTNUT_BOOT_8BIT_SIZE_ACTUAL		(1024*1024)
-#define CHESTNUT_BOOT_SRAM_BASE			0xffe00000
-#define CHESTNUT_BOOT_SRAM_SIZE_ACTUAL		(1024*1024)
-#define CHESTNUT_CPLD_BASE			0xffd00000
-#define CHESTNUT_CPLD_SIZE_ACTUAL		5
-#define CHESTNUT_CPLD_REG3			(CHESTNUT_CPLD_BASE+3)
-#define CHESTNUT_UART_BASE			0xffc00000
-#define CHESTNUT_UART_SIZE_ACTUAL		16
-#define CHESTNUT_FRAM_BASE			0xffb00000
-#define CHESTNUT_FRAM_SIZE_ACTUAL		(32*1024)
-#define CHESTNUT_INTERNAL_SRAM_BASE		0xff800000
-#define CHESTNUT_32BIT_BASE			0xfc000000
-#define CHESTNUT_32BIT_SIZE			(32*1024*1024)
-
-#define CHESTNUT_BOOT_8BIT_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
-					CHESTNUT_BOOT_8BIT_SIZE_ACTUAL)
-#define CHESTNUT_BOOT_SRAM_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
-					CHESTNUT_BOOT_SRAM_SIZE_ACTUAL)
-#define CHESTNUT_CPLD_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
-					CHESTNUT_CPLD_SIZE_ACTUAL)
-#define CHESTNUT_UART_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
-					CHESTNUT_UART_SIZE_ACTUAL)
-#define CHESTNUT_FRAM_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
-					CHESTNUT_FRAM_SIZE_ACTUAL)
-
-#define CHESTNUT_BUS_SPEED		200000000
-#define CHESTNUT_PIBS_DATABASE		0xf0000 /* from PIBS src code */
-
-#define	KATANA_ETH0_PHY_ADDR			12
-#define	KATANA_ETH1_PHY_ADDR			11
-#define	KATANA_ETH2_PHY_ADDR			4
-
-#define CHESTNUT_ETH_TX_QUEUE_SIZE		800
-#define CHESTNUT_ETH_RX_QUEUE_SIZE		400
-
-/*
- * PCI windows
- */
-
-#define CHESTNUT_PCI0_MEM_PROC_ADDR	0x80000000
-#define CHESTNUT_PCI0_MEM_PCI_HI_ADDR	0x00000000
-#define CHESTNUT_PCI0_MEM_PCI_LO_ADDR	0x80000000
-#define CHESTNUT_PCI0_MEM_SIZE		0x10000000
-#define CHESTNUT_PCI0_IO_PROC_ADDR	0xa0000000
-#define CHESTNUT_PCI0_IO_PCI_ADDR	0x00000000
-#define CHESTNUT_PCI0_IO_SIZE		0x01000000
-
-/*
- * Board-specific IRQ info
- */
-#define CHESTNUT_PCI_SLOT0_IRQ	(64 + 31)
-#define CHESTNUT_PCI_SLOT1_IRQ	(64 + 30)
-#define CHESTNUT_PCI_SLOT2_IRQ	(64 + 29)
-#define CHESTNUT_PCI_SLOT3_IRQ	(64 + 28)
-
-/* serial port definitions */
-#define CHESTNUT_UART0_IO_BASE  (CHESTNUT_UART_BASE + 8)
-#define CHESTNUT_UART1_IO_BASE  CHESTNUT_UART_BASE
-
-#define UART0_INT           	(64 + 25)
-#define UART1_INT        	(64 + 26)
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define RS_TABLE_SIZE  64
-#else
-#define RS_TABLE_SIZE  2
-#endif
-
-/* Rate for the 3.6864 Mhz clock for the onboard serial chip */
-#define BASE_BAUD 		(3686400 / 16)
-
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
-#endif
-
-#define STD_UART_OP(num)						\
-        { 0, BASE_BAUD, 0, UART##num##_INT, STD_COM_FLAGS,		\
-                iomem_base: (u8 *)CHESTNUT_UART##num##_IO_BASE,	\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS        \
-        STD_UART_OP(0)          \
-        STD_UART_OP(1)
-
-#endif /* __PPC_PLATFORMS_CHESTNUT_H__ */
diff --git a/arch/ppc/platforms/cpci690.c b/arch/ppc/platforms/cpci690.c
deleted file mode 100644
index 07f672d5876..00000000000
--- a/arch/ppc/platforms/cpci690.c
+++ /dev/null
@@ -1,453 +0,0 @@
-/*
- * Board setup routines for the Force CPCI690 board.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2003 (c) MontaVista Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This programr
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/delay.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/fs.h>
-#include <linux/seq_file.h>
-#include <linux/console.h>
-#include <linux/initrd.h>
-#include <linux/root_dev.h>
-#include <linux/mv643xx.h>
-#include <linux/platform_device.h>
-#include <asm/bootinfo.h>
-#include <asm/machdep.h>
-#include <asm/todc.h>
-#include <asm/time.h>
-#include <asm/mv64x60.h>
-#include <platforms/cpci690.h>
-
-#define BOARD_VENDOR	"Force"
-#define BOARD_MACHINE	"CPCI690"
-
-/* Set IDE controllers into Native mode? */
-#define SET_PCI_IDE_NATIVE
-
-static struct mv64x60_handle	bh;
-static void __iomem *cpci690_br_base;
-
-TODC_ALLOC();
-
-static int __init
-cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	struct pci_controller	*hose = pci_bus_to_hose(dev->bus->number);
-
-	if (hose->index == 0) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 * 	   A   B   C   D
-		 */
-		{
-			{ 90, 91, 88, 89 }, /* IDSEL 30/20 - Sentinel */
-		};
-
-		const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	} else {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 * 	   A   B   C   D
-		 */
-		{
-			{ 93, 94, 95, 92 }, /* IDSEL 28/18 - PMC slot 2 */
-			{  0,  0,  0,  0 }, /* IDSEL 29/19 - Not used */
-			{ 94, 95, 92, 93 }, /* IDSEL 30/20 - PMC slot 1 */
-		};
-
-		const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-}
-
-#define	GB	(1024UL * 1024UL * 1024UL)
-
-static u32
-cpci690_get_bus_freq(void)
-{
-	if (boot_mem_size >= (1*GB)) /* bus speed based on mem size */
-		return 100000000;
-	else
-		return 133333333;
-}
-
-static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
-	 0,  0,  2,  2,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,/* 0-15*/
-	16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40,  0 /*16-31*/
-};
-
-static int
-cpci690_get_cpu_freq(void)
-{
-	unsigned long	pll_cfg;
-
-	pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
-	return cpci690_get_bus_freq() * cpu_750xx[pll_cfg]/2;
-}
-
-static void __init
-cpci690_setup_bridge(void)
-{
-	struct mv64x60_setup_info	si;
-	int				i;
-
-	memset(&si, 0, sizeof(si));
-
-	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
-
-	si.pci_0.enable_bus = 1;
-	si.pci_0.pci_io.cpu_base = CPCI690_PCI0_IO_START_PROC_ADDR;
-	si.pci_0.pci_io.pci_base_hi = 0;
-	si.pci_0.pci_io.pci_base_lo = CPCI690_PCI0_IO_START_PCI_ADDR;
-	si.pci_0.pci_io.size = CPCI690_PCI0_IO_SIZE;
-	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_mem[0].cpu_base = CPCI690_PCI0_MEM_START_PROC_ADDR;
-	si.pci_0.pci_mem[0].pci_base_hi = CPCI690_PCI0_MEM_START_PCI_HI_ADDR;
-	si.pci_0.pci_mem[0].pci_base_lo = CPCI690_PCI0_MEM_START_PCI_LO_ADDR;
-	si.pci_0.pci_mem[0].size = CPCI690_PCI0_MEM_SIZE;
-	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_cmd_bits = 0;
-	si.pci_0.latency_timer = 0x80;
-
-	si.pci_1.enable_bus = 1;
-	si.pci_1.pci_io.cpu_base = CPCI690_PCI1_IO_START_PROC_ADDR;
-	si.pci_1.pci_io.pci_base_hi = 0;
-	si.pci_1.pci_io.pci_base_lo = CPCI690_PCI1_IO_START_PCI_ADDR;
-	si.pci_1.pci_io.size = CPCI690_PCI1_IO_SIZE;
-	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_mem[0].cpu_base = CPCI690_PCI1_MEM_START_PROC_ADDR;
-	si.pci_1.pci_mem[0].pci_base_hi = CPCI690_PCI1_MEM_START_PCI_HI_ADDR;
-	si.pci_1.pci_mem[0].pci_base_lo = CPCI690_PCI1_MEM_START_PCI_LO_ADDR;
-	si.pci_1.pci_mem[0].size = CPCI690_PCI1_MEM_SIZE;
-	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_cmd_bits = 0;
-	si.pci_1.latency_timer = 0x80;
-
-	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
-		si.cpu_prot_options[i] = 0;
-		si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
-		si.pci_0.acc_cntl_options[i] =
-			GT64260_PCI_ACC_CNTL_DREADEN |
-			GT64260_PCI_ACC_CNTL_RDPREFETCH |
-			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
-			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
-			GT64260_PCI_ACC_CNTL_SWAP_NONE |
-			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
-		si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
-		si.pci_1.acc_cntl_options[i] =
-			GT64260_PCI_ACC_CNTL_DREADEN |
-			GT64260_PCI_ACC_CNTL_RDPREFETCH |
-			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
-			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
-			GT64260_PCI_ACC_CNTL_SWAP_NONE |
-			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
-		si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
-	}
-
-        /* Lookup PCI host bridges */
-        if (mv64x60_init(&bh, &si))
-                printk(KERN_ERR "Bridge initialization failed.\n");
-
-	pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = cpci690_map_irq;
-	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
-
-	mv64x60_set_bus(&bh, 0, 0);
-	bh.hose_a->first_busno = 0;
-	bh.hose_a->last_busno = 0xff;
-	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
-
-	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
-	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
-	bh.hose_b->last_busno = 0xff;
-	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
-		bh.hose_b->first_busno);
-}
-
-static void __init
-cpci690_setup_peripherals(void)
-{
-	/* Set up windows to CPLD, RTC/TODC, IPMI. */
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
-		CPCI690_BR_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
-	cpci690_br_base = ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
-		CPCI690_TODC_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
-	TODC_INIT(TODC_TYPE_MK48T35, 0, 0,
-			ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE,
-		CPCI690_IPMI_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
-
-	mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
-	mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
-
-        mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
-
-	/*
-	 * Turn off timer/counters.  Not turning off watchdog timer because
-	 * can't read its reg on the 64260A so don't know if we'll be enabling
-	 * or disabling.
-	 */
-	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
-			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
-	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
-			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
-
-	/*
-	 * Set MPSC Multiplex RMII
-	 * NOTE: ethernet driver modifies bit 0 and 1
-	 */
-	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
-
-#define GPP_EXTERNAL_INTERRUPTS \
-		((1<<24) | (1<<25) | (1<<26) | (1<<27) | \
-		 (1<<28) | (1<<29) | (1<<30) | (1<<31))
-	/* PCI interrupts are inputs */
-	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
-	/* PCI interrupts are active low */
-	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
-
-	/* Clear any pending interrupts for these inputs and enable them. */
-	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
-	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
-
-	/* Route MPP interrupt inputs to GPP */
-	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);
-	mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);
-}
-
-static void __init
-cpci690_setup_arch(void)
-{
-	if (ppc_md.progress)
-		ppc_md.progress("cpci690_setup_arch: enter", 0);
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef   CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	if (ppc_md.progress)
-		ppc_md.progress("cpci690_setup_arch: Enabling L2 cache", 0);
-
-	/* Enable L2 and L3 caches (if 745x) */
-	_set_L2CR(_get_L2CR() | L2CR_L2E);
-	_set_L3CR(_get_L3CR() | L3CR_L3E);
-
-	if (ppc_md.progress)
-		ppc_md.progress("cpci690_setup_arch: Initializing bridge", 0);
-
-	cpci690_setup_bridge();		/* set up PCI bridge(s) */
-	cpci690_setup_peripherals();	/* set up chip selects/GPP/MPP etc */
-
-	if (ppc_md.progress)
-		ppc_md.progress("cpci690_setup_arch: bridge init complete", 0);
-
-	printk(KERN_INFO "%s %s port (C) 2003 MontaVista Software, Inc. "
-		"(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
-
-	if (ppc_md.progress)
-		ppc_md.progress("cpci690_setup_arch: exit", 0);
-}
-
-/* Platform device data fixup routines. */
-#if defined(CONFIG_SERIAL_MPSC)
-static void __init
-cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
-{
-	struct mpsc_pdata *pdata;
-
-	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
-
-	pdata->max_idle = 40;
-	pdata->default_baud = CPCI690_MPSC_BAUD;
-	pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
-	pdata->brg_clk_freq = cpci690_get_bus_freq();
-}
-
-static int
-cpci690_platform_notify(struct device *dev)
-{
-	static struct {
-		char	*bus_id;
-		void	((*rtn)(struct platform_device *pdev));
-	} dev_map[] = {
-		{ MPSC_CTLR_NAME ".0", cpci690_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME ".1", cpci690_fixup_mpsc_pdata },
-	};
-	struct platform_device	*pdev;
-	int	i;
-
-	if (dev && dev->bus_id)
-		for (i=0; i<ARRAY_SIZE(dev_map); i++)
-			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
-				BUS_ID_SIZE)) {
-
-				pdev = container_of(dev,
-					struct platform_device, dev);
-				dev_map[i].rtn(pdev);
-			}
-
-	return 0;
-}
-#endif
-
-static void
-cpci690_reset_board(void)
-{
-	u32	i = 10000;
-
-	local_irq_disable();
-	out_8((cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
-
-	while (i != 0) i++;
-	panic("restart failed\n");
-}
-
-static void
-cpci690_restart(char *cmd)
-{
-	cpci690_reset_board();
-}
-
-static void
-cpci690_halt(void)
-{
-	while (1);
-	/* NOTREACHED */
-}
-
-static void
-cpci690_power_off(void)
-{
-	cpci690_halt();
-	/* NOTREACHED */
-}
-
-static int
-cpci690_show_cpuinfo(struct seq_file *m)
-{
-	char	*s;
-
-	seq_printf(m, "cpu MHz\t\t: %d\n",
-		(cpci690_get_cpu_freq() + 500000) / 1000000);
-	seq_printf(m, "bus MHz\t\t: %d\n",
-		(cpci690_get_bus_freq() + 500000) / 1000000);
-	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
-	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
-	seq_printf(m, "FPGA Revision\t: %d\n",
-		in_8(cpci690_br_base + CPCI690_BR_MEM_CTLR) >> 5);
-
-	switch(bh.type) {
-	case MV64x60_TYPE_GT64260A:
-		s = "gt64260a";
-		break;
-	case MV64x60_TYPE_GT64260B:
-		s = "gt64260b";
-		break;
-	case MV64x60_TYPE_MV64360:
-		s = "mv64360";
-		break;
-	case MV64x60_TYPE_MV64460:
-		s = "mv64460";
-		break;
-	default:
-		s = "Unknown";
-	}
-	seq_printf(m, "bridge type\t: %s\n", s);
-	seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-	seq_printf(m, "coherency\t: %s\n", "off");
-#else
-	seq_printf(m, "coherency\t: %s\n", "on");
-#endif
-
-	return 0;
-}
-
-static void __init
-cpci690_calibrate_decr(void)
-{
-	ulong freq;
-
-	freq = cpci690_get_bus_freq() / 4;
-
-	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
-	       freq/1000000, freq%1000000);
-
-	tb_ticks_per_jiffy = freq / HZ;
-	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
-static void __init
-cpci690_map_io(void)
-{
-	io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
-		128 * 1024, _PAGE_IO);
-}
-#endif
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	/* take care of initrd if we have one */
-	if (r4) {
-		initrd_start = r4 + KERNELBASE;
-		initrd_end = r5 + KERNELBASE;
-	}
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-	isa_mem_base = 0;
-
-	ppc_md.setup_arch = cpci690_setup_arch;
-	ppc_md.show_cpuinfo = cpci690_show_cpuinfo;
-	ppc_md.init_IRQ = gt64260_init_irq;
-	ppc_md.get_irq = gt64260_get_irq;
-	ppc_md.restart = cpci690_restart;
-	ppc_md.power_off = cpci690_power_off;
-	ppc_md.halt = cpci690_halt;
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-	ppc_md.calibrate_decr = cpci690_calibrate_decr;
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC)
-	ppc_md.setup_io_mappings = cpci690_map_io;
-#ifdef CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.progress = mv64x60_mpsc_progress;
-	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
-#endif	/* CONFIG_SERIAL_TEXT_DEBUG */
-#endif	/* defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB_MPSC) */
-
-#if defined(CONFIG_SERIAL_MPSC)
-	platform_notify = cpci690_platform_notify;
-#endif
-}
diff --git a/arch/ppc/platforms/cpci690.h b/arch/ppc/platforms/cpci690.h
deleted file mode 100644
index 0fa5a4c31b6..00000000000
--- a/arch/ppc/platforms/cpci690.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Definitions for Force CPCI690
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2003 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * The GT64260 has 2 PCI buses each with 1 window from the CPU bus to
- * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
- */
-
-#ifndef __PPC_PLATFORMS_CPCI690_H
-#define __PPC_PLATFORMS_CPCI690_H
-
-/*
- * Define bd_t to pass in the MAC addresses used by the GT64260's enet ctlrs.
- */
-#define	CPCI690_BI_MAGIC		0xFE8765DC
-
-typedef struct board_info {
-	u32	bi_magic;
-	u8	bi_enetaddr[3][6];
-} bd_t;
-
-/* PCI bus Resource setup */
-#define CPCI690_PCI0_MEM_START_PROC_ADDR	0x80000000
-#define CPCI690_PCI0_MEM_START_PCI_HI_ADDR	0x00000000
-#define CPCI690_PCI0_MEM_START_PCI_LO_ADDR	0x80000000
-#define CPCI690_PCI0_MEM_SIZE			0x10000000
-#define CPCI690_PCI0_IO_START_PROC_ADDR		0xa0000000
-#define CPCI690_PCI0_IO_START_PCI_ADDR		0x00000000
-#define CPCI690_PCI0_IO_SIZE			0x01000000
-
-#define CPCI690_PCI1_MEM_START_PROC_ADDR	0x90000000
-#define CPCI690_PCI1_MEM_START_PCI_HI_ADDR	0x00000000
-#define CPCI690_PCI1_MEM_START_PCI_LO_ADDR	0x90000000
-#define CPCI690_PCI1_MEM_SIZE			0x10000000
-#define CPCI690_PCI1_IO_START_PROC_ADDR		0xa1000000
-#define CPCI690_PCI1_IO_START_PCI_ADDR		0x01000000
-#define CPCI690_PCI1_IO_SIZE			0x01000000
-
-/* Board Registers */
-#define	CPCI690_BR_BASE				0xf0000000
-#define	CPCI690_BR_SIZE_ACTUAL			0x8
-#define	CPCI690_BR_SIZE			max(GT64260_WINDOW_SIZE_MIN,	\
-						CPCI690_BR_SIZE_ACTUAL)
-#define	CPCI690_BR_LED_CNTL			0x00
-#define	CPCI690_BR_SW_RESET			0x01
-#define	CPCI690_BR_MISC_STATUS			0x02
-#define	CPCI690_BR_SWITCH_STATUS		0x03
-#define	CPCI690_BR_MEM_CTLR			0x04
-#define	CPCI690_BR_LAST_RESET_1			0x05
-#define	CPCI690_BR_LAST_RESET_2			0x06
-
-#define	CPCI690_TODC_BASE			0xf0100000
-#define	CPCI690_TODC_SIZE_ACTUAL		0x8000 /* Size or NVRAM + RTC */
-#define	CPCI690_TODC_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
-						CPCI690_TODC_SIZE_ACTUAL)
-#define	CPCI690_MAC_OFFSET			0x7c10 /* MAC in RTC NVRAM */
-
-#define	CPCI690_IPMI_BASE			0xf0200000
-#define	CPCI690_IPMI_SIZE_ACTUAL		0x10 /* 16 bytes of IPMI */
-#define	CPCI690_IPMI_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
-						CPCI690_IPMI_SIZE_ACTUAL)
-
-#define	CPCI690_MPSC_BAUD			9600
-#define	CPCI690_MPSC_CLK_SRC			8 /* TCLK */
-
-#endif /* __PPC_PLATFORMS_CPCI690_H */
diff --git a/arch/ppc/platforms/est8260.h b/arch/ppc/platforms/est8260.h
deleted file mode 100644
index adba68ecf57..00000000000
--- a/arch/ppc/platforms/est8260.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/* Board information for the EST8260, which should be generic for
- * all 8260 boards.  The IMMR is now given to us so the hard define
- * will soon be removed.  All of the clock values are computed from
- * the configuration SCMR and the Power-On-Reset word.
- */
-#ifndef __EST8260_PLATFORM
-#define __EST8260_PLATFORM
-
-#define CPM_MAP_ADDR		((uint)0xf0000000)
-
-#define BOOTROM_RESTART_ADDR	((uint)0xff000104)
-
-/* For our show_cpuinfo hooks. */
-#define CPUINFO_VENDOR		"EST Corporation"
-#define CPUINFO_MACHINE		"SBC8260 PowerPC"
-
-/* A Board Information structure that is given to a program when
- * prom starts it up.
- */
-typedef struct bd_info {
-	unsigned int	bi_memstart;	/* Memory start address */
-	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
-	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
-	unsigned int	bi_busfreq;	/* Bus Freq, in MHz */
-	unsigned int	bi_cpmfreq;	/* CPM Freq, in MHz */
-	unsigned int	bi_brgfreq;	/* BRG Freq, in MHz */
-	unsigned int	bi_vco;		/* VCO Out from PLL */
-	unsigned int	bi_baudrate;	/* Default console baud rate */
-	unsigned int	bi_immr;	/* IMMR when called from boot rom */
-	unsigned char	bi_enetaddr[6];
-} bd_t;
-
-extern bd_t m8xx_board_info;
-
-#endif 	/* __EST8260_PLATFORM */
diff --git a/arch/ppc/platforms/ev64260.c b/arch/ppc/platforms/ev64260.c
deleted file mode 100644
index f522b31c46d..00000000000
--- a/arch/ppc/platforms/ev64260.c
+++ /dev/null
@@ -1,649 +0,0 @@
-/*
- * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001-2003 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * The EV-64260-BP port is the result of hard work from many people from
- * many companies.  In particular, employees of Marvell/Galileo, Mission
- * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
- *
- * Note: I have not been able to get *all* PCI slots to work reliably
- *	at 66 MHz.  I recommend setting jumpers J15 & J16 to short pins 1&2
- *	so that 33 MHz is used. --MAG
- * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK.
- * 	At 100MHz, they are solid.
- */
-
-#include <linux/delay.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/fs.h>
-#include <linux/seq_file.h>
-#include <linux/console.h>
-#include <linux/initrd.h>
-#include <linux/root_dev.h>
-#include <linux/platform_device.h>
-#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#else
-#include <linux/mv643xx.h>
-#endif
-#include <asm/bootinfo.h>
-#include <asm/machdep.h>
-#include <asm/mv64x60.h>
-#include <asm/todc.h>
-#include <asm/time.h>
-
-#include <platforms/ev64260.h>
-
-#define BOARD_VENDOR	"Marvell/Galileo"
-#define BOARD_MACHINE	"EV-64260-BP"
-
-static struct mv64x60_handle	bh;
-
-#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
-extern void gen550_progress(char *, unsigned short);
-extern void gen550_init(int, struct uart_port *);
-#endif
-
-static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
-	18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
-};
-static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */
-	{ 1, 15, 14,  2,  4, 13,  5,  9,  6, 11,  8, 10, 16, 12,  7,  0 },
-	{ 0, 30,  0,  2,  0, 26,  0, 18,  0, 22, 20, 24, 28, 32,  0,  0 }
-};
-
-
-TODC_ALLOC();
-
-static int
-ev64260_get_bus_speed(void)
-{
-	return 100000000;
-}
-
-static int
-ev64260_get_cpu_speed(void)
-{
-	unsigned long	pvr, hid1, pll_ext;
-
-	pvr = PVR_VER(mfspr(SPRN_PVR));
-
-	if (pvr != PVR_VER(PVR_7450)) {
-		hid1 = mfspr(SPRN_HID1) >> 28;
-		return ev64260_get_bus_speed() * cpu_7xx[hid1]/2;
-	}
-	else {
-		hid1 = (mfspr(SPRN_HID1) & 0x0001e000) >> 13;
-		pll_ext = 0; /* No way to read; must get from schematic */
-		return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2;
-	}
-}
-
-unsigned long __init
-ev64260_find_end_of_memory(void)
-{
-	return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
-		MV64x60_TYPE_GT64260A);
-}
-
-/*
- * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
- * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first
- *	PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ).
- *	This is the most IRQs you can get from one bus with this board, though.
- */
-static int __init
-ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	struct pci_controller	*hose = pci_bus_to_hose(dev->bus->number);
-
-	if (hose->index == 0) {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 * 	   A   B   C   D
-		 */
-		{
-			{EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */
-			{EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */
-		};
-
-		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-	else {
-		static char pci_irq_table[][4] =
-		/*
-		 *	PCI IDSEL/INTPIN->INTLINE
-		 * 	   A   B   C   D
-		 */
-		{
-			{ EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */
-			{ EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */
-		};
-
-		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-}
-
-static void __init
-ev64260_setup_peripherals(void)
-{
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
-		EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
-		EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
-		EV64260_TODC_BASE, EV64260_TODC_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
-		EV64260_UART_BASE, EV64260_UART_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
-		EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
-
-	TODC_INIT(TODC_TYPE_DS1501, 0, 0,
-			ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8);
-
-	mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29)));
-	mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27));
-
-	if (ev64260_get_bus_speed() > 100000000)
-		mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23));
-
-	mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
-	mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
-
-        /*
-         * Enabling of PCI internal-vs-external arbitration
-         * is a platform- and errata-dependent decision.
-         */
-        if (bh.type == MV64x60_TYPE_GT64260A )  {
-                mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
-                mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
-        }
-
-        mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
-
-	/*
-	 * Turn off timer/counters.  Not turning off watchdog timer because
-	 * can't read its reg on the 64260A so don't know if we'll be enabling
-	 * or disabling.
-	 */
-	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
-			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
-	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
-			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
-
-	/*
-	 * Set MPSC Multiplex RMII
-	 * NOTE: ethernet driver modifies bit 0 and 1
-	 */
-	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
-
-	/*
-	 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
-	 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
-	 * register).  Need to route the MPP inputs to the GPP and set the
-	 * polarity correctly.
-	 *
-	 * In MPP Control 2 Register
-	 *   MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0
-	 *   MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0
-	 */
-	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) );
-
-	/*
-	 * In MPP Control 3 Register
-	 *   MPP 26 -> GPP 26 (RTC INT)		bits  8-11 -> 0
-	 *   MPP 27 -> GPP 27 (PCI 0 INTA)	bits 12-15 -> 0
-	 *   MPP 29 -> GPP 29 (PCI 1 INTA)	bits 20-23 -> 0
-	 */
-	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20));
-
-#define GPP_EXTERNAL_INTERRUPTS \
-		((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
-	/* DUART & PCI interrupts are inputs */
-	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
-	/* DUART & PCI interrupts are active low */
-	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
-
-	/* Clear any pending interrupts for these inputs and enable them. */
-	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
-	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
-
-	return;
-}
-
-static void __init
-ev64260_setup_bridge(void)
-{
-	struct mv64x60_setup_info	si;
-	int				i;
-
-	memset(&si, 0, sizeof(si));
-
-	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
-
-	si.pci_0.enable_bus = 1;
-	si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE;
-	si.pci_0.pci_io.pci_base_hi = 0;
-	si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE;
-	si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE;
-	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE;
-	si.pci_0.pci_mem[0].pci_base_hi = 0;
-	si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE;
-	si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE;
-	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_cmd_bits = 0;
-	si.pci_0.latency_timer = 0x8;
-
-	si.pci_1.enable_bus = 1;
-	si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE;
-	si.pci_1.pci_io.pci_base_hi = 0;
-	si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE;
-	si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE;
-	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE;
-	si.pci_1.pci_mem[0].pci_base_hi = 0;
-	si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE;
-	si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE;
-	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_cmd_bits = 0;
-	si.pci_1.latency_timer = 0x8;
-
-	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
-		si.cpu_prot_options[i] = 0;
-		si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
-		si.pci_0.acc_cntl_options[i] =
-			GT64260_PCI_ACC_CNTL_DREADEN |
-			GT64260_PCI_ACC_CNTL_RDPREFETCH |
-			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
-			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
-			GT64260_PCI_ACC_CNTL_SWAP_NONE |
-			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
-		si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
-		si.pci_1.acc_cntl_options[i] =
-			GT64260_PCI_ACC_CNTL_DREADEN |
-			GT64260_PCI_ACC_CNTL_RDPREFETCH |
-			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
-			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
-			GT64260_PCI_ACC_CNTL_SWAP_NONE |
-			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
-		si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
-	}
-
-        /* Lookup PCI host bridges */
-        if (mv64x60_init(&bh, &si))
-                printk(KERN_ERR "Bridge initialization failed.\n");
-
-	pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = ev64260_map_irq;
-	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
-
-	mv64x60_set_bus(&bh, 0, 0);
-	bh.hose_a->first_busno = 0;
-	bh.hose_a->last_busno = 0xff;
-	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
-
-	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
-	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
-	bh.hose_b->last_busno = 0xff;
-	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
-		bh.hose_b->first_busno);
-
-	return;
-}
-
-#if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE)
-static void __init
-ev64260_early_serial_map(void)
-{
-	struct uart_port	port;
-	static char		first_time = 1;
-
-	if (first_time) {
-		memset(&port, 0, sizeof(port));
-
-		port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE);
-		port.irq = EV64260_UART_0_IRQ;
-		port.uartclk = BASE_BAUD * 16;
-		port.regshift = 2;
-		port.iotype = UPIO_MEM;
-		port.flags = STD_COM_FLAGS;
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-		gen550_init(0, &port);
-#endif
-
-		if (early_serial_setup(&port) != 0)
-			printk(KERN_WARNING "Early serial init of port 0 "
-				"failed\n");
-
-		first_time = 0;
-	}
-
-	return;
-}
-#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
-static void __init
-ev64260_early_serial_map(void)
-{
-}
-#endif
-
-static void __init
-ev64260_setup_arch(void)
-{
-	if (ppc_md.progress)
-		ppc_md.progress("ev64260_setup_arch: enter", 0);
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef	CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	if (ppc_md.progress)
-		ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0);
-
-	/* Enable L2 and L3 caches (if 745x) */
-	_set_L2CR(_get_L2CR() | L2CR_L2E);
-	_set_L3CR(_get_L3CR() | L3CR_L3E);
-
-	if (ppc_md.progress)
-		ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0);
-
-	ev64260_setup_bridge();		/* set up PCI bridge(s) */
-	ev64260_setup_peripherals();	/* set up chip selects/GPP/MPP etc */
-
-	if (ppc_md.progress)
-		ppc_md.progress("ev64260_setup_arch: bridge init complete", 0);
-
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
-	ev64260_early_serial_map();
-#endif
-
-	printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc. "
-		"(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
-
-	if (ppc_md.progress)
-		ppc_md.progress("ev64260_setup_arch: exit", 0);
-
-	return;
-}
-
-/* Platform device data fixup routines. */
-#if defined(CONFIG_SERIAL_MPSC)
-static void __init
-ev64260_fixup_mpsc_pdata(struct platform_device *pdev)
-{
-	struct mpsc_pdata *pdata;
-
-	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
-
-	pdata->max_idle = 40;
-	pdata->default_baud = EV64260_DEFAULT_BAUD;
-	pdata->brg_clk_src = EV64260_MPSC_CLK_SRC;
-	pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
-
-	return;
-}
-
-static int
-ev64260_platform_notify(struct device *dev)
-{
-	static struct {
-		char	*bus_id;
-		void	((*rtn)(struct platform_device *pdev));
-	} dev_map[] = {
-		{ MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata },
-	};
-	struct platform_device	*pdev;
-	int	i;
-
-	if (dev && dev->bus_id)
-		for (i=0; i<ARRAY_SIZE(dev_map); i++)
-			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
-				BUS_ID_SIZE)) {
-
-				pdev = container_of(dev,
-					struct platform_device, dev);
-				dev_map[i].rtn(pdev);
-			}
-
-	return 0;
-}
-#endif
-
-static void
-ev64260_reset_board(void *addr)
-{
-	local_irq_disable();
-
-	/* disable and invalidate the L2 cache */
-	_set_L2CR(0);
-	_set_L2CR(0x200000);
-
-	/* flush and disable L1 I/D cache */
-	__asm__ __volatile__
-	("mfspr   3,1008\n\t"
-	 "ori	5,5,0xcc00\n\t"
-	 "ori	4,3,0xc00\n\t"
-	 "andc	5,3,5\n\t"
-	 "sync\n\t"
-	 "mtspr	1008,4\n\t"
-	 "isync\n\t"
-	 "sync\n\t"
-	 "mtspr	1008,5\n\t"
-	 "isync\n\t"
-	 "sync\n\t");
-
-	/* unmap any other random cs's that might overlap with bootcs */
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0);
-	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0);
-	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0);
-	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0);
-	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
-
-	/* map bootrom back in to gt @ reset defaults */
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
-						0xff800000, 8*1024*1024, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-
-	/* move reg base back to default, setup default pci0 */
-	mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE,
-		(1<<24) | CONFIG_MV64X60_BASE >> 20);
-
-	/* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped
-	 * via BAT or MMU, and MSR IR/DR is ON */
-	/* SRR0 has system reset vector, SRR1 has default MSR value */
-	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
-	/* NOTE: assumes reset vector is at 0xfff00100 */
-	__asm__ __volatile__
-	("mtspr   26, %0\n\t"
-	 "li      4,(1<<6)\n\t"
-	 "mtspr   27,4\n\t"
-	 "rfi\n\t"
-	 :: "r" (addr):"r4");
-
-	return;
-}
-
-static void
-ev64260_restart(char *cmd)
-{
-	volatile ulong	i = 10000000;
-
-	ev64260_reset_board((void *)0xfff00100);
-
-	while (i-- > 0);
-	panic("restart failed\n");
-}
-
-static void
-ev64260_halt(void)
-{
-	local_irq_disable();
-	while (1);
-	/* NOTREACHED */
-}
-
-static void
-ev64260_power_off(void)
-{
-	ev64260_halt();
-	/* NOTREACHED */
-}
-
-static int
-ev64260_show_cpuinfo(struct seq_file *m)
-{
-	uint pvid;
-
-	pvid = mfspr(SPRN_PVR);
-	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
-	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
-	seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
-	seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
-
-	return 0;
-}
-
-/* DS1501 RTC has too much variation to use RTC for calibration */
-static void __init
-ev64260_calibrate_decr(void)
-{
-	ulong freq;
-
-	freq = ev64260_get_bus_speed()/4;
-
-	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
-	       freq/1000000, freq%1000000);
-
-	tb_ticks_per_jiffy = freq / HZ;
-	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-
-	return;
-}
-
-/*
- * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space.
- */
-static __inline__ void
-ev64260_set_bat(void)
-{
-	mb();
-	mtspr(SPRN_DBAT1U, 0xfb0001fe);
-	mtspr(SPRN_DBAT1L, 0xfb00002a);
-	mb();
-
-	return;
-}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
-static void __init
-ev64260_map_io(void)
-{
-	io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO);
-}
-#endif
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-#ifdef CONFIG_BLK_DEV_INITRD
-	extern int	initrd_below_start_ok;
-
-	initrd_start=initrd_end=0;
-	initrd_below_start_ok=0;
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-	parse_bootinfo(find_bootinfo());
-
-	isa_mem_base = 0;
-	isa_io_base = EV64260_PCI0_IO_CPU_BASE;
-	pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE;
-
-	loops_per_jiffy = ev64260_get_cpu_speed() / HZ;
-
-	ppc_md.setup_arch = ev64260_setup_arch;
-	ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
-	ppc_md.init_IRQ = gt64260_init_irq;
-	ppc_md.get_irq = gt64260_get_irq;
-
-	ppc_md.restart = ev64260_restart;
-	ppc_md.power_off = ev64260_power_off;
-	ppc_md.halt = ev64260_halt;
-
-	ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
-
-	ppc_md.init = NULL;
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-	ppc_md.calibrate_decr = ev64260_calibrate_decr;
-
-	bh.p_base = CONFIG_MV64X60_NEW_BASE;
-
-	ev64260_set_bat();
-
-#ifdef	CONFIG_SERIAL_8250
-#if defined(CONFIG_SERIAL_TEXT_DEBUG)
-	ppc_md.setup_io_mappings = ev64260_map_io;
-	ppc_md.progress = gen550_progress;
-#endif
-#if defined(CONFIG_KGDB)
-	ppc_md.setup_io_mappings = ev64260_map_io;
-	ppc_md.early_serial_map = ev64260_early_serial_map;
-#endif
-#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
-#ifdef	CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.setup_io_mappings = ev64260_map_io;
-	ppc_md.progress = mv64x60_mpsc_progress;
-	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
-#endif	/* CONFIG_SERIAL_TEXT_DEBUG */
-#ifdef	CONFIG_KGDB
-	ppc_md.setup_io_mappings = ev64260_map_io;
-	ppc_md.early_serial_map = ev64260_early_serial_map;
-#endif	/* CONFIG_KGDB */
-
-#endif
-
-#if defined(CONFIG_SERIAL_MPSC)
-	platform_notify = ev64260_platform_notify;
-#endif
-
-	return;
-}
diff --git a/arch/ppc/platforms/ev64260.h b/arch/ppc/platforms/ev64260.h
deleted file mode 100644
index 44d90d56745..00000000000
--- a/arch/ppc/platforms/ev64260.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Definitions for Marvell/Galileo EV-64260-BP Evaluation Board.
- *
- * Author: Mark A. Greer <mgreer@mvista.com>
- *
- * 2001-2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * The MV64x60 has 2 PCI buses each with 1 window from the CPU bus to
- * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
- * We'll only use one PCI MEM window on each PCI bus.
- *
- * This is the CPU physical memory map (windows must be at least 1MB and start
- * on a boundary that is a multiple of the window size):
- *
- * 	0xfc000000-0xffffffff		- External FLASH on device module
- * 	0xfbf00000-0xfbffffff		- Embedded (on board) FLASH
- * 	0xfbe00000-0xfbefffff		- GT64260 Registers (preferably)
- * 					  but really a config option
- * 	0xfbd00000-0xfbdfffff		- External SRAM on device module
- * 	0xfbc00000-0xfbcfffff		- TODC chip on device module
- * 	0xfbb00000-0xfbbfffff		- External UART on device module
- * 	0xa2000000-0xfbafffff		- <hole>
- * 	0xa1000000-0xa1ffffff		- PCI 1 I/O (defined in gt64260.h)
- * 	0xa0000000-0xa0ffffff		- PCI 0 I/O (defined in gt64260.h)
- * 	0x90000000-0x9fffffff		- PCI 1 MEM (defined in gt64260.h)
- * 	0x80000000-0x8fffffff		- PCI 0 MEM (defined in gt64260.h)
- */
-
-#ifndef __PPC_PLATFORMS_EV64260_H
-#define __PPC_PLATFORMS_EV64260_H
-
-/* PCI mappings */
-#define	EV64260_PCI0_IO_CPU_BASE	0xa0000000
-#define	EV64260_PCI0_IO_PCI_BASE	0x00000000
-#define	EV64260_PCI0_IO_SIZE		0x01000000
-
-#define	EV64260_PCI0_MEM_CPU_BASE	0x80000000
-#define	EV64260_PCI0_MEM_PCI_BASE	0x80000000
-#define	EV64260_PCI0_MEM_SIZE		0x10000000
-
-#define	EV64260_PCI1_IO_CPU_BASE	(EV64260_PCI0_IO_CPU_BASE + \
-						EV64260_PCI0_IO_SIZE)
-#define	EV64260_PCI1_IO_PCI_BASE	(EV64260_PCI0_IO_PCI_BASE + \
-						EV64260_PCI0_IO_SIZE)
-#define	EV64260_PCI1_IO_SIZE		0x01000000
-
-#define	EV64260_PCI1_MEM_CPU_BASE	(EV64260_PCI0_MEM_CPU_BASE + \
-						EV64260_PCI0_MEM_SIZE)
-#define	EV64260_PCI1_MEM_PCI_BASE	(EV64260_PCI0_MEM_PCI_BASE + \
-						EV64260_PCI0_MEM_SIZE)
-#define	EV64260_PCI1_MEM_SIZE		0x10000000
-
-/* CPU Physical Memory Map setup (other than PCI) */
-#define	EV64260_EXT_FLASH_BASE		0xfc000000
-#define	EV64260_EMB_FLASH_BASE		0xfbf00000
-#define	EV64260_EXT_SRAM_BASE		0xfbd00000
-#define	EV64260_TODC_BASE		0xfbc00000
-#define	EV64260_UART_BASE		0xfbb00000
-
-#define	EV64260_EXT_FLASH_SIZE_ACTUAL	0x04000000  /* <= 64MB Extern FLASH */
-#define	EV64260_EMB_FLASH_SIZE_ACTUAL	0x00080000  /* 512KB of Embed FLASH */
-#define	EV64260_EXT_SRAM_SIZE_ACTUAL	0x00100000  /* 1MB SDRAM */
-#define	EV64260_TODC_SIZE_ACTUAL	0x00000020  /* 32 bytes for TODC */
-#define	EV64260_UART_SIZE_ACTUAL	0x00000040  /* 64 bytes for DUART */
-
-#define	EV64260_EXT_FLASH_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
-						EV64260_EXT_FLASH_SIZE_ACTUAL)
-#define	EV64260_EMB_FLASH_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
-						EV64260_EMB_FLASH_SIZE_ACTUAL)
-#define	EV64260_EXT_SRAM_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
-						EV64260_EXT_SRAM_SIZE_ACTUAL)
-#define	EV64260_TODC_SIZE		max(GT64260_WINDOW_SIZE_MIN,	\
-						EV64260_TODC_SIZE_ACTUAL)
-/* Assembler in bootwrapper blows up if 'max' is used */
-#define	EV64260_UART_SIZE		GT64260_WINDOW_SIZE_MIN
-#define	EV64260_UART_END		((EV64260_UART_BASE +		\
-					EV64260_UART_SIZE - 1) & 0xfff00000)
-
-/* Board-specific IRQ info */
-#define	EV64260_UART_0_IRQ		85
-#define	EV64260_UART_1_IRQ		86
-#define	EV64260_PCI_0_IRQ		91
-#define	EV64260_PCI_1_IRQ		93
-
-/* Serial port setup */
-#define	EV64260_DEFAULT_BAUD		115200
-
-#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
-#define SERIAL_PORT_DFNS
-
-#define	EV64260_MPSC_CLK_SRC		8		/* TCLK */
-#define	EV64260_MPSC_CLK_FREQ		100000000	/* 100MHz clk */
-#else
-#define EV64260_SERIAL_0		(EV64260_UART_BASE + 0x20)
-#define EV64260_SERIAL_1		EV64260_UART_BASE
-
-#define BASE_BAUD	(EV64260_DEFAULT_BAUD * 2)
-
-#ifdef CONFIG_SERIAL_MANY_PORTS
-#define RS_TABLE_SIZE	64
-#else
-#define RS_TABLE_SIZE	2
-#endif
-
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
-#endif
-
-/* Required for bootloader's ns16550.c code */
-#define STD_SERIAL_PORT_DFNS 						\
-        { 0, BASE_BAUD, EV64260_SERIAL_0, EV64260_UART_0_IRQ, STD_COM_FLAGS, \
-	iomem_base: (u8 *)EV64260_SERIAL_0,	/* ttyS0 */		\
-	iomem_reg_shift: 2,						\
-	io_type: SERIAL_IO_MEM },
-
-#define SERIAL_PORT_DFNS \
-        STD_SERIAL_PORT_DFNS
-#endif
-#endif /* __PPC_PLATFORMS_EV64260_H */
diff --git a/arch/ppc/platforms/ev64360.c b/arch/ppc/platforms/ev64360.c
deleted file mode 100644
index 6765676a5c6..00000000000
--- a/arch/ppc/platforms/ev64360.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- * Board setup routines for the Marvell EV-64360-BP Evaluation Board.
- *
- * Author: Lee Nicks <allinux@gmail.com>
- *
- * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
- * Based on code done by - Mark A. Greer <mgreer@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/console.h>
-#include <linux/initrd.h>
-#include <linux/root_dev.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/bootmem.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx.h>
-#include <linux/platform_device.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/smp.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppcboot.h>
-#include <asm/mv64x60.h>
-#include <asm/machdep.h>
-#include <platforms/ev64360.h>
-
-#define BOARD_VENDOR    "Marvell"
-#define BOARD_MACHINE   "EV-64360-BP"
-
-static struct		mv64x60_handle bh;
-static void __iomem	*sram_base;
-
-static u32		ev64360_flash_size_0;
-static u32		ev64360_flash_size_1;
-
-static u32		ev64360_bus_frequency;
-
-unsigned char	__res[sizeof(bd_t)];
-
-TODC_ALLOC();
-
-static int __init
-ev64360_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	return 0;
-}
-
-static void __init
-ev64360_setup_bridge(void)
-{
-	struct mv64x60_setup_info si;
-	int i;
-
-	memset(&si, 0, sizeof(si));
-
-	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
-
-	#ifdef CONFIG_PCI
-	si.pci_1.enable_bus = 1;
-	si.pci_1.pci_io.cpu_base = EV64360_PCI1_IO_START_PROC_ADDR;
-	si.pci_1.pci_io.pci_base_hi = 0;
-	si.pci_1.pci_io.pci_base_lo = EV64360_PCI1_IO_START_PCI_ADDR;
-	si.pci_1.pci_io.size = EV64360_PCI1_IO_SIZE;
-	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_mem[0].cpu_base = EV64360_PCI1_MEM_START_PROC_ADDR;
-	si.pci_1.pci_mem[0].pci_base_hi = EV64360_PCI1_MEM_START_PCI_HI_ADDR;
-	si.pci_1.pci_mem[0].pci_base_lo = EV64360_PCI1_MEM_START_PCI_LO_ADDR;
-	si.pci_1.pci_mem[0].size = EV64360_PCI1_MEM_SIZE;
-	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_cmd_bits = 0;
-	si.pci_1.latency_timer = 0x80;
-	#else
-	si.pci_0.enable_bus = 0;
-	si.pci_1.enable_bus = 0;
-	#endif
-
-	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
-
-		si.pci_1.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-#else
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
-
-		si.pci_1.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
-#endif
-	}
-
-	if (mv64x60_init(&bh, &si))
-		printk(KERN_WARNING "Bridge initialization failed.\n");
-
-	#ifdef CONFIG_PCI
-	pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = ev64360_map_irq;
-	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
-
-	mv64x60_set_bus(&bh, 1, 0);
-	bh.hose_b->first_busno = 0;
-	bh.hose_b->last_busno = 0xff;
-	#endif
-}
-
-/* Bridge & platform setup routines */
-void __init
-ev64360_intr_setup(void)
-{
-	/* MPP 8, 9, and 10 */
-	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
-
-	/*
-	 * Define GPP 8,9,and 10 interrupt polarity as active low
-	 * input signal and level triggered
-	 */
-	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
-	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
-
-	/* Config GPP intr ctlr to respond to level trigger */
-	mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
-
-	/* Erranum FEr PCI-#8 */
-	mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1<<5) | (1<<9));
-	mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<5) | (1<<9));
-
-	/*
-	 * Dismiss and then enable interrupt on GPP interrupt cause
-	 * for CPU #0
-	 */
-	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
-	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
-
-	/*
-	 * Dismiss and then enable interrupt on CPU #0 high cause reg
-	 * BIT25 summarizes GPP interrupts 8-15
-	 */
-	mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
-}
-
-void __init
-ev64360_setup_peripherals(void)
-{
-	u32 base;
-
-	/* Set up window for boot CS */
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
-		 EV64360_BOOT_WINDOW_BASE, EV64360_BOOT_WINDOW_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-
-	/* We only use the 32-bit flash */
-	mv64x60_get_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, &base,
-		&ev64360_flash_size_0);
-	ev64360_flash_size_1 = 0;
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
-		 EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
-
-	TODC_INIT(TODC_TYPE_DS1501, 0, 0,
-		ioremap(EV64360_RTC_WINDOW_BASE, EV64360_RTC_WINDOW_SIZE), 8);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
-		 EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-	sram_base = ioremap(EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
-
-	/* Set up Enet->SRAM window */
-	mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
-		EV64360_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
-	bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
-
-	/* Give enet r/w access to memory region */
-	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
-	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
-	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
-
-	mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
-	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
-			 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
-
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
-#else
-	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
-#endif
-
-	/*
-	 * Setting the SRAM to 0. Note that this generates parity errors on
-	 * internal data path in SRAM since it's first time accessing it
-	 * while after reset it's not configured.
-	 */
-	memset(sram_base, 0, MV64360_SRAM_SIZE);
-
-	/* set up PCI interrupt controller */
-	ev64360_intr_setup();
-}
-
-static void __init
-ev64360_setup_arch(void)
-{
-	if (ppc_md.progress)
-		ppc_md.progress("ev64360_setup_arch: enter", 0);
-
-	set_tb(0, 0);
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef   CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	/*
-	 * Set up the L2CR register.
-	 */
-	_set_L2CR(L2CR_L2E | L2CR_L2PE);
-
-	if (ppc_md.progress)
-		ppc_md.progress("ev64360_setup_arch: calling setup_bridge", 0);
-
-	ev64360_setup_bridge();
-	ev64360_setup_peripherals();
-	ev64360_bus_frequency = ev64360_bus_freq();
-
-	printk(KERN_INFO "%s %s port (C) 2005 Lee Nicks "
-		"(allinux@gmail.com)\n", BOARD_VENDOR, BOARD_MACHINE);
-	if (ppc_md.progress)
-		ppc_md.progress("ev64360_setup_arch: exit", 0);
-}
-
-/* Platform device data fixup routines. */
-#if defined(CONFIG_SERIAL_MPSC)
-static void __init
-ev64360_fixup_mpsc_pdata(struct platform_device *pdev)
-{
-	struct mpsc_pdata *pdata;
-
-	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
-
-	pdata->max_idle = 40;
-	pdata->default_baud = EV64360_DEFAULT_BAUD;
-	pdata->brg_clk_src = EV64360_MPSC_CLK_SRC;
-	/*
-	 * TCLK (not SysCLk) is routed to BRG, then to the MPSC.  On most parts,
-	 * TCLK == SysCLK but on 64460, they are separate pins.
-	 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
-	 */
-	pdata->brg_clk_freq = min(ev64360_bus_frequency, MV64x60_TCLK_FREQ_MAX);
-}
-#endif
-
-#if defined(CONFIG_MV643XX_ETH)
-static void __init
-ev64360_fixup_eth_pdata(struct platform_device *pdev)
-{
-	struct mv643xx_eth_platform_data *eth_pd;
-	static u16 phy_addr[] = {
-		EV64360_ETH0_PHY_ADDR,
-		EV64360_ETH1_PHY_ADDR,
-		EV64360_ETH2_PHY_ADDR,
-	};
-
-	eth_pd = pdev->dev.platform_data;
-	eth_pd->force_phy_addr = 1;
-	eth_pd->phy_addr = phy_addr[pdev->id];
-	eth_pd->tx_queue_size = EV64360_ETH_TX_QUEUE_SIZE;
-	eth_pd->rx_queue_size = EV64360_ETH_RX_QUEUE_SIZE;
-}
-#endif
-
-static int
-ev64360_platform_notify(struct device *dev)
-{
-	static struct {
-		char	*bus_id;
-		void	((*rtn)(struct platform_device *pdev));
-	} dev_map[] = {
-#if defined(CONFIG_SERIAL_MPSC)
-		{ MPSC_CTLR_NAME ".0", ev64360_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME ".1", ev64360_fixup_mpsc_pdata },
-#endif
-#if defined(CONFIG_MV643XX_ETH)
-		{ MV643XX_ETH_NAME ".0", ev64360_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME ".1", ev64360_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME ".2", ev64360_fixup_eth_pdata },
-#endif
-	};
-	struct platform_device	*pdev;
-	int	i;
-
-	if (dev && dev->bus_id)
-		for (i=0; i<ARRAY_SIZE(dev_map); i++)
-			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
-				BUS_ID_SIZE)) {
-
-				pdev = container_of(dev,
-					struct platform_device, dev);
-				dev_map[i].rtn(pdev);
-			}
-
-	return 0;
-}
-
-#ifdef CONFIG_MTD_PHYSMAP
-
-#ifndef MB
-#define MB	(1 << 20)
-#endif
-
-/*
- * MTD Layout.
- *
- * FLASH Amount:	0xff000000 - 0xffffffff
- * -------------	-----------------------
- * Reserved:		0xff000000 - 0xff03ffff
- * JFFS2 file system:	0xff040000 - 0xffefffff
- * U-boot:		0xfff00000 - 0xffffffff
- */
-static int __init
-ev64360_setup_mtd(void)
-{
-	u32	size;
-	int	ptbl_entries;
-	static struct mtd_partition	*ptbl;
-
-	size = ev64360_flash_size_0 + ev64360_flash_size_1;
-	if (!size)
-		return -ENOMEM;
-
-	ptbl_entries = 3;
-
-	if ((ptbl = kzalloc(ptbl_entries * sizeof(struct mtd_partition),
-		GFP_KERNEL)) == NULL) {
-
-		printk(KERN_WARNING "Can't alloc MTD partition table\n");
-		return -ENOMEM;
-	}
-
-	ptbl[0].name = "reserved";
-	ptbl[0].offset = 0;
-	ptbl[0].size = EV64360_MTD_RESERVED_SIZE;
-	ptbl[1].name = "jffs2";
-	ptbl[1].offset = EV64360_MTD_RESERVED_SIZE;
-	ptbl[1].size = EV64360_MTD_JFFS2_SIZE;
-	ptbl[2].name = "U-BOOT";
-	ptbl[2].offset = EV64360_MTD_RESERVED_SIZE + EV64360_MTD_JFFS2_SIZE;
-	ptbl[2].size = EV64360_MTD_UBOOT_SIZE;
-
-	physmap_map.size = size;
-	physmap_set_partitions(ptbl, ptbl_entries);
-	return 0;
-}
-
-arch_initcall(ev64360_setup_mtd);
-#endif
-
-static void
-ev64360_restart(char *cmd)
-{
-	ulong	i = 0xffffffff;
-	volatile unsigned char * rtc_base = ioremap(EV64360_RTC_WINDOW_BASE,0x4000);
-
-	/* issue hard reset */
-	rtc_base[0xf] = 0x80;
-	rtc_base[0xc] = 0x00;
-	rtc_base[0xd] = 0x01;
-	rtc_base[0xf] = 0x83;
-
-	while (i-- > 0) ;
-	panic("restart failed\n");
-}
-
-static void
-ev64360_halt(void)
-{
-	while (1) ;
-	/* NOTREACHED */
-}
-
-static void
-ev64360_power_off(void)
-{
-	ev64360_halt();
-	/* NOTREACHED */
-}
-
-static int
-ev64360_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
-	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
-	seq_printf(m, "bus speed\t: %dMHz\n", ev64360_bus_frequency/1000/1000);
-
-	return 0;
-}
-
-static void __init
-ev64360_calibrate_decr(void)
-{
-	u32 freq;
-
-	freq = ev64360_bus_frequency / 4;
-
-	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
-	       (long)freq / 1000000, (long)freq % 1000000);
-
-	tb_ticks_per_jiffy = freq / HZ;
-	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-}
-
-unsigned long __init
-ev64360_find_end_of_memory(void)
-{
-	return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
-		MV64x60_TYPE_MV64360);
-}
-
-static inline void
-ev64360_set_bat(void)
-{
-	mb();
-	mtspr(SPRN_DBAT2U, 0xf0001ffe);
-	mtspr(SPRN_DBAT2L, 0xf000002a);
-	mb();
-}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
-static void __init
-ev64360_map_io(void)
-{
-	io_block_mapping(CONFIG_MV64X60_NEW_BASE, \
-			 CONFIG_MV64X60_NEW_BASE, \
-			 0x00020000, _PAGE_IO);
-}
-#endif
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	/* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
-	 * are non-zero, then we should use the board info from the bd_t
-	 * structure and the cmdline pointed to by r6 instead of the
-	 * information from birecs, if any.  Otherwise, use the information
-	 * from birecs as discovered by the preceding call to
-	 * parse_bootinfo().  This rule should work with both PPCBoot, which
-	 * uses a bd_t board info structure, and the kernel boot wrapper,
-	 * which uses birecs.
-	 */
-	if (r3 && r6) {
-		/* copy board info structure */
-		memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
-		/* copy command line */
-		*(char *)(r7+KERNELBASE) = 0;
-		strcpy(cmd_line, (char *)(r6+KERNELBASE));
-	}
-	#ifdef CONFIG_ISA
-	isa_mem_base = 0;
-	#endif
-
-	ppc_md.setup_arch = ev64360_setup_arch;
-	ppc_md.show_cpuinfo = ev64360_show_cpuinfo;
-	ppc_md.init_IRQ = mv64360_init_irq;
-	ppc_md.get_irq = mv64360_get_irq;
-	ppc_md.restart = ev64360_restart;
-	ppc_md.power_off = ev64360_power_off;
-	ppc_md.halt = ev64360_halt;
-	ppc_md.find_end_of_memory = ev64360_find_end_of_memory;
-	ppc_md.init = NULL;
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-	ppc_md.calibrate_decr = ev64360_calibrate_decr;
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
-	ppc_md.setup_io_mappings = ev64360_map_io;
-	ppc_md.progress = mv64x60_mpsc_progress;
-	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
-#endif
-
-#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
-	platform_notify = ev64360_platform_notify;
-#endif
-
-	ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */
-}
diff --git a/arch/ppc/platforms/ev64360.h b/arch/ppc/platforms/ev64360.h
deleted file mode 100644
index b30f4722690..00000000000
--- a/arch/ppc/platforms/ev64360.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Definitions for Marvell EV-64360-BP Evaluation Board.
- *
- * Author: Lee Nicks <allinux@gmail.com>
- *
- * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
- * Based on code done by Mark A. Greer <mgreer@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-/*
- * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
- * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
- * We'll only use one PCI MEM window on each PCI bus.
- *
- * This is the CPU physical memory map (windows must be at least 64KB and start
- * on a boundary that is a multiple of the window size):
- *
- *    0x42000000-0x4203ffff      - Internal SRAM
- *    0xf1000000-0xf100ffff      - MV64360 Registers (CONFIG_MV64X60_NEW_BASE)
- *    0xfc800000-0xfcffffff      - RTC
- *    0xff000000-0xffffffff      - Boot window, 16 MB flash
- *    0xc0000000-0xc3ffffff      - PCI I/O (second hose)
- *    0x80000000-0xbfffffff      - PCI MEM (second hose)
- */
-
-#ifndef __PPC_PLATFORMS_EV64360_H
-#define __PPC_PLATFORMS_EV64360_H
-
-/* CPU Physical Memory Map setup. */
-#define EV64360_BOOT_WINDOW_BASE		0xff000000
-#define EV64360_BOOT_WINDOW_SIZE		0x01000000 /* 16 MB */
-#define EV64360_INTERNAL_SRAM_BASE		0x42000000
-#define EV64360_RTC_WINDOW_BASE			0xfc800000
-#define EV64360_RTC_WINDOW_SIZE			0x00800000 /* 8 MB */
-
-#define EV64360_PCI1_MEM_START_PROC_ADDR	0x80000000
-#define EV64360_PCI1_MEM_START_PCI_HI_ADDR	0x00000000
-#define EV64360_PCI1_MEM_START_PCI_LO_ADDR	0x80000000
-#define EV64360_PCI1_MEM_SIZE			0x40000000 /* 1 GB */
-#define EV64360_PCI1_IO_START_PROC_ADDR		0xc0000000
-#define EV64360_PCI1_IO_START_PCI_ADDR		0x00000000
-#define EV64360_PCI1_IO_SIZE			0x04000000 /* 64 MB */
-
-#define	EV64360_DEFAULT_BAUD			115200
-#define	EV64360_MPSC_CLK_SRC			8	  /* TCLK */
-#define EV64360_MPSC_CLK_FREQ			133333333
-
-#define	EV64360_MTD_RESERVED_SIZE		0x40000
-#define EV64360_MTD_JFFS2_SIZE			0xec0000
-#define EV64360_MTD_UBOOT_SIZE			0x100000
-
-#define	EV64360_ETH0_PHY_ADDR			8
-#define	EV64360_ETH1_PHY_ADDR			9
-#define	EV64360_ETH2_PHY_ADDR			10
-
-#define EV64360_ETH_TX_QUEUE_SIZE		800
-#define EV64360_ETH_RX_QUEUE_SIZE		400
-
-#define	EV64360_ETH_PORT_CONFIG_VALUE			\
-	ETH_UNICAST_NORMAL_MODE			|	\
-	ETH_DEFAULT_RX_QUEUE_0			|	\
-	ETH_DEFAULT_RX_ARP_QUEUE_0		|	\
-	ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP		|	\
-	ETH_RECEIVE_BC_IF_IP			|	\
-	ETH_RECEIVE_BC_IF_ARP			|	\
-	ETH_CAPTURE_TCP_FRAMES_DIS		|	\
-	ETH_CAPTURE_UDP_FRAMES_DIS		|	\
-	ETH_DEFAULT_RX_TCP_QUEUE_0		|	\
-	ETH_DEFAULT_RX_UDP_QUEUE_0		|	\
-	ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-#define	EV64360_ETH_PORT_CONFIG_EXTEND_VALUE		\
-	ETH_SPAN_BPDU_PACKETS_AS_NORMAL		|	\
-	ETH_PARTITION_DISABLE
-
-#define	GT_ETH_IPG_INT_RX(value)			\
-	((value & 0x3fff) << 8)
-
-#define	EV64360_ETH_PORT_SDMA_CONFIG_VALUE		\
-	ETH_RX_BURST_SIZE_4_64BIT		|	\
-	GT_ETH_IPG_INT_RX(0)			|	\
-	ETH_TX_BURST_SIZE_4_64BIT
-
-#define	EV64360_ETH_PORT_SERIAL_CONTROL_VALUE		\
-	ETH_FORCE_LINK_PASS			|	\
-	ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-	ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-	ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-	ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-	ETH_FORCE_BP_MODE_NO_JAM		|	\
-	BIT9					|	\
-	ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-	ETH_RETRANSMIT_16_ATTEMPTS		|	\
-	ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-	ETH_DTE_ADV_0				|	\
-	ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-	ETH_AUTO_NEG_NO_CHANGE			|	\
-	ETH_MAX_RX_PACKET_9700BYTE		|	\
-	ETH_CLR_EXT_LOOPBACK			|	\
-	ETH_SET_FULL_DUPLEX_MODE		|	\
-	ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
-
-static inline u32
-ev64360_bus_freq(void)
-{
-	return 133333333;
-}
-
-#endif	/* __PPC_PLATFORMS_EV64360_H */
diff --git a/arch/ppc/platforms/fads.h b/arch/ppc/platforms/fads.h
deleted file mode 100644
index 5219366667b..00000000000
--- a/arch/ppc/platforms/fads.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * A collection of structures, addresses, and values associated with
- * the Motorola 860T FADS board.  Copied from the MBX stuff.
- *
- * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
- *
- * Added MPC86XADS support.
- * The MPC86xADS manual says the board "is compatible with the MPC8xxFADS
- * for SW point of view". This is 99% correct.
- *
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- * 2005 (c) MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_FADS_H__
-#define __ASM_FADS_H__
-
-
-#include <asm/ppcboot.h>
-
-/* Memory map is configured by the PROM startup.
- * I tried to follow the FADS manual, although the startup PROM
- * dictates this and we simply have to move some of the physical
- * addresses for Linux.
- */
-#define BCSR_ADDR		((uint)0xff010000)
-
-/* PHY link change interrupt */
-#define PHY_INTERRUPT	SIU_IRQ2
-
-#define BCSR_SIZE		((uint)(64 * 1024))
-#define BCSR0			((uint)(BCSR_ADDR + 0x00))
-#define BCSR1			((uint)(BCSR_ADDR + 0x04))
-#define BCSR2			((uint)(BCSR_ADDR + 0x08))
-#define BCSR3			((uint)(BCSR_ADDR + 0x0c))
-#define BCSR4			((uint)(BCSR_ADDR + 0x10))
-
-#define IMAP_ADDR		((uint)0xff000000)
-#define IMAP_SIZE		((uint)(64 * 1024))
-
-#define PCMCIA_MEM_ADDR		((uint)0xff020000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
-
-/* Bits of interest in the BCSRs.
- */
-#define BCSR1_ETHEN		((uint)0x20000000)
-#define BCSR1_IRDAEN		((uint)0x10000000)
-#define BCSR1_RS232EN_1		((uint)0x01000000)
-#define BCSR1_PCCEN		((uint)0x00800000)
-#define BCSR1_PCCVCC0		((uint)0x00400000)
-#define BCSR1_PCCVPP0		((uint)0x00200000)
-#define BCSR1_PCCVPP1		((uint)0x00100000)
-#define BCSR1_PCCVPP_MASK	(BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
-#define BCSR1_RS232EN_2		((uint)0x00040000)
-#define BCSR1_PCCVCC1		((uint)0x00010000)
-#define BCSR1_PCCVCC_MASK	(BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
-
-#define BCSR4_ETHLOOP		((uint)0x80000000)	/* EEST Loopback */
-#define BCSR4_EEFDX		((uint)0x40000000)	/* EEST FDX enable */
-#define BCSR4_FETH_EN		((uint)0x08000000)	/* PHY enable */
-#define BCSR4_FETHCFG0		((uint)0x04000000)	/* PHY autoneg mode */
-#define BCSR4_FETHCFG1		((uint)0x00400000)	/* PHY autoneg mode */
-#define BCSR4_FETHFDE		((uint)0x02000000)	/* PHY FDX advertise */
-#define BCSR4_FETHRST		((uint)0x00200000)	/* PHY Reset */
-
-/* IO_BASE definition for pcmcia.
- */
-#define _IO_BASE	0x80000000
-#define _IO_BASE_SIZE	0x1000
-
-#ifdef CONFIG_IDE
-#define MAX_HWIFS 1
-#endif
-
-/* Interrupt level assignments.
- */
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-/* We don't use the 8259.
- */
-#define NR_8259_INTS	0
-
-/* CPM Ethernet through SCC1 or SCC2 */
-
-#if defined(CONFIG_SCC1_ENET) || defined(CONFIG_MPC8xx_SECOND_ETH_SCC1)		/* Probably 860 variant */
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- * TCLK - CLK1, RCLK - CLK2.
- */
-#define PA_ENET_RXD	((ushort)0x0001)
-#define PA_ENET_TXD	((ushort)0x0002)
-#define PA_ENET_TCLK	((ushort)0x0100)
-#define PA_ENET_RCLK	((ushort)0x0200)
-#define PB_ENET_TENA	((uint)0x00001000)
-#define PC_ENET_CLSN	((ushort)0x0010)
-#define PC_ENET_RENA	((ushort)0x0020)
-
-/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
- * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK	((uint)0x000000ff)
-#define SICR_ENET_CLKRT	((uint)0x0000002c)
-#endif /* CONFIG_SCC1_ENET */
-
-#ifdef CONFIG_SCC2_ENET		/* Probably 823/850 variant */
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- * TCLK - CLK1, RCLK - CLK2.
- */
-#define PA_ENET_RXD	((ushort)0x0004)
-#define PA_ENET_TXD	((ushort)0x0008)
-#define PA_ENET_TCLK	((ushort)0x0400)
-#define PA_ENET_RCLK	((ushort)0x0200)
-#define PB_ENET_TENA	((uint)0x00002000)
-#define PC_ENET_CLSN	((ushort)0x0040)
-#define PC_ENET_RENA	((ushort)0x0080)
-
-/* Control bits in the SICR to route TCLK and RCLK to
- * SCC2.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK	((uint)0x0000ff00)
-#define SICR_ENET_CLKRT	((uint)0x00002e00)
-#endif /* CONFIG_SCC2_ENET */
-
-#endif /* __ASM_FADS_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/hdpu.c b/arch/ppc/platforms/hdpu.c
deleted file mode 100644
index 904b518c152..00000000000
--- a/arch/ppc/platforms/hdpu.c
+++ /dev/null
@@ -1,1015 +0,0 @@
-/*
- * Board setup routines for the Sky Computers HDPU Compute Blade.
- *
- * Written by Brian Waite <waite@skycomputers.com>
- *
- * Based on code done by - Mark A. Greer <mgreer@mvista.com>
- *                         Rabeeh Khoury - rabeeh@galileo.co.il
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-
-#include <linux/pci.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/seq_file.h>
-#include <linux/platform_device.h>
-
-#include <linux/initrd.h>
-#include <linux/root_dev.h>
-#include <linux/smp.h>
-
-#include <asm/time.h>
-#include <asm/machdep.h>
-#include <asm/todc.h>
-#include <asm/mv64x60.h>
-#include <asm/ppcboot.h>
-#include <platforms/hdpu.h>
-#include <linux/mv643xx.h>
-#include <linux/hdpu_features.h>
-#include <linux/device.h>
-#include <linux/mtd/physmap.h>
-
-#define BOARD_VENDOR	"Sky Computers"
-#define BOARD_MACHINE	"HDPU-CB-A"
-
-bd_t ppcboot_bd;
-int ppcboot_bd_valid = 0;
-
-static mv64x60_handle_t bh;
-
-extern char cmd_line[];
-
-unsigned long hdpu_find_end_of_memory(void);
-void hdpu_mpsc_progress(char *s, unsigned short hex);
-void hdpu_heartbeat(void);
-
-static void parse_bootinfo(unsigned long r3,
-			   unsigned long r4, unsigned long r5,
-			   unsigned long r6, unsigned long r7);
-static void hdpu_set_l1pe(void);
-static void hdpu_cpustate_set(unsigned char new_state);
-#ifdef CONFIG_SMP
-static DEFINE_SPINLOCK(timebase_lock);
-static unsigned int timebase_upper = 0, timebase_lower = 0;
-extern int smp_tb_synchronized;
-
-void __devinit hdpu_tben_give(void);
-void __devinit hdpu_tben_take(void);
-#endif
-
-static int __init
-hdpu_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
-
-	if (hose->index == 0) {
-		static char pci_irq_table[][4] = {
-			{HDPU_PCI_0_IRQ, 0, 0, 0},
-			{HDPU_PCI_0_IRQ, 0, 0, 0},
-		};
-
-		const long min_idsel = 1, max_idsel = 2, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	} else {
-		static char pci_irq_table[][4] = {
-			{HDPU_PCI_1_IRQ, 0, 0, 0},
-		};
-
-		const long min_idsel = 1, max_idsel = 1, irqs_per_slot = 4;
-		return PCI_IRQ_TABLE_LOOKUP;
-	}
-}
-
-static void __init hdpu_intr_setup(void)
-{
-	mv64x60_write(&bh, MV64x60_GPP_IO_CNTL,
-		      (1 | (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) |
-		       (1 << 6) | (1 << 7) | (1 << 12) | (1 << 16) |
-		       (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) |
-		       (1 << 22) | (1 << 23) | (1 << 24) | (1 << 25) |
-		       (1 << 26) | (1 << 27) | (1 << 28) | (1 << 29)));
-
-	/* XXXX Erranum FEr PCI-#8 */
-	mv64x60_clr_bits(&bh, MV64x60_PCI0_CMD, (1 << 5) | (1 << 9));
-	mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1 << 5) | (1 << 9));
-
-	/*
-	 * Dismiss and then enable interrupt on GPP interrupt cause
-	 * for CPU #0
-	 */
-	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~((1 << 8) | (1 << 13)));
-	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1 << 8) | (1 << 13));
-
-	/*
-	 * Dismiss and then enable interrupt on CPU #0 high cause reg
-	 * BIT25 summarizes GPP interrupts 8-15
-	 */
-	mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1 << 25));
-}
-
-static void __init hdpu_setup_peripherals(void)
-{
-	unsigned int val;
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
-				 HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
-				 HDPU_TBEN_BASE, HDPU_TBEN_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
-				 HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
-				 HDPU_INTERNAL_SRAM_BASE,
-				 HDPU_INTERNAL_SRAM_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-
-	bh.ci->disable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN, 0, 0, 0);
-
-	mv64x60_clr_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, (1 << 3));
-	mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
-	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
-			 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
-
-	/* Enable pipelining */
-	mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1 << 13));
-	/* Enable Snoop Pipelining */
-	mv64x60_set_bits(&bh, MV64360_D_UNIT_CONTROL_HIGH, (1 << 24));
-
-	/*
-	 * Change DRAM read buffer assignment.
-	 * Assign read buffer 0 dedicated only for CPU,
-	 * and the rest read buffer 1.
-	 */
-	val = mv64x60_read(&bh, MV64360_SDRAM_CONFIG);
-	val = val & 0x03ffffff;
-	val = val | 0xf8000000;
-	mv64x60_write(&bh, MV64360_SDRAM_CONFIG, val);
-
-	/*
-	 * Configure internal SRAM -
-	 * Cache coherent write back, if CONFIG_MV64360_SRAM_CACHE_COHERENT set
-	 * Parity enabled.
-	 * Parity error propagation
-	 * Arbitration not parked for CPU only
-	 * Other bits are reserved.
-	 */
-#ifdef CONFIG_MV64360_SRAM_CACHE_COHERENT
-	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
-#else
-	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
-#endif
-
-	hdpu_intr_setup();
-}
-
-static void __init hdpu_setup_bridge(void)
-{
-	struct mv64x60_setup_info si;
-	int i;
-
-	memset(&si, 0, sizeof(si));
-
-	si.phys_reg_base = HDPU_BRIDGE_REG_BASE;
-	si.pci_0.enable_bus = 1;
-	si.pci_0.pci_io.cpu_base = HDPU_PCI0_IO_START_PROC_ADDR;
-	si.pci_0.pci_io.pci_base_hi = 0;
-	si.pci_0.pci_io.pci_base_lo = HDPU_PCI0_IO_START_PCI_ADDR;
-	si.pci_0.pci_io.size = HDPU_PCI0_IO_SIZE;
-	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_mem[0].cpu_base = HDPU_PCI0_MEM_START_PROC_ADDR;
-	si.pci_0.pci_mem[0].pci_base_hi = HDPU_PCI0_MEM_START_PCI_HI_ADDR;
-	si.pci_0.pci_mem[0].pci_base_lo = HDPU_PCI0_MEM_START_PCI_LO_ADDR;
-	si.pci_0.pci_mem[0].size = HDPU_PCI0_MEM_SIZE;
-	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_cmd_bits = 0;
-	si.pci_0.latency_timer = 0x80;
-
-	si.pci_1.enable_bus = 1;
-	si.pci_1.pci_io.cpu_base = HDPU_PCI1_IO_START_PROC_ADDR;
-	si.pci_1.pci_io.pci_base_hi = 0;
-	si.pci_1.pci_io.pci_base_lo = HDPU_PCI1_IO_START_PCI_ADDR;
-	si.pci_1.pci_io.size = HDPU_PCI1_IO_SIZE;
-	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_mem[0].cpu_base = HDPU_PCI1_MEM_START_PROC_ADDR;
-	si.pci_1.pci_mem[0].pci_base_hi = HDPU_PCI1_MEM_START_PCI_HI_ADDR;
-	si.pci_1.pci_mem[0].pci_base_lo = HDPU_PCI1_MEM_START_PCI_LO_ADDR;
-	si.pci_1.pci_mem[0].size = HDPU_PCI1_MEM_SIZE;
-	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_cmd_bits = 0;
-	si.pci_1.latency_timer = 0x80;
-
-	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
-
-		si.pci_1.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-
-		si.pci_0.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-
-#else
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;	/* errata */
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;	/* errata */
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;	/* errata */
-
-		si.pci_0.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-
-		si.pci_1.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-#endif
-	}
-
-	hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_PCI);
-
-	/* Lookup PCI host bridges */
-	mv64x60_init(&bh, &si);
-	pci_dram_offset = 0;	/* System mem at same addr on PCI & cpu bus */
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = hdpu_map_irq;
-
-	mv64x60_set_bus(&bh, 0, 0);
-	bh.hose_a->first_busno = 0;
-	bh.hose_a->last_busno = 0xff;
-	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
-
-	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
-	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
-	bh.hose_b->last_busno = 0xff;
-	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
-		bh.hose_b->first_busno);
-
-	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
-
-	hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_INIT_REG);
-	/*
-	 * Enabling of PCI internal-vs-external arbitration
-	 * is a platform- and errata-dependent decision.
-	 */
-	return;
-}
-
-#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
-static void __init hdpu_early_serial_map(void)
-{
-#ifdef	CONFIG_KGDB
-	static char first_time = 1;
-
-#if defined(CONFIG_KGDB_TTYS0)
-#define KGDB_PORT 0
-#elif defined(CONFIG_KGDB_TTYS1)
-#define KGDB_PORT 1
-#else
-#error "Invalid kgdb_tty port"
-#endif
-
-	if (first_time) {
-		gt_early_mpsc_init(KGDB_PORT,
-				   B9600 | CS8 | CREAD | HUPCL | CLOCAL);
-		first_time = 0;
-	}
-
-	return;
-#endif
-}
-#endif
-
-static void hdpu_init2(void)
-{
-	return;
-}
-
-#if defined(CONFIG_MV643XX_ETH)
-static void __init hdpu_fixup_eth_pdata(struct platform_device *pd)
-{
-
-	struct mv643xx_eth_platform_data *eth_pd;
-	eth_pd = pd->dev.platform_data;
-
-	eth_pd->force_phy_addr = 1;
-	eth_pd->phy_addr = pd->id;
-	eth_pd->speed = SPEED_100;
-	eth_pd->duplex = DUPLEX_FULL;
-	eth_pd->tx_queue_size = 400;
-	eth_pd->rx_queue_size = 800;
-}
-#endif
-
-static void __init hdpu_fixup_mpsc_pdata(struct platform_device *pd)
-{
-
-	struct mpsc_pdata *pdata;
-
-	pdata = (struct mpsc_pdata *)pd->dev.platform_data;
-
-	pdata->max_idle = 40;
-	if (ppcboot_bd_valid)
-		pdata->default_baud = ppcboot_bd.bi_baudrate;
-	else
-		pdata->default_baud = HDPU_DEFAULT_BAUD;
-	pdata->brg_clk_src = HDPU_MPSC_CLK_SRC;
-	pdata->brg_clk_freq = HDPU_MPSC_CLK_FREQ;
-}
-
-#if defined(CONFIG_HDPU_FEATURES)
-static void __init hdpu_fixup_cpustate_pdata(struct platform_device *pd)
-{
-	struct platform_device *pds[1];
-	pds[0] = pd;
-	mv64x60_pd_fixup(&bh, pds, 1);
-}
-#endif
-
-static int hdpu_platform_notify(struct device *dev)
-{
-	static struct {
-		char *bus_id;
-		void ((*rtn) (struct platform_device * pdev));
-	} dev_map[] = {
-		{
-		MPSC_CTLR_NAME ".0", hdpu_fixup_mpsc_pdata},
-#if defined(CONFIG_MV643XX_ETH)
-		{
-		MV643XX_ETH_NAME ".0", hdpu_fixup_eth_pdata},
-#endif
-#if defined(CONFIG_HDPU_FEATURES)
-		{
-		HDPU_CPUSTATE_NAME ".0", hdpu_fixup_cpustate_pdata},
-#endif
-	};
-	struct platform_device *pdev;
-	int i;
-
-	if (dev && dev->bus_id)
-		for (i = 0; i < ARRAY_SIZE(dev_map); i++)
-			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
-				     BUS_ID_SIZE)) {
-
-				pdev = container_of(dev,
-						    struct platform_device,
-						    dev);
-				dev_map[i].rtn(pdev);
-			}
-
-	return 0;
-}
-
-static void __init hdpu_setup_arch(void)
-{
-	if (ppc_md.progress)
-		ppc_md.progress("hdpu_setup_arch: enter", 0);
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef	CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	ppc_md.heartbeat = hdpu_heartbeat;
-
-	ppc_md.heartbeat_reset = HZ;
-	ppc_md.heartbeat_count = 1;
-
-	if (ppc_md.progress)
-		ppc_md.progress("hdpu_setup_arch: Enabling L2 cache", 0);
-
-	/* Enable L1 Parity Bits */
-	hdpu_set_l1pe();
-
-	/* Enable L2 and L3 caches (if 745x) */
-	_set_L2CR(0x80080000);
-
-	if (ppc_md.progress)
-		ppc_md.progress("hdpu_setup_arch: enter", 0);
-
-	hdpu_setup_bridge();
-
-	hdpu_setup_peripherals();
-
-#ifdef CONFIG_SERIAL_MPSC_CONSOLE
-	hdpu_early_serial_map();
-#endif
-
-	printk("SKY HDPU Compute Blade \n");
-
-	if (ppc_md.progress)
-		ppc_md.progress("hdpu_setup_arch: exit", 0);
-
-	hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_OK);
-	return;
-}
-static void __init hdpu_init_irq(void)
-{
-	mv64360_init_irq();
-}
-
-static void __init hdpu_set_l1pe()
-{
-	unsigned long ictrl;
-	asm volatile ("mfspr %0, 1011":"=r" (ictrl):);
-	ictrl |= ICTRL_EICE | ICTRL_EDC | ICTRL_EICP;
-	asm volatile ("mtspr 1011, %0"::"r" (ictrl));
-}
-
-/*
- * Set BAT 1 to map 0xf1000000 to end of physical memory space.
- */
-static __inline__ void hdpu_set_bat(void)
-{
-	mb();
-	mtspr(SPRN_DBAT1U, 0xf10001fe);
-	mtspr(SPRN_DBAT1L, 0xf100002a);
-	mb();
-
-	return;
-}
-
-unsigned long __init hdpu_find_end_of_memory(void)
-{
-	return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
-				    MV64x60_TYPE_MV64360);
-}
-
-static void hdpu_reset_board(void)
-{
-	volatile int infinite = 1;
-
-	hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_RESET);
-
-	local_irq_disable();
-
-	/* Clear all the LEDs */
-	mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) |
-						   (1 << 5) | (1 << 6)));
-
-	/* disable and invalidate the L2 cache */
-	_set_L2CR(0);
-	_set_L2CR(0x200000);
-
-	/* flush and disable L1 I/D cache */
-	__asm__ __volatile__
-	    ("\n"
-	     "mfspr   3,1008\n"
-	     "ori	5,5,0xcc00\n"
-	     "ori	4,3,0xc00\n"
-	     "andc	5,3,5\n"
-	     "sync\n"
-	     "mtspr	1008,4\n"
-	     "isync\n" "sync\n" "mtspr	1008,5\n" "isync\n" "sync\n");
-
-	/* Hit the reset bit */
-	mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 3));
-
-	while (infinite)
-		infinite = infinite;
-
-	return;
-}
-
-static void hdpu_restart(char *cmd)
-{
-	volatile ulong i = 10000000;
-
-	hdpu_reset_board();
-
-	while (i-- > 0) ;
-	panic("restart failed\n");
-}
-
-static void hdpu_halt(void)
-{
-	local_irq_disable();
-
-	hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_HALT);
-
-	/* Clear all the LEDs */
-	mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, ((1 << 4) | (1 << 5) |
-						   (1 << 6)));
-	while (1) ;
-	/* NOTREACHED */
-}
-
-static void hdpu_power_off(void)
-{
-	hdpu_halt();
-	/* NOTREACHED */
-}
-
-static int hdpu_show_cpuinfo(struct seq_file *m)
-{
-	uint pvid;
-
-	pvid = mfspr(SPRN_PVR);
-	seq_printf(m, "vendor\t\t: Sky Computers\n");
-	seq_printf(m, "machine\t\t: HDPU Compute Blade\n");
-	seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
-		   pvid, (pvid & (1 << 15) ? "IBM" : "Motorola"));
-
-	return 0;
-}
-
-static void __init hdpu_calibrate_decr(void)
-{
-	ulong freq;
-
-	if (ppcboot_bd_valid)
-		freq = ppcboot_bd.bi_busfreq / 4;
-	else
-		freq = 133000000;
-
-	printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
-	       freq / 1000000, freq % 1000000);
-
-	tb_ticks_per_jiffy = freq / HZ;
-	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-
-	return;
-}
-
-static void parse_bootinfo(unsigned long r3,
-			   unsigned long r4, unsigned long r5,
-			   unsigned long r6, unsigned long r7)
-{
-	bd_t *bd = NULL;
-	char *cmdline_start = NULL;
-	int cmdline_len = 0;
-
-	if (r3) {
-		if ((r3 & 0xf0000000) == 0)
-			r3 += KERNELBASE;
-		if ((r3 & 0xf0000000) == KERNELBASE) {
-			bd = (void *)r3;
-
-			memcpy(&ppcboot_bd, bd, sizeof(ppcboot_bd));
-			ppcboot_bd_valid = 1;
-		}
-	}
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (r4 && r5 && r5 > r4) {
-		if ((r4 & 0xf0000000) == 0)
-			r4 += KERNELBASE;
-		if ((r5 & 0xf0000000) == 0)
-			r5 += KERNELBASE;
-		if ((r4 & 0xf0000000) == KERNELBASE) {
-			initrd_start = r4;
-			initrd_end = r5;
-			initrd_below_start_ok = 1;
-		}
-	}
-#endif				/* CONFIG_BLK_DEV_INITRD */
-
-	if (r6 && r7 && r7 > r6) {
-		if ((r6 & 0xf0000000) == 0)
-			r6 += KERNELBASE;
-		if ((r7 & 0xf0000000) == 0)
-			r7 += KERNELBASE;
-		if ((r6 & 0xf0000000) == KERNELBASE) {
-			cmdline_start = (void *)r6;
-			cmdline_len = (r7 - r6);
-			strncpy(cmd_line, cmdline_start, cmdline_len);
-		}
-	}
-}
-
-void hdpu_heartbeat(void)
-{
-	if (mv64x60_read(&bh, MV64x60_GPP_VALUE) & (1 << 5))
-		mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (1 << 5));
-	else
-		mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, (1 << 5));
-
-	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
-
-}
-
-static void __init hdpu_map_io(void)
-{
-	io_block_mapping(0xf1000000, 0xf1000000, 0x20000, _PAGE_IO);
-}
-
-#ifdef CONFIG_SMP
-char hdpu_smp0[] = "SMP Cpu #0";
-char hdpu_smp1[] = "SMP Cpu #1";
-
-static irqreturn_t hdpu_smp_cpu0_int_handler(int irq, void *dev_id)
-{
-	volatile unsigned int doorbell;
-
-	doorbell = mv64x60_read(&bh, MV64360_CPU0_DOORBELL);
-
-	/* Ack the doorbell interrupts */
-	mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, doorbell);
-
-	if (doorbell & 1) {
-		smp_message_recv(0);
-	}
-	if (doorbell & 2) {
-		smp_message_recv(1);
-	}
-	if (doorbell & 4) {
-		smp_message_recv(2);
-	}
-	if (doorbell & 8) {
-		smp_message_recv(3);
-	}
-	return IRQ_HANDLED;
-}
-
-static irqreturn_t hdpu_smp_cpu1_int_handler(int irq, void *dev_id)
-{
-	volatile unsigned int doorbell;
-
-	doorbell = mv64x60_read(&bh, MV64360_CPU1_DOORBELL);
-
-	/* Ack the doorbell interrupts */
-	mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, doorbell);
-
-	if (doorbell & 1) {
-		smp_message_recv(0);
-	}
-	if (doorbell & 2) {
-		smp_message_recv(1);
-	}
-	if (doorbell & 4) {
-		smp_message_recv(2);
-	}
-	if (doorbell & 8) {
-		smp_message_recv(3);
-	}
-	return IRQ_HANDLED;
-}
-
-static void smp_hdpu_CPU_two(void)
-{
-	__asm__ __volatile__
-	    ("\n"
-	     "lis     3,0x0000\n"
-	     "ori     3,3,0x00c0\n"
-	     "mtspr   26, 3\n" "li      4,0\n" "mtspr   27,4\n" "rfi");
-
-}
-
-static int smp_hdpu_probe(void)
-{
-	int *cpu_count_reg;
-	int num_cpus = 0;
-
-	cpu_count_reg = ioremap(HDPU_NEXUS_ID_BASE, HDPU_NEXUS_ID_SIZE);
-	if (cpu_count_reg) {
-		num_cpus = (*cpu_count_reg >> 20) & 0x3;
-		iounmap(cpu_count_reg);
-	}
-
-	/* Validate the bits in the CPLD. If we could not map the reg, return 2.
-	 * If the register reported 0 or 3, return 2.
-	 * Older CPLD revisions set these bits to all ones (val = 3).
-	 */
-	if ((num_cpus < 1) || (num_cpus > 2)) {
-		printk
-		    ("Unable to determine the number of processors %d . deafulting to 2.\n",
-		     num_cpus);
-		num_cpus = 2;
-	}
-	return num_cpus;
-}
-
-static void
-smp_hdpu_message_pass(int target, int msg)
-{
-	if (msg > 0x3) {
-		printk("SMP %d: smp_message_pass: unknown msg %d\n",
-		       smp_processor_id(), msg);
-		return;
-	}
-	switch (target) {
-	case MSG_ALL:
-		mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
-		mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
-		break;
-	case MSG_ALL_BUT_SELF:
-		if (smp_processor_id())
-			mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
-		else
-			mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
-		break;
-	default:
-		if (target == 0)
-			mv64x60_write(&bh, MV64360_CPU0_DOORBELL, 1 << msg);
-		else
-			mv64x60_write(&bh, MV64360_CPU1_DOORBELL, 1 << msg);
-		break;
-	}
-}
-
-static void smp_hdpu_kick_cpu(int nr)
-{
-	volatile unsigned int *bootaddr;
-
-	if (ppc_md.progress)
-		ppc_md.progress("smp_hdpu_kick_cpu", 0);
-
-	hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR | CPUSTATE_KERNEL_CPU1_KICK);
-
-       /* Disable BootCS. Must also reduce the windows size to zero. */
-	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN, 0, 0, 0);
-
-	bootaddr = ioremap(HDPU_INTERNAL_SRAM_BASE, HDPU_INTERNAL_SRAM_SIZE);
-	if (!bootaddr) {
-		if (ppc_md.progress)
-			ppc_md.progress("smp_hdpu_kick_cpu: ioremap failed", 0);
-		return;
-	}
-
-	memcpy((void *)(bootaddr + 0x40), (void *)&smp_hdpu_CPU_two, 0x20);
-
-	/* map SRAM to 0xfff00000 */
-	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
-				 0xfff00000, HDPU_INTERNAL_SRAM_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-
-	/* Enable CPU1 arbitration */
-	mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1 << 9));
-
-	/*
-	 * Wait 100mSecond until other CPU has reached __secondary_start.
-	 * When it reaches, it is permittable to rever the SRAM mapping etc...
-	 */
-	mdelay(100);
-	*(unsigned long *)KERNELBASE = nr;
-	asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
-
-	iounmap(bootaddr);
-
-	/* Set up window for internal sram (256KByte insize) */
-	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
-				 HDPU_INTERNAL_SRAM_BASE,
-				 HDPU_INTERNAL_SRAM_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-	/*
-	 * Set up windows for embedded FLASH (using boot CS window).
-	 */
-
-	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
-				 HDPU_EMB_FLASH_BASE, HDPU_EMB_FLASH_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-}
-
-static void smp_hdpu_setup_cpu(int cpu_nr)
-{
-	if (cpu_nr == 0) {
-		if (ppc_md.progress)
-			ppc_md.progress("smp_hdpu_setup_cpu 0", 0);
-		mv64x60_write(&bh, MV64360_CPU0_DOORBELL_CLR, 0xff);
-		mv64x60_write(&bh, MV64360_CPU0_DOORBELL_MASK, 0xff);
-		request_irq(60, hdpu_smp_cpu0_int_handler,
-			    IRQF_DISABLED, hdpu_smp0, 0);
-	}
-
-	if (cpu_nr == 1) {
-		if (ppc_md.progress)
-			ppc_md.progress("smp_hdpu_setup_cpu 1", 0);
-
-		hdpu_cpustate_set(CPUSTATE_KERNEL_MAJOR |
-				  CPUSTATE_KERNEL_CPU1_OK);
-
-		/* Enable L1 Parity Bits */
-		hdpu_set_l1pe();
-
-		/* Enable L2 cache */
-		_set_L2CR(0);
-		_set_L2CR(0x80080000);
-
-		mv64x60_write(&bh, MV64360_CPU1_DOORBELL_CLR, 0x0);
-		mv64x60_write(&bh, MV64360_CPU1_DOORBELL_MASK, 0xff);
-		request_irq(28, hdpu_smp_cpu1_int_handler,
-			    IRQF_DISABLED, hdpu_smp1, 0);
-	}
-
-}
-
-void __devinit hdpu_tben_give()
-{
-	volatile unsigned long *val = 0;
-
-	/* By writing 0 to the TBEN_BASE, the timebases is frozen */
-	val = ioremap(HDPU_TBEN_BASE, 4);
-	*val = 0;
-	mb();
-
-	spin_lock(&timebase_lock);
-	timebase_upper = get_tbu();
-	timebase_lower = get_tbl();
-	spin_unlock(&timebase_lock);
-
-	while (timebase_upper || timebase_lower)
-		barrier();
-
-	/* By writing 1 to the TBEN_BASE, the timebases is thawed */
-	*val = 1;
-	mb();
-
-	iounmap(val);
-
-}
-
-void __devinit hdpu_tben_take()
-{
-	while (!(timebase_upper || timebase_lower))
-		barrier();
-
-	spin_lock(&timebase_lock);
-	set_tb(timebase_upper, timebase_lower);
-	timebase_upper = 0;
-	timebase_lower = 0;
-	spin_unlock(&timebase_lock);
-}
-
-static struct smp_ops_t hdpu_smp_ops = {
-	.message_pass = smp_hdpu_message_pass,
-	.probe = smp_hdpu_probe,
-	.kick_cpu = smp_hdpu_kick_cpu,
-	.setup_cpu = smp_hdpu_setup_cpu,
-	.give_timebase = hdpu_tben_give,
-	.take_timebase = hdpu_tben_take,
-};
-#endif				/* CONFIG_SMP */
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(r3, r4, r5, r6, r7);
-
-	isa_mem_base = 0;
-
-	ppc_md.setup_arch = hdpu_setup_arch;
-	ppc_md.init = hdpu_init2;
-	ppc_md.show_cpuinfo = hdpu_show_cpuinfo;
-	ppc_md.init_IRQ = hdpu_init_irq;
-	ppc_md.get_irq = mv64360_get_irq;
-	ppc_md.restart = hdpu_restart;
-	ppc_md.power_off = hdpu_power_off;
-	ppc_md.halt = hdpu_halt;
-	ppc_md.find_end_of_memory = hdpu_find_end_of_memory;
-	ppc_md.calibrate_decr = hdpu_calibrate_decr;
-	ppc_md.setup_io_mappings = hdpu_map_io;
-
-	bh.p_base = CONFIG_MV64X60_NEW_BASE;
-	bh.v_base = (unsigned long *)bh.p_base;
-
-	hdpu_set_bat();
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG)
-	ppc_md.progress = hdpu_mpsc_progress;	/* embedded UART */
-	mv64x60_progress_init(bh.p_base);
-#endif				/* CONFIG_SERIAL_TEXT_DEBUG */
-
-#ifdef CONFIG_SMP
-	smp_ops = &hdpu_smp_ops;
-#endif				/* CONFIG_SMP */
-
-#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
-	platform_notify = hdpu_platform_notify;
-#endif
-	return;
-}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
-/* SMP safe version of the serial text debug routine. Uses Semaphore 0 */
-void hdpu_mpsc_progress(char *s, unsigned short hex)
-{
-	while (mv64x60_read(&bh, MV64360_WHO_AM_I) !=
-	       mv64x60_read(&bh, MV64360_SEMAPHORE_0)) {
-	}
-	mv64x60_mpsc_progress(s, hex);
-	mv64x60_write(&bh, MV64360_SEMAPHORE_0, 0xff);
-}
-#endif
-
-static void hdpu_cpustate_set(unsigned char new_state)
-{
-	unsigned int state = (new_state << 21);
-	mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, (0xff << 21));
-	mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, state);
-}
-
-#ifdef CONFIG_MTD_PHYSMAP
-static struct mtd_partition hdpu_partitions[] = {
-	{
-	 .name = "Root FS",
-	 .size = 0x03400000,
-	 .offset = 0,
-	 .mask_flags = 0,
-	 },{
-	 .name = "User FS",
-	 .size = 0x00800000,
-	 .offset = 0x03400000,
-	 .mask_flags = 0,
-	 },{
-	 .name = "Kernel Image",
-	 .size = 0x002C0000,
-	 .offset = 0x03C00000,
-	 .mask_flags = 0,
-	 },{
-	 .name = "bootEnv",
-	 .size = 0x00040000,
-	 .offset = 0x03EC0000,
-	 .mask_flags = 0,
-	 },{
-	 .name = "bootROM",
-	 .size = 0x00100000,
-	 .offset = 0x03F00000,
-	 .mask_flags = 0,
-	 }
-};
-
-static int __init hdpu_setup_mtd(void)
-{
-
-	physmap_set_partitions(hdpu_partitions, 5);
-	return 0;
-}
-
-arch_initcall(hdpu_setup_mtd);
-#endif
-
-#ifdef CONFIG_HDPU_FEATURES
-
-static struct resource hdpu_cpustate_resources[] = {
-	[0] = {
-	       .name = "addr base",
-	       .start = MV64x60_GPP_VALUE_SET,
-	       .end = MV64x60_GPP_VALUE_CLR + 1,
-	       .flags = IORESOURCE_MEM,
-	       },
-};
-
-static struct resource hdpu_nexus_resources[] = {
-	[0] = {
-	       .name = "nexus register",
-	       .start = HDPU_NEXUS_ID_BASE,
-	       .end = HDPU_NEXUS_ID_BASE + HDPU_NEXUS_ID_SIZE,
-	       .flags = IORESOURCE_MEM,
-	       },
-};
-
-static struct platform_device hdpu_cpustate_device = {
-	.name = HDPU_CPUSTATE_NAME,
-	.id = 0,
-	.num_resources = ARRAY_SIZE(hdpu_cpustate_resources),
-	.resource = hdpu_cpustate_resources,
-};
-
-static struct platform_device hdpu_nexus_device = {
-	.name = HDPU_NEXUS_NAME,
-	.id = 0,
-	.num_resources = ARRAY_SIZE(hdpu_nexus_resources),
-	.resource = hdpu_nexus_resources,
-};
-
-static int __init hdpu_add_pds(void)
-{
-	platform_device_register(&hdpu_cpustate_device);
-	platform_device_register(&hdpu_nexus_device);
-	return 0;
-}
-
-arch_initcall(hdpu_add_pds);
-#endif
diff --git a/arch/ppc/platforms/hdpu.h b/arch/ppc/platforms/hdpu.h
deleted file mode 100644
index f9e020b6970..00000000000
--- a/arch/ppc/platforms/hdpu.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Definitions for Sky Computers HDPU board.
- *
- * Brian Waite <waite@skycomputers.com>
- *
- * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
- * Based on code done by Mark A. Greer <mgreer@mvista.com>
- * Based on code done by  Tim Montgomery <timm@artesyncp.com>
- *
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-/*
- * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
- * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
- * We'll only use one PCI MEM window on each PCI bus.
- *
- * This is the CPU physical memory map (windows must be at least 64K and start
- * on a boundary that is a multiple of the window size):
- *
- *    0x80000000-0x8fffffff	 - PCI 0 MEM
- *    0xa0000000-0xafffffff	 - PCI 1 MEM
- *    0xc0000000-0xc0ffffff	 - PCI 0 I/O
- *    0xc1000000-0xc1ffffff	 - PCI 1 I/O
-
- *    0xf1000000-0xf100ffff      - MV64360 Registers
- *    0xf1010000-0xfb9fffff      - HOLE
- *    0xfbfa0000-0xfbfaffff      - TBEN
- *    0xfbf00000-0xfbfbffff      - NEXUS
- *    0xfbfc0000-0xfbffffff      - Internal SRAM
- *    0xfc000000-0xffffffff      - Boot window
- */
-
-#ifndef __PPC_PLATFORMS_HDPU_H
-#define __PPC_PLATFORMS_HDPU_H
-
-/* CPU Physical Memory Map setup. */
-#define	HDPU_BRIDGE_REG_BASE		     0xf1000000
-
-#define HDPU_TBEN_BASE                        0xfbfa0000
-#define HDPU_TBEN_SIZE                        0x00010000
-#define HDPU_NEXUS_ID_BASE                    0xfbfb0000
-#define HDPU_NEXUS_ID_SIZE                    0x00010000
-#define HDPU_INTERNAL_SRAM_BASE               0xfbfc0000
-#define HDPU_INTERNAL_SRAM_SIZE               0x00040000
-#define	HDPU_EMB_FLASH_BASE		      0xfc000000
-#define	HDPU_EMB_FLASH_SIZE      	      0x04000000
-
-/* PCI Mappings */
-
-#define HDPU_PCI0_MEM_START_PROC_ADDR         0x80000000
-#define HDPU_PCI0_MEM_START_PCI_HI_ADDR       0x00000000
-#define HDPU_PCI0_MEM_START_PCI_LO_ADDR       HDPU_PCI0_MEM_START_PROC_ADDR
-#define HDPU_PCI0_MEM_SIZE                    0x10000000
-
-#define HDPU_PCI1_MEM_START_PROC_ADDR         0xc0000000
-#define HDPU_PCI1_MEM_START_PCI_HI_ADDR       0x00000000
-#define HDPU_PCI1_MEM_START_PCI_LO_ADDR       HDPU_PCI1_MEM_START_PROC_ADDR
-#define HDPU_PCI1_MEM_SIZE                    0x20000000
-
-#define HDPU_PCI0_IO_START_PROC_ADDR          0xc0000000
-#define HDPU_PCI0_IO_START_PCI_ADDR           0x00000000
-#define HDPU_PCI0_IO_SIZE                     0x01000000
-
-#define HDPU_PCI1_IO_START_PROC_ADDR          0xc1000000
-#define HDPU_PCI1_IO_START_PCI_ADDR           0x01000000
-#define HDPU_PCI1_IO_SIZE                     0x01000000
-
-#define HDPU_DEFAULT_BAUD 115200
-#define HDPU_MPSC_CLK_SRC 8	/* TCLK */
-#define HDPU_MPSC_CLK_FREQ 133000000	/* 133 Mhz */
-
-#define	HDPU_PCI_0_IRQ		(8+64)
-#define	HDPU_PCI_1_IRQ		(13+64)
-
-#endif				/* __PPC_PLATFORMS_HDPU_H */
diff --git a/arch/ppc/platforms/hermes.h b/arch/ppc/platforms/hermes.h
deleted file mode 100644
index de91afff8ca..00000000000
--- a/arch/ppc/platforms/hermes.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Multidata HERMES-PRO ( / SL ) board specific definitions
- *
- * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de)
- */
-
-#ifndef __MACH_HERMES_H
-#define __MACH_HERMES_H
-
-
-#include <asm/ppcboot.h>
-
-#define	HERMES_IMMR_BASE    0xFF000000	/* phys. addr of IMMR			*/
-#define	HERMES_IMAP_SIZE   (64 * 1024)	/* size of mapped area			*/
-
-#define	IMAP_ADDR     HERMES_IMMR_BASE	/* physical base address of IMMR area	*/
-#define IMAP_SIZE     HERMES_IMAP_SIZE	/* mapped size of IMMR area		*/
-
-#define	FEC_INTERRUPT	 9		/* = SIU_LEVEL4				*/
-#define	CPM_INTERRUPT	11		/* = SIU_LEVEL5 (was: SIU_LEVEL2)	*/
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif	/* __MACH_HERMES_H */
diff --git a/arch/ppc/platforms/ip860.h b/arch/ppc/platforms/ip860.h
deleted file mode 100644
index 2f1f86ce144..00000000000
--- a/arch/ppc/platforms/ip860.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * MicroSys IP860 VMEBus board specific definitions
- *
- * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de)
- */
-
-#ifndef __MACH_IP860_H
-#define __MACH_IP860_H
-
-
-#include <asm/ppcboot.h>
-
-#define	IP860_IMMR_BASE	0xF1000000	/* phys. addr of IMMR			*/
-#define	IP860_IMAP_SIZE	(64 * 1024)	/* size of mapped area			*/
-
-#define	IMAP_ADDR	IP860_IMMR_BASE	/* physical base address of IMMR area	*/
-#define IMAP_SIZE	IP860_IMAP_SIZE	/* mapped size of IMMR area		*/
-
-/*
- * MPC8xx Chip Select Usage
- */
-#define	IP860_BOOT_CS		0	/* Boot (VMEBus or Flash) Chip Select 0	*/
-#define IP860_FLASH_CS		1	/* Flash	    is on Chip Select 1	*/
-#define IP860_SDRAM_CS		2	/* SDRAM	    is on Chip Select 2	*/
-#define	IP860_SRAM_CS		3	/* SRAM		    is on Chip Select 3	*/
-#define IP860_BCSR_CS		4	/* BCSR		    is on Chip Select 4	*/
-#define IP860_IP_CS		5	/* IP Slots	   are on Chip Select 5	*/
-#define IP860_VME_STD_CS	6	/* VME Standard I/O is on Chip Select 6	*/
-#define IP860_VME_SHORT_CS	7	/* VME Short    I/O is on Chip Select 7	*/
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif	/* __MACH_IP860_H */
diff --git a/arch/ppc/platforms/ivms8.h b/arch/ppc/platforms/ivms8.h
deleted file mode 100644
index 9109e684ad9..00000000000
--- a/arch/ppc/platforms/ivms8.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Speech Design Integrated Voicemail board specific definitions
- * - IVMS8  (small,  8 channels)
- * - IVML24 (large, 24 channels)
- *
- * In 2.5 when we force a new bootloader, we can merge these two, and add
- * in _MACH_'s for them. -- Tom
- *
- * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de)
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_IVMS8_H__
-#define __ASM_IVMS8_H__
-
-
-#include <asm/ppcboot.h>
-
-#define IVMS_IMMR_BASE	0xFFF00000	/* phys. addr of IMMR */
-#define IVMS_IMAP_SIZE	(64 * 1024)	/* size of mapped area */
-
-#define IMAP_ADDR	IVMS_IMMR_BASE	/* phys. base address of IMMR area */
-#define IMAP_SIZE	IVMS_IMAP_SIZE	/* mapped size of IMMR area */
-
-#define PCMCIA_MEM_ADDR	((uint)0xFE100000)
-#define PCMCIA_MEM_SIZE	((uint)(64 * 1024))
-
-#define FEC_INTERRUPT	 9		/* = SIU_LEVEL4 */
-#define IDE0_INTERRUPT	10		/* = IRQ5 */
-#define CPM_INTERRUPT	11		/* = SIU_LEVEL5 (was: SIU_LEVEL2) */
-#define PHY_INTERRUPT	12		/* = IRQ6 */
-
-/* override the default number of IDE hardware interfaces */
-#define MAX_HWIFS	1
-
-/*
- * Definitions for IDE0 Interface
- */
-#define IDE0_BASE_OFFSET		0x0000	/* Offset in PCMCIA memory */
-#define IDE0_DATA_REG_OFFSET		0x0000
-#define IDE0_ERROR_REG_OFFSET		0x0081
-#define IDE0_NSECTOR_REG_OFFSET		0x0082
-#define IDE0_SECTOR_REG_OFFSET		0x0083
-#define IDE0_LCYL_REG_OFFSET		0x0084
-#define IDE0_HCYL_REG_OFFSET		0x0085
-#define IDE0_SELECT_REG_OFFSET		0x0086
-#define IDE0_STATUS_REG_OFFSET		0x0087
-#define IDE0_CONTROL_REG_OFFSET		0x0106
-#define IDE0_IRQ_REG_OFFSET		0x000A	/* not used */
-
-/* We don't use the 8259. */
-#define NR_8259_INTS	0
-
-#endif /* __ASM_IVMS8_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/katana.c b/arch/ppc/platforms/katana.c
deleted file mode 100644
index fe6e88cdb1c..00000000000
--- a/arch/ppc/platforms/katana.c
+++ /dev/null
@@ -1,902 +0,0 @@
-/*
- * Board setup routines for the Artesyn Katana cPCI boards.
- *
- * Author: Tim Montgomery <timm@artesyncp.com>
- * Maintained by: Mark A. Greer <mgreer@mvista.com>
- *
- * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
- * Based on code done by - Mark A. Greer <mgreer@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-/*
- * Supports the Artesyn 750i, 752i, and 3750.  The 752i is virtually identical
- * to the 750i except that it has an mv64460 bridge.
- */
-#include <linux/kernel.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/console.h>
-#include <linux/initrd.h>
-#include <linux/root_dev.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx.h>
-#include <linux/platform_device.h>
-#include <asm/io.h>
-#include <asm/unistd.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/smp.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/ppcboot.h>
-#include <asm/mv64x60.h>
-#include <platforms/katana.h>
-#include <asm/machdep.h>
-
-static struct mv64x60_handle	bh;
-static katana_id_t		katana_id;
-static void __iomem		*cpld_base;
-static void __iomem		*sram_base;
-static u32			katana_flash_size_0;
-static u32			katana_flash_size_1;
-static u32			katana_bus_frequency;
-static struct pci_controller	katana_hose_a;
-
-unsigned char	__res[sizeof(bd_t)];
-
-/* PCI Interrupt routing */
-static int __init
-katana_irq_lookup_750i(unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] = {
-		/*
-		 * PCI IDSEL/INTPIN->INTLINE
-		 *       A   B   C   D
-		 */
-		/* IDSEL 4  (PMC 1) */
-		{ KATANA_PCI_INTB_IRQ_750i, KATANA_PCI_INTC_IRQ_750i,
-			KATANA_PCI_INTD_IRQ_750i, KATANA_PCI_INTA_IRQ_750i },
-		/* IDSEL 5  (PMC 2) */
-		{ KATANA_PCI_INTC_IRQ_750i, KATANA_PCI_INTD_IRQ_750i,
-			KATANA_PCI_INTA_IRQ_750i, KATANA_PCI_INTB_IRQ_750i },
-		/* IDSEL 6 (T8110) */
-		{KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
-		/* IDSEL 7 (unused) */
-		{0, 0, 0, 0 },
-		/* IDSEL 8 (Intel 82544) (752i only but doesn't harm 750i) */
-		{KATANA_PCI_INTD_IRQ_750i, 0, 0, 0 },
-	};
-	const long min_idsel = 4, max_idsel = 8, irqs_per_slot = 4;
-
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static int __init
-katana_irq_lookup_3750(unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] = {
-		/*
-		 * PCI IDSEL/INTPIN->INTLINE
-		 *       A   B   C   D
-		 */
-		{ KATANA_PCI_INTA_IRQ_3750, 0, 0, 0 }, /* IDSEL 3 (BCM5691) */
-		{ KATANA_PCI_INTB_IRQ_3750, 0, 0, 0 }, /* IDSEL 4 (MV64360 #2)*/
-		{ KATANA_PCI_INTC_IRQ_3750, 0, 0, 0 }, /* IDSEL 5 (MV64360 #3)*/
-	};
-	const long min_idsel = 3, max_idsel = 5, irqs_per_slot = 4;
-
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static int __init
-katana_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	switch (katana_id) {
-	case KATANA_ID_750I:
-	case KATANA_ID_752I:
-		return katana_irq_lookup_750i(idsel, pin);
-
-	case KATANA_ID_3750:
-		return katana_irq_lookup_3750(idsel, pin);
-
-	default:
-		printk(KERN_ERR "Bogus board ID\n");
-		return 0;
-	}
-}
-
-/* Board info retrieval routines */
-void __init
-katana_get_board_id(void)
-{
-	switch (in_8(cpld_base + KATANA_CPLD_PRODUCT_ID)) {
-	case KATANA_PRODUCT_ID_3750:
-		katana_id = KATANA_ID_3750;
-		break;
-
-	case KATANA_PRODUCT_ID_750i:
-		katana_id = KATANA_ID_750I;
-		break;
-
-	case KATANA_PRODUCT_ID_752i:
-		katana_id = KATANA_ID_752I;
-		break;
-
-	default:
-		printk(KERN_ERR "Unsupported board\n");
-	}
-}
-
-int __init
-katana_get_proc_num(void)
-{
-	u16		val;
-	u8		save_exclude;
-	static int	proc = -1;
-	static u8	first_time = 1;
-
-	if (first_time) {
-		if (katana_id != KATANA_ID_3750)
-			proc = 0;
-		else {
-			save_exclude = mv64x60_pci_exclude_bridge;
-			mv64x60_pci_exclude_bridge = 0;
-
-			early_read_config_word(bh.hose_b, 0,
-				PCI_DEVFN(0,0), PCI_DEVICE_ID, &val);
-
-			mv64x60_pci_exclude_bridge = save_exclude;
-
-			switch(val) {
-			case PCI_DEVICE_ID_KATANA_3750_PROC0:
-				proc = 0;
-				break;
-
-			case PCI_DEVICE_ID_KATANA_3750_PROC1:
-				proc = 1;
-				break;
-
-			case PCI_DEVICE_ID_KATANA_3750_PROC2:
-				proc = 2;
-				break;
-
-			default:
-				printk(KERN_ERR "Bogus Device ID\n");
-			}
-		}
-
-		first_time = 0;
-	}
-
-	return proc;
-}
-
-static inline int
-katana_is_monarch(void)
-{
-	return in_8(cpld_base + KATANA_CPLD_BD_CFG_3) &
-		KATANA_CPLD_BD_CFG_3_MONARCH;
-}
-
-static void __init
-katana_setup_bridge(void)
-{
-	struct pci_controller hose;
-	struct mv64x60_setup_info si;
-	void __iomem *vaddr;
-	int i;
-	u32 v;
-	u16 val, type;
-	u8 save_exclude;
-
-	/*
-	 * Some versions of the Katana firmware mistakenly change the vendor
-	 * & device id fields in the bridge's pci device (visible via pci
-	 * config accesses).  This breaks mv64x60_init() because those values
-	 * are used to identify the type of bridge that's there.  Artesyn
-	 * claims that the subsystem vendor/device id's will have the correct
-	 * Marvell values so this code puts back the correct values from there.
-	 */
-	memset(&hose, 0, sizeof(hose));
-	vaddr = ioremap(CONFIG_MV64X60_NEW_BASE, MV64x60_INTERNAL_SPACE_SIZE);
-	setup_indirect_pci_nomap(&hose, vaddr + MV64x60_PCI0_CONFIG_ADDR,
-		vaddr + MV64x60_PCI0_CONFIG_DATA);
-	save_exclude = mv64x60_pci_exclude_bridge;
-	mv64x60_pci_exclude_bridge = 0;
-
-	early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_VENDOR_ID, &val);
-
-	if (val != PCI_VENDOR_ID_MARVELL) {
-		early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
-			PCI_SUBSYSTEM_VENDOR_ID, &val);
-		early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
-			PCI_VENDOR_ID, val);
-		early_read_config_word(&hose, 0, PCI_DEVFN(0, 0),
-			PCI_SUBSYSTEM_ID, &val);
-		early_write_config_word(&hose, 0, PCI_DEVFN(0, 0),
-			PCI_DEVICE_ID, val);
-	}
-
-	/*
-	 * While we're in here, set the hotswap register correctly.
-	 * Turn off blue LED; mask ENUM#, clear insertion & extraction bits.
-	 */
-	early_read_config_dword(&hose, 0, PCI_DEVFN(0, 0),
-		MV64360_PCICFG_CPCI_HOTSWAP, &v);
-	v &= ~(1<<19);
-	v |= ((1<<17) | (1<<22) | (1<<23));
-	early_write_config_dword(&hose, 0, PCI_DEVFN(0, 0),
-		MV64360_PCICFG_CPCI_HOTSWAP, v);
-
-	/* While we're at it, grab the bridge type for later */
-	early_read_config_word(&hose, 0, PCI_DEVFN(0, 0), PCI_DEVICE_ID, &type);
-
-	mv64x60_pci_exclude_bridge = save_exclude;
-	iounmap(vaddr);
-
-	memset(&si, 0, sizeof(si));
-
-	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
-
-	si.pci_1.enable_bus = 1;
-	si.pci_1.pci_io.cpu_base = KATANA_PCI1_IO_START_PROC_ADDR;
-	si.pci_1.pci_io.pci_base_hi = 0;
-	si.pci_1.pci_io.pci_base_lo = KATANA_PCI1_IO_START_PCI_ADDR;
-	si.pci_1.pci_io.size = KATANA_PCI1_IO_SIZE;
-	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_mem[0].cpu_base = KATANA_PCI1_MEM_START_PROC_ADDR;
-	si.pci_1.pci_mem[0].pci_base_hi = KATANA_PCI1_MEM_START_PCI_HI_ADDR;
-	si.pci_1.pci_mem[0].pci_base_lo = KATANA_PCI1_MEM_START_PCI_LO_ADDR;
-	si.pci_1.pci_mem[0].size = KATANA_PCI1_MEM_SIZE;
-	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_cmd_bits = 0;
-	si.pci_1.latency_timer = 0x80;
-
-	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
-
-		si.pci_1.acc_cntl_options[i] =
-			MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-			MV64360_PCI_ACC_CNTL_SWAP_NONE |
-			MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
-			MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-#else
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
-
-		si.pci_1.acc_cntl_options[i] =
-			MV64360_PCI_ACC_CNTL_SNOOP_WB |
-			MV64360_PCI_ACC_CNTL_SWAP_NONE |
-			MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
-			((type == PCI_DEVICE_ID_MARVELL_MV64360) ?
-				MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES :
-				MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES);
-#endif
-	}
-
-	/* Lookup PCI host bridges */
-	if (mv64x60_init(&bh, &si))
-		printk(KERN_WARNING "Bridge initialization failed.\n");
-
-	pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = katana_map_irq;
-	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
-
-	mv64x60_set_bus(&bh, 1, 0);
-	bh.hose_b->first_busno = 0;
-	bh.hose_b->last_busno = 0xff;
-
-	/*
-	 * Need to access hotswap reg which is in the pci config area of the
-	 * bridge's hose 0.  Note that pcibios_alloc_controller() can't be used
-	 * to alloc hose_a b/c that would make hose 0 known to the generic
-	 * pci code which we don't want.
-	 */
-	bh.hose_a = &katana_hose_a;
-	setup_indirect_pci_nomap(bh.hose_a,
-		bh.v_base + MV64x60_PCI0_CONFIG_ADDR,
-		bh.v_base + MV64x60_PCI0_CONFIG_DATA);
-}
-
-/* Bridge & platform setup routines */
-void __init
-katana_intr_setup(void)
-{
-	if (bh.type == MV64x60_TYPE_MV64460) /* As per instns from Marvell */
-		mv64x60_clr_bits(&bh, MV64x60_CPU_MASTER_CNTL, 1 << 15);
-
-	/* MPP 8, 9, and 10 */
-	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0xfff);
-
-	/* MPP 14 */
-	if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I))
-		mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1, 0x0f000000);
-
-	/*
-	 * Define GPP 8,9,and 10 interrupt polarity as active low
-	 * input signal and level triggered
-	 */
-	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, 0x700);
-	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, 0x700);
-
-	if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
-		mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, (1<<14));
-		mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, (1<<14));
-	}
-
-	/* Config GPP intr ctlr to respond to level trigger */
-	mv64x60_set_bits(&bh, MV64x60_COMM_ARBITER_CNTL, (1<<10));
-
-	if (bh.type == MV64x60_TYPE_MV64360) {
-		/* Erratum FEr PCI-#9 */
-		mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD,
-				(1<<4) | (1<<5) | (1<<6) | (1<<7));
-		mv64x60_set_bits(&bh, MV64x60_PCI1_CMD, (1<<8) | (1<<9));
-	} else {
-		mv64x60_clr_bits(&bh, MV64x60_PCI1_CMD, (1<<6) | (1<<7));
-		mv64x60_set_bits(&bh, MV64x60_PCI1_CMD,
-				(1<<4) | (1<<5) | (1<<8) | (1<<9));
-	}
-
-	/*
-	 * Dismiss and then enable interrupt on GPP interrupt cause
-	 * for CPU #0
-	 */
-	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~0x700);
-	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, 0x700);
-
-	if ((katana_id == KATANA_ID_750I) || (katana_id == KATANA_ID_752I)) {
-		mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1<<14));
-		mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, (1<<14));
-	}
-
-	/*
-	 * Dismiss and then enable interrupt on CPU #0 high cause reg
-	 * BIT25 summarizes GPP interrupts 8-15
-	 */
-	mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, (1<<25));
-}
-
-void __init
-katana_setup_peripherals(void)
-{
-	u32 base;
-
-	/* Set up windows for boot CS, soldered & socketed flash, and CPLD */
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
-		 KATANA_BOOT_WINDOW_BASE, KATANA_BOOT_WINDOW_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-
-	/* Assume firmware set up window sizes correctly for dev 0 & 1 */
-	mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, &base,
-		&katana_flash_size_0);
-
-	if (katana_flash_size_0 > 0) {
-		mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
-			 KATANA_SOLDERED_FLASH_BASE, katana_flash_size_0, 0);
-		bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
-	}
-
-	mv64x60_get_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, &base,
-		&katana_flash_size_1);
-
-	if (katana_flash_size_1 > 0) {
-		mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
-			 (KATANA_SOLDERED_FLASH_BASE + katana_flash_size_0),
-			 katana_flash_size_1, 0);
-		bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
-	}
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
-		 KATANA_SOCKET_BASE, KATANA_SOCKETED_FLASH_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
-		 KATANA_CPLD_BASE, KATANA_CPLD_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
-	cpld_base = ioremap(KATANA_CPLD_BASE, KATANA_CPLD_SIZE);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
-		 KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-	sram_base = ioremap(KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
-
-	/* Set up Enet->SRAM window */
-	mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
-		KATANA_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0x2);
-	bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
-
-	/* Give enet r/w access to memory region */
-	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_0, (0x3 << (4 << 1)));
-	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_1, (0x3 << (4 << 1)));
-	mv64x60_set_bits(&bh, MV64360_ENET2MEM_ACC_PROT_2, (0x3 << (4 << 1)));
-
-	mv64x60_clr_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, (1 << 3));
-	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
-			 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
-
-	/* Must wait until window set up before retrieving board id */
-	katana_get_board_id();
-
-	/* Enumerate pci bus (must know board id before getting proc number) */
-	if (katana_get_proc_num() == 0)
-		bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b, 0);
-
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x00160000);
-#else
-	mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
-#endif
-
-	/*
-	 * Setting the SRAM to 0. Note that this generates parity errors on
-	 * internal data path in SRAM since it's first time accessing it
-	 * while after reset it's not configured.
-	 */
-	memset(sram_base, 0, MV64360_SRAM_SIZE);
-
-	/* Only processor zero [on 3750] is an PCI interrupt controller */
-	if (katana_get_proc_num() == 0)
-		katana_intr_setup();
-}
-
-static void __init
-katana_enable_ipmi(void)
-{
-	u8 reset_out;
-
-	/* Enable access to IPMI ctlr by clearing IPMI PORTSEL bit in CPLD */
-	reset_out = in_8(cpld_base + KATANA_CPLD_RESET_OUT);
-	reset_out &= ~KATANA_CPLD_RESET_OUT_PORTSEL;
-	out_8(cpld_base + KATANA_CPLD_RESET_OUT, reset_out);
-}
-
-static void __init
-katana_setup_arch(void)
-{
-	if (ppc_md.progress)
-		ppc_md.progress("katana_setup_arch: enter", 0);
-
-	set_tb(0, 0);
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef   CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	/*
-	 * Set up the L2CR register.
-	 *
-	 * 750FX has only L2E, L2PE (bits 2-8 are reserved)
-	 * DD2.0 has bug that requires the L2 to be in WRT mode
-	 * avoid dirty data in cache
-	 */
-	if (PVR_REV(mfspr(SPRN_PVR)) == 0x0200) {
-		printk(KERN_INFO "DD2.0 detected. Setting L2 cache"
-			"to Writethrough mode\n");
-		_set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2WT);
-	} else
-		_set_L2CR(L2CR_L2E | L2CR_L2PE);
-
-	if (ppc_md.progress)
-		ppc_md.progress("katana_setup_arch: calling setup_bridge", 0);
-
-	katana_setup_bridge();
-	katana_setup_peripherals();
-	katana_enable_ipmi();
-
-	katana_bus_frequency = katana_bus_freq(cpld_base);
-
-	printk(KERN_INFO "Artesyn Communication Products, LLC - Katana(TM)\n");
-	if (ppc_md.progress)
-		ppc_md.progress("katana_setup_arch: exit", 0);
-}
-
-void
-katana_fixup_resources(struct pci_dev *dev)
-{
-	u16	v16;
-
-	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES>>2);
-
-	pci_read_config_word(dev, PCI_COMMAND, &v16);
-	v16 |= PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK;
-	pci_write_config_word(dev, PCI_COMMAND, v16);
-}
-
-static const unsigned int cpu_750xx[32] = { /* 750FX & 750GX */
-	 0,  0,  2,  2,  4,  5,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15,/* 0-15*/
-	16, 17, 18, 19, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40,  0 /*16-31*/
-};
-
-static int
-katana_get_cpu_freq(void)
-{
-	unsigned long	pll_cfg;
-
-	pll_cfg = (mfspr(SPRN_HID1) & 0xf8000000) >> 27;
-	return katana_bus_frequency * cpu_750xx[pll_cfg]/2;
-}
-
-/* Platform device data fixup routines. */
-#if defined(CONFIG_SERIAL_MPSC)
-static void __init
-katana_fixup_mpsc_pdata(struct platform_device *pdev)
-{
-	struct mpsc_pdata *pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
-	bd_t *bdp = (bd_t *)__res;
-
-	if (bdp->bi_baudrate)
-		pdata->default_baud = bdp->bi_baudrate;
-	else
-		pdata->default_baud = KATANA_DEFAULT_BAUD;
-
-	pdata->max_idle = 40;
-	pdata->brg_clk_src = KATANA_MPSC_CLK_SRC;
-	/*
-	 * TCLK (not SysCLk) is routed to BRG, then to the MPSC.  On most parts,
-	 * TCLK == SysCLK but on 64460, they are separate pins.
-	 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
-	 */
-	pdata->brg_clk_freq = min(katana_bus_frequency, MV64x60_TCLK_FREQ_MAX);
-}
-#endif
-
-#if defined(CONFIG_MV643XX_ETH)
-static void __init
-katana_fixup_eth_pdata(struct platform_device *pdev)
-{
-	struct mv643xx_eth_platform_data *eth_pd;
-	static u16 phy_addr[] = {
-		KATANA_ETH0_PHY_ADDR,
-		KATANA_ETH1_PHY_ADDR,
-		KATANA_ETH2_PHY_ADDR,
-	};
-
-	eth_pd = pdev->dev.platform_data;
-	eth_pd->force_phy_addr = 1;
-	eth_pd->phy_addr = phy_addr[pdev->id];
-	eth_pd->tx_queue_size = KATANA_ETH_TX_QUEUE_SIZE;
-	eth_pd->rx_queue_size = KATANA_ETH_RX_QUEUE_SIZE;
-}
-#endif
-
-#if defined(CONFIG_SYSFS)
-static void __init
-katana_fixup_mv64xxx_pdata(struct platform_device *pdev)
-{
-	struct mv64xxx_pdata *pdata = (struct mv64xxx_pdata *)
-		pdev->dev.platform_data;
-
-	/* Katana supports the mv64xxx hotswap register */
-	pdata->hs_reg_valid = 1;
-}
-#endif
-
-static int
-katana_platform_notify(struct device *dev)
-{
-	static struct {
-		char	*bus_id;
-		void	((*rtn)(struct platform_device *pdev));
-	} dev_map[] = {
-#if defined(CONFIG_SERIAL_MPSC)
-		{ MPSC_CTLR_NAME ".0", katana_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME ".1", katana_fixup_mpsc_pdata },
-#endif
-#if defined(CONFIG_MV643XX_ETH)
-		{ MV643XX_ETH_NAME ".0", katana_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME ".1", katana_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME ".2", katana_fixup_eth_pdata },
-#endif
-#if defined(CONFIG_SYSFS)
-		{ MV64XXX_DEV_NAME ".0", katana_fixup_mv64xxx_pdata },
-#endif
-	};
-	struct platform_device	*pdev;
-	int	i;
-
-	if (dev && dev->bus_id)
-		for (i=0; i<ARRAY_SIZE(dev_map); i++)
-			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
-					BUS_ID_SIZE)) {
-				pdev = container_of(dev,
-					struct platform_device, dev);
-				dev_map[i].rtn(pdev);
-			}
-
-	return 0;
-}
-
-#ifdef CONFIG_MTD_PHYSMAP
-
-#ifndef MB
-#define MB	(1 << 20)
-#endif
-
-/*
- * MTD Layout depends on amount of soldered FLASH in system. Sizes in MB.
- *
- * FLASH Amount:	128	64	32	16
- * -------------	---	--	--	--
- * Monitor:		1	1	1	1
- * Primary Kernel:	1.5	1.5	1.5	1.5
- * Primary fs:		30	30	<end>	<end>
- * Secondary Kernel:	1.5	1.5	N/A	N/A
- * Secondary fs:	<end>	<end>	N/A	N/A
- * User: 		<overlays entire FLASH except for "Monitor" section>
- */
-static int __init
-katana_setup_mtd(void)
-{
-	u32	size;
-	int	ptbl_entries;
-	static struct mtd_partition	*ptbl;
-
-	size = katana_flash_size_0 + katana_flash_size_1;
-	if (!size)
-		return -ENOMEM;
-
-	ptbl_entries = (size >= (64*MB)) ? 6 : 4;
-
-	if ((ptbl = kcalloc(ptbl_entries, sizeof(struct mtd_partition),
-			GFP_KERNEL)) == NULL) {
-		printk(KERN_WARNING "Can't alloc MTD partition table\n");
-		return -ENOMEM;
-	}
-
-	ptbl[0].name = "Monitor";
-	ptbl[0].size = KATANA_MTD_MONITOR_SIZE;
-	ptbl[1].name = "Primary Kernel";
-	ptbl[1].offset = MTDPART_OFS_NXTBLK;
-	ptbl[1].size = 0x00180000; /* 1.5 MB */
-	ptbl[2].name = "Primary Filesystem";
-	ptbl[2].offset = MTDPART_OFS_APPEND;
-	ptbl[2].size = MTDPART_SIZ_FULL; /* Correct for 16 & 32 MB */
-	ptbl[ptbl_entries-1].name = "User FLASH";
-	ptbl[ptbl_entries-1].offset = KATANA_MTD_MONITOR_SIZE;
-	ptbl[ptbl_entries-1].size = MTDPART_SIZ_FULL;
-
-	if (size >= (64*MB)) {
-		ptbl[2].size = 30*MB;
-		ptbl[3].name = "Secondary Kernel";
-		ptbl[3].offset = MTDPART_OFS_NXTBLK;
-		ptbl[3].size = 0x00180000; /* 1.5 MB */
-		ptbl[4].name = "Secondary Filesystem";
-		ptbl[4].offset = MTDPART_OFS_APPEND;
-		ptbl[4].size = MTDPART_SIZ_FULL;
-	}
-
-	physmap_map.size = size;
-	physmap_set_partitions(ptbl, ptbl_entries);
-	return 0;
-}
-arch_initcall(katana_setup_mtd);
-#endif
-
-static void
-katana_restart(char *cmd)
-{
-	ulong	i = 10000000;
-
-	/* issue hard reset to the reset command register */
-	out_8(cpld_base + KATANA_CPLD_RST_CMD, KATANA_CPLD_RST_CMD_HR);
-
-	while (i-- > 0) ;
-	panic("restart failed\n");
-}
-
-static void
-katana_halt(void)
-{
-	u8	v;
-
-	/* Turn on blue LED to indicate its okay to remove */
-	if (katana_id == KATANA_ID_750I) {
-		u32	v;
-		u8	save_exclude;
-
-		/* Set LOO bit in cPCI HotSwap reg of hose 0 to turn on LED. */
-		save_exclude = mv64x60_pci_exclude_bridge;
-		mv64x60_pci_exclude_bridge = 0;
-		early_read_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
-			MV64360_PCICFG_CPCI_HOTSWAP, &v);
-		v &= 0xff;
-		v |= (1 << 19);
-		early_write_config_dword(bh.hose_a, 0, PCI_DEVFN(0, 0),
-			MV64360_PCICFG_CPCI_HOTSWAP, v);
-		mv64x60_pci_exclude_bridge = save_exclude;
-	} else if (katana_id == KATANA_ID_752I) {
-		   v = in_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF);
-		   v |= HSL_PLD_HOT_SWAP_LED_BIT;
-		   out_8(cpld_base + HSL_PLD_BASE + HSL_PLD_HOT_SWAP_OFF, v);
-	}
-
-	while (1) ;
-	/* NOTREACHED */
-}
-
-static void
-katana_power_off(void)
-{
-	katana_halt();
-	/* NOTREACHED */
-}
-
-static int
-katana_show_cpuinfo(struct seq_file *m)
-{
-	char	*s;
-
-	seq_printf(m, "cpu freq\t: %dMHz\n",
-		(katana_get_cpu_freq() + 500000) / 1000000);
-	seq_printf(m, "bus freq\t: %ldMHz\n",
-		((long)katana_bus_frequency + 500000) / 1000000);
-	seq_printf(m, "vendor\t\t: Artesyn Communication Products, LLC\n");
-
-	seq_printf(m, "board\t\t: ");
-	switch (katana_id) {
-	case KATANA_ID_3750:
-		seq_printf(m, "Katana 3750");
-		break;
-
-	case KATANA_ID_750I:
-		seq_printf(m, "Katana 750i");
-		break;
-
-	case KATANA_ID_752I:
-		seq_printf(m, "Katana 752i");
-		break;
-
-	default:
-		seq_printf(m, "Unknown");
-		break;
-	}
-	seq_printf(m, " (product id: 0x%x)\n",
-		   in_8(cpld_base + KATANA_CPLD_PRODUCT_ID));
-
-	seq_printf(m, "pci mode\t: %sMonarch\n",
-		katana_is_monarch()? "" : "Non-");
-	seq_printf(m, "hardware rev\t: 0x%x\n",
-		   in_8(cpld_base+KATANA_CPLD_HARDWARE_VER));
-	seq_printf(m, "pld rev\t\t: 0x%x\n",
-		   in_8(cpld_base + KATANA_CPLD_PLD_VER));
-
-	switch(bh.type) {
-	case MV64x60_TYPE_GT64260A:
-		s = "gt64260a";
-		break;
-	case MV64x60_TYPE_GT64260B:
-		s = "gt64260b";
-		break;
-	case MV64x60_TYPE_MV64360:
-		s = "mv64360";
-		break;
-	case MV64x60_TYPE_MV64460:
-		s = "mv64460";
-		break;
-	default:
-		s = "Unknown";
-	}
-	seq_printf(m, "bridge type\t: %s\n", s);
-	seq_printf(m, "bridge rev\t: 0x%x\n", bh.rev);
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-	seq_printf(m, "coherency\t: %s\n", "off");
-#else
-	seq_printf(m, "coherency\t: %s\n", "on");
-#endif
-
-	return 0;
-}
-
-static void __init
-katana_calibrate_decr(void)
-{
-	u32 freq;
-
-	freq = katana_bus_frequency / 4;
-
-	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
-	       (long)freq / 1000000, (long)freq % 1000000);
-
-	tb_ticks_per_jiffy = freq / HZ;
-	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-}
-
-/*
- * The katana supports both uImage and zImage.  If uImage, get the mem size
- * from the bd info.  If zImage, the bootwrapper adds a BI_MEMSIZE entry in
- * the bi_rec data which is sucked out and put into boot_mem_size by
- * parse_bootinfo().  MMU_init() will then use the boot_mem_size for the mem
- * size and not call this routine.  The only way this will fail is when a uImage
- * is used but the fw doesn't pass in a valid bi_memsize.  This should never
- * happen, though.
- */
-unsigned long __init
-katana_find_end_of_memory(void)
-{
-	bd_t *bdp = (bd_t *)__res;
-	return bdp->bi_memsize;
-}
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
-static void __init
-katana_map_io(void)
-{
-	io_block_mapping(0xf8100000, 0xf8100000, 0x00020000, _PAGE_IO);
-}
-#endif
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	/* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
-	 * are non-zero, then we should use the board info from the bd_t
-	 * structure and the cmdline pointed to by r6 instead of the
-	 * information from birecs, if any.  Otherwise, use the information
-	 * from birecs as discovered by the preceding call to
-	 * parse_bootinfo().  This rule should work with both PPCBoot, which
-	 * uses a bd_t board info structure, and the kernel boot wrapper,
-	 * which uses birecs.
-	 */
-	if (r3 && r6) {
-		/* copy board info structure */
-		memcpy((void *)__res, (void *)(r3+KERNELBASE), sizeof(bd_t));
-		/* copy command line */
-		*(char *)(r7+KERNELBASE) = 0;
-		strcpy(cmd_line, (char *)(r6+KERNELBASE));
-	}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	/* take care of initrd if we have one */
-	if (r4) {
-		initrd_start = r4 + KERNELBASE;
-		initrd_end = r5 + KERNELBASE;
-	}
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-	isa_mem_base = 0;
-
-	ppc_md.setup_arch = katana_setup_arch;
-	ppc_md.pcibios_fixup_resources = katana_fixup_resources;
-	ppc_md.show_cpuinfo = katana_show_cpuinfo;
-	ppc_md.init_IRQ = mv64360_init_irq;
-	ppc_md.get_irq = mv64360_get_irq;
-	ppc_md.restart = katana_restart;
-	ppc_md.power_off = katana_power_off;
-	ppc_md.halt = katana_halt;
-	ppc_md.find_end_of_memory = katana_find_end_of_memory;
-	ppc_md.calibrate_decr = katana_calibrate_decr;
-
-#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
-	ppc_md.setup_io_mappings = katana_map_io;
-	ppc_md.progress = mv64x60_mpsc_progress;
-	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
-#endif
-
-#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
-	platform_notify = katana_platform_notify;
-#endif
-}
diff --git a/arch/ppc/platforms/katana.h b/arch/ppc/platforms/katana.h
deleted file mode 100644
index 0a9b036526b..00000000000
--- a/arch/ppc/platforms/katana.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * Definitions for Artesyn Katana750i/3750 board.
- *
- * Author: Tim Montgomery <timm@artesyncp.com>
- * Maintained by: Mark A. Greer <mgreer@mvista.com>
- *
- * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
- * Based on code done by Mark A. Greer <mgreer@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-/*
- * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
- * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
- * We'll only use one PCI MEM window on each PCI bus.
- *
- * This is the CPU physical memory map (windows must be at least 64 KB and start
- * on a boundary that is a multiple of the window size):
- *
- *    0xff800000-0xffffffff      - Boot window
- *    0xf8400000-0xf843ffff      - Internal SRAM
- *    0xf8200000-0xf83fffff      - CPLD
- *    0xf8100000-0xf810ffff      - MV64360 Registers (CONFIG_MV64X60_NEW_BASE)
- *    0xf8000000-0xf80fffff      - Socketed FLASH
- *    0xe0000000-0xefffffff      - Soldered FLASH
- *    0xc0000000-0xc3ffffff      - PCI I/O (second hose)
- *    0x80000000-0xbfffffff      - PCI MEM (second hose)
- */
-
-#ifndef __PPC_PLATFORMS_KATANA_H
-#define __PPC_PLATFORMS_KATANA_H
-
-/* CPU Physical Memory Map setup. */
-#define KATANA_BOOT_WINDOW_BASE			0xff800000
-#define KATANA_BOOT_WINDOW_SIZE			0x00800000 /* 8 MB */
-#define KATANA_INTERNAL_SRAM_BASE		0xf8400000
-#define KATANA_CPLD_BASE			0xf8200000
-#define KATANA_CPLD_SIZE			0x00200000 /* 2 MB */
-#define KATANA_SOCKET_BASE			0xf8000000
-#define KATANA_SOCKETED_FLASH_SIZE		0x00100000 /* 1 MB */
-#define KATANA_SOLDERED_FLASH_BASE		0xe0000000
-#define KATANA_SOLDERED_FLASH_SIZE		0x10000000 /* 256 MB */
-
-#define KATANA_PCI1_MEM_START_PROC_ADDR         0x80000000
-#define KATANA_PCI1_MEM_START_PCI_HI_ADDR       0x00000000
-#define KATANA_PCI1_MEM_START_PCI_LO_ADDR       0x80000000
-#define KATANA_PCI1_MEM_SIZE                    0x40000000 /* 1 GB */
-#define KATANA_PCI1_IO_START_PROC_ADDR          0xc0000000
-#define KATANA_PCI1_IO_START_PCI_ADDR           0x00000000
-#define KATANA_PCI1_IO_SIZE                     0x04000000 /* 64 MB */
-
-/* Board-specific IRQ info */
-#define  KATANA_PCI_INTA_IRQ_3750		(64+8)
-#define  KATANA_PCI_INTB_IRQ_3750		(64+9)
-#define  KATANA_PCI_INTC_IRQ_3750		(64+10)
-
-#define  KATANA_PCI_INTA_IRQ_750i		(64+8)
-#define  KATANA_PCI_INTB_IRQ_750i		(64+9)
-#define  KATANA_PCI_INTC_IRQ_750i		(64+10)
-#define  KATANA_PCI_INTD_IRQ_750i		(64+14)
-
-#define KATANA_CPLD_RST_EVENT			0x00000000
-#define KATANA_CPLD_RST_CMD			0x00001000
-#define KATANA_CPLD_PCI_ERR_INT_EN		0x00002000
-#define KATANA_CPLD_PCI_ERR_INT_PEND		0x00003000
-#define KATANA_CPLD_PRODUCT_ID			0x00004000
-#define KATANA_CPLD_EREADY			0x00005000
-
-#define KATANA_CPLD_HARDWARE_VER		0x00007000
-#define KATANA_CPLD_PLD_VER			0x00008000
-#define KATANA_CPLD_BD_CFG_0			0x00009000
-#define KATANA_CPLD_BD_CFG_1			0x0000a000
-#define KATANA_CPLD_BD_CFG_3			0x0000c000
-#define KATANA_CPLD_LED				0x0000d000
-#define KATANA_CPLD_RESET_OUT			0x0000e000
-
-#define KATANA_CPLD_RST_EVENT_INITACT		0x80
-#define KATANA_CPLD_RST_EVENT_SW		0x40
-#define KATANA_CPLD_RST_EVENT_WD		0x20
-#define KATANA_CPLD_RST_EVENT_COPS		0x10
-#define KATANA_CPLD_RST_EVENT_COPH		0x08
-#define KATANA_CPLD_RST_EVENT_CPCI		0x02
-#define KATANA_CPLD_RST_EVENT_FP		0x01
-
-#define KATANA_CPLD_RST_CMD_SCL			0x80
-#define KATANA_CPLD_RST_CMD_SDA			0x40
-#define KATANA_CPLD_RST_CMD_I2C			0x10
-#define KATANA_CPLD_RST_CMD_FR			0x08
-#define KATANA_CPLD_RST_CMD_SR			0x04
-#define KATANA_CPLD_RST_CMD_HR			0x01
-
-#define KATANA_CPLD_BD_CFG_0_SYSCLK_MASK	0xc0
-#define KATANA_CPLD_BD_CFG_0_SYSCLK_200		0x00
-#define KATANA_CPLD_BD_CFG_0_SYSCLK_166		0x80
-#define KATANA_CPLD_BD_CFG_0_SYSCLK_133		0xc0
-#define KATANA_CPLD_BD_CFG_0_SYSCLK_100		0x40
-
-#define KATANA_CPLD_BD_CFG_1_FL_BANK_MASK	0x03
-#define KATANA_CPLD_BD_CFG_1_FL_BANK_16MB	0x00
-#define KATANA_CPLD_BD_CFG_1_FL_BANK_32MB	0x01
-#define KATANA_CPLD_BD_CFG_1_FL_BANK_64MB	0x02
-#define KATANA_CPLD_BD_CFG_1_FL_BANK_128MB	0x03
-
-#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_MASK	0x04
-#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_ONE	0x00
-#define KATANA_CPLD_BD_CFG_1_FL_NUM_BANKS_TWO	0x04
-
-#define KATANA_CPLD_BD_CFG_3_MONARCH		0x04
-
-#define KATANA_CPLD_RESET_OUT_PORTSEL		0x80
-#define KATANA_CPLD_RESET_OUT_WD		0x20
-#define KATANA_CPLD_RESET_OUT_COPH		0x08
-#define KATANA_CPLD_RESET_OUT_PCI_RST_PCI	0x02
-#define KATANA_CPLD_RESET_OUT_PCI_RST_FP	0x01
-
-#define KATANA_MBOX_RESET_REQUEST		0xC83A
-#define KATANA_MBOX_RESET_ACK			0xE430
-#define KATANA_MBOX_RESET_DONE			0x32E5
-
-#define HSL_PLD_BASE				0x00010000
-#define HSL_PLD_J4SGA_REG_OFF			0
-#define HSL_PLD_J4GA_REG_OFF			1
-#define HSL_PLD_J2GA_REG_OFF			2
-#define HSL_PLD_HOT_SWAP_OFF			6
-#define HSL_PLD_HOT_SWAP_LED_BIT		0x1
-#define GA_MASK					0x1f
-#define HSL_PLD_SIZE				0x1000
-#define K3750_GPP_GEO_ADDR_PINS			0xf8000000
-#define K3750_GPP_GEO_ADDR_SHIFT		27
-
-#define K3750_GPP_EVENT_PROC_0			(1 << 21)
-#define K3750_GPP_EVENT_PROC_1_2		(1 << 2)
-
-#define PCI_VENDOR_ID_ARTESYN			0x1223
-#define PCI_DEVICE_ID_KATANA_3750_PROC0		0x0041
-#define PCI_DEVICE_ID_KATANA_3750_PROC1		0x0042
-#define PCI_DEVICE_ID_KATANA_3750_PROC2		0x0043
-
-#define COPROC_MEM_FUNCTION			0
-#define COPROC_MEM_BAR				0
-#define COPROC_REGS_FUNCTION			0
-#define COPROC_REGS_BAR				4
-#define COPROC_FLASH_FUNCTION			2
-#define COPROC_FLASH_BAR			4
-
-#define KATANA_IPMB_LOCAL_I2C_ADDR		0x08
-
-#define	KATANA_DEFAULT_BAUD			9600
-#define	KATANA_MPSC_CLK_SRC			8	  /* TCLK */
-
-#define	KATANA_MTD_MONITOR_SIZE			(1 << 20) /* 1 MB */
-
-#define	KATANA_ETH0_PHY_ADDR			12
-#define	KATANA_ETH1_PHY_ADDR			11
-#define	KATANA_ETH2_PHY_ADDR			4
-
-#define KATANA_PRODUCT_ID_3750			0x01
-#define KATANA_PRODUCT_ID_750i			0x02
-#define KATANA_PRODUCT_ID_752i			0x04
-
-#define KATANA_ETH_TX_QUEUE_SIZE		800
-#define KATANA_ETH_RX_QUEUE_SIZE		400
-
-#define	KATANA_ETH_PORT_CONFIG_VALUE			\
-	ETH_UNICAST_NORMAL_MODE			|	\
-	ETH_DEFAULT_RX_QUEUE_0			|	\
-	ETH_DEFAULT_RX_ARP_QUEUE_0		|	\
-	ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP		|	\
-	ETH_RECEIVE_BC_IF_IP			|	\
-	ETH_RECEIVE_BC_IF_ARP			|	\
-	ETH_CAPTURE_TCP_FRAMES_DIS		|	\
-	ETH_CAPTURE_UDP_FRAMES_DIS		|	\
-	ETH_DEFAULT_RX_TCP_QUEUE_0		|	\
-	ETH_DEFAULT_RX_UDP_QUEUE_0		|	\
-	ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-#define	KATANA_ETH_PORT_CONFIG_EXTEND_VALUE		\
-	ETH_SPAN_BPDU_PACKETS_AS_NORMAL		|	\
-	ETH_PARTITION_DISABLE
-
-#define	GT_ETH_IPG_INT_RX(value)			\
-	((value & 0x3fff) << 8)
-
-#define	KATANA_ETH_PORT_SDMA_CONFIG_VALUE		\
-	ETH_RX_BURST_SIZE_4_64BIT		|	\
-	GT_ETH_IPG_INT_RX(0)			|	\
-	ETH_TX_BURST_SIZE_4_64BIT
-
-#define	KATANA_ETH_PORT_SERIAL_CONTROL_VALUE		\
-	ETH_FORCE_LINK_PASS			|	\
-	ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-	ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-	ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-	ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-	ETH_FORCE_BP_MODE_NO_JAM		|	\
-	BIT9					|	\
-	ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-	ETH_RETRANSMIT_16_ATTEMPTS		|	\
-	ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-	ETH_DTE_ADV_0				|	\
-	ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-	ETH_AUTO_NEG_NO_CHANGE			|	\
-	ETH_MAX_RX_PACKET_9700BYTE		|	\
-	ETH_CLR_EXT_LOOPBACK			|	\
-	ETH_SET_FULL_DUPLEX_MODE		|	\
-	ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
-
-#ifndef __ASSEMBLY__
-
-typedef enum {
-	KATANA_ID_3750,
-	KATANA_ID_750I,
-	KATANA_ID_752I,
-	KATANA_ID_MAX
-} katana_id_t;
-
-#endif
-
-static inline u32
-katana_bus_freq(void __iomem *cpld_base)
-{
-	u8 bd_cfg_0;
-
-	bd_cfg_0 = in_8(cpld_base + KATANA_CPLD_BD_CFG_0);
-
-	switch (bd_cfg_0 & KATANA_CPLD_BD_CFG_0_SYSCLK_MASK) {
-	case KATANA_CPLD_BD_CFG_0_SYSCLK_200:
-		return 200000000;
-		break;
-
-	case KATANA_CPLD_BD_CFG_0_SYSCLK_166:
-		return 166666666;
-		break;
-
-	case KATANA_CPLD_BD_CFG_0_SYSCLK_133:
-		return 133333333;
-		break;
-
-	case KATANA_CPLD_BD_CFG_0_SYSCLK_100:
-		return 100000000;
-		break;
-
-	default:
-		return 133333333;
-		break;
-	}
-}
-
-#endif	/* __PPC_PLATFORMS_KATANA_H */
diff --git a/arch/ppc/platforms/lantec.h b/arch/ppc/platforms/lantec.h
deleted file mode 100644
index 5e5eb6d0f6a..00000000000
--- a/arch/ppc/platforms/lantec.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * LANTEC board specific definitions
- *
- * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
- */
-
-#ifndef __MACH_LANTEC_H
-#define __MACH_LANTEC_H
-
-
-#include <asm/ppcboot.h>
-
-#define	IMAP_ADDR	0xFFF00000	/* physical base address of IMMR area	*/
-#define IMAP_SIZE	(64 * 1024)	/* mapped size of IMMR area		*/
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif	/* __MACH_LANTEC_H */
diff --git a/arch/ppc/platforms/lite5200.c b/arch/ppc/platforms/lite5200.c
deleted file mode 100644
index b9e9db63f65..00000000000
--- a/arch/ppc/platforms/lite5200.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Platform support file for the Freescale LITE5200 based on MPC52xx.
- * A maximum of this file should be moved to syslib/mpc52xx_?????
- * so that new platform based on MPC52xx need a minimal platform file
- * ( avoid code duplication )
- *
- * 
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- *
- * Based on the 2.4 code written by Kent Borg,
- * Dale Farnsworth <dale.farnsworth@mvista.com> and
- * Wolfgang Denk <wd@denx.de>
- * 
- * Copyright 2004-2005 Sylvain Munaut <tnt@246tNt.com>
- * Copyright 2003 Motorola Inc.
- * Copyright 2003 MontaVista Software Inc.
- * Copyright 2003 DENX Software Engineering (wd@denx.de)
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/initrd.h>
-#include <linux/seq_file.h>
-#include <linux/kdev_t.h>
-#include <linux/root_dev.h>
-#include <linux/console.h>
-#include <linux/module.h>
-
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/mpc52xx.h>
-#include <asm/ppc_sys.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-
-
-extern int powersave_nap;
-
-/* Board data given by U-Boot */
-bd_t __res;
-EXPORT_SYMBOL(__res);	/* For modules */
-
-
-/* ======================================================================== */
-/* Platform specific code                                                   */
-/* ======================================================================== */
-
-/* Supported PSC function in "preference" order */
-struct mpc52xx_psc_func mpc52xx_psc_functions[] = {
-		{       .id     = 0,
-			.func   = "uart",
-		},
-		{       .id     = -1,   /* End entry */
-			.func   = NULL,
-		}
-	};
-
-
-static int
-lite5200_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "machine\t\t: Freescale LITE5200\n");
-	return 0;
-}
-
-#ifdef CONFIG_PCI
-#ifdef CONFIG_LITE5200B
-static int
-lite5200_map_irq(struct pci_dev *dev, unsigned char idsel,
-		    unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *      PCI IDSEL/INTPIN->INTLINE
-	 *        A             B             C             D
-	 */
-	{
-		{MPC52xx_IRQ0, MPC52xx_IRQ1, MPC52xx_IRQ2, MPC52xx_IRQ3},
-		{MPC52xx_IRQ1, MPC52xx_IRQ2, MPC52xx_IRQ3, MPC52xx_IRQ0},
-	};
-
-	const long min_idsel = 24, max_idsel = 25, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-#else /* Original Lite */
-static int
-lite5200_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	return (pin == 1) && (idsel==24) ? MPC52xx_IRQ0 : -1;
-}
-#endif
-#endif
-
-static void __init
-lite5200_setup_cpu(void)
-{
-	struct mpc52xx_gpio __iomem *gpio;
-	struct mpc52xx_intr __iomem *intr;
-
-	u32 port_config;
-	u32 intr_ctrl;
-
-	/* Map zones */
-	gpio = ioremap(MPC52xx_PA(MPC52xx_GPIO_OFFSET), MPC52xx_GPIO_SIZE);
-	intr = ioremap(MPC52xx_PA(MPC52xx_INTR_OFFSET), MPC52xx_INTR_SIZE);
-
-	if (!gpio || !intr) {
-		printk(KERN_ERR __FILE__ ": "
-			"Error while mapping GPIO/INTR during "
-			"lite5200_setup_cpu\n");
-		goto unmap_regs;
-	}
-
-	/* Get port mux config */
-	port_config = in_be32(&gpio->port_config);
-
-	/* 48Mhz internal, pin is GPIO */
-	port_config &= ~0x00800000;
-
-	/* USB port */
-	port_config &= ~0x00007000;	/* Differential mode - USB1 only */
-	port_config |=  0x00001000;
-
-	/* ATA CS is on csb_4/5 */
-	port_config &= ~0x03000000;
-	port_config |=  0x01000000;
-
-	/* Commit port config */
-	out_be32(&gpio->port_config, port_config);
-
-	/* IRQ[0-3] setup */
-	intr_ctrl = in_be32(&intr->ctrl);
-	intr_ctrl &= ~0x00ff0000;
-#ifdef CONFIG_LITE5200B
-	/* IRQ[0-3] Level Active Low */
-	intr_ctrl |=  0x00ff0000;
-#else
-	/* IRQ0 Level Active Low
-	 * IRQ[1-3] Level Active High */
- 	intr_ctrl |=  0x00c00000;
-#endif
-	out_be32(&intr->ctrl, intr_ctrl);
-
-	/* Unmap reg zone */
-unmap_regs:
-	if (gpio) iounmap(gpio);
-	if (intr) iounmap(intr);
-}
-
-static void __init
-lite5200_setup_arch(void)
-{
-	/* CPU & Port mux setup */
-	mpc52xx_setup_cpu();	/* Generic */
-	lite5200_setup_cpu();	/* Platform specific */
-
-#ifdef CONFIG_PCI
-	/* PCI Bridge setup */
-	mpc52xx_find_bridges();
-#endif
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-              unsigned long r6, unsigned long r7)
-{
-	/* Generic MPC52xx platform initialization */
-	/* TODO Create one and move a max of stuff in it.
-	   Put this init in the syslib */
-
-	struct bi_record *bootinfo = find_bootinfo();
-
-	if (bootinfo)
-		parse_bootinfo(bootinfo);
-	else {
-		/* Load the bd_t board info structure */
-		if (r3)
-			memcpy((void*)&__res,(void*)(r3+KERNELBASE),
-					sizeof(bd_t));
-
-#ifdef CONFIG_BLK_DEV_INITRD
-		/* Load the initrd */
-		if (r4) {
-			initrd_start = r4 + KERNELBASE;
-			initrd_end = r5 + KERNELBASE;
-		}
-#endif
-
-		/* Load the command line */
-		if (r6) {
-			*(char *)(r7+KERNELBASE) = 0;
-			strcpy(cmd_line, (char *)(r6+KERNELBASE));
-		}
-	}
-
-	/* PPC Sys identification */
-	identify_ppc_sys_by_id(mfspr(SPRN_SVR));
-
-	/* BAT setup */
-	mpc52xx_set_bat();
-
-	/* No ISA bus by default */
-#ifdef CONFIG_PCI
-	isa_io_base		= 0;
-	isa_mem_base		= 0;
-#endif
-
-	/* Powersave */
-	/* This is provided as an example on how to do it. But you
-	   need to be aware that NAP disable bus snoop and that may
-	   be required for some devices to work properly, like USB ... */
-	/* powersave_nap = 1; */
-
-
-	/* Setup the ppc_md struct */
-	ppc_md.setup_arch	= lite5200_setup_arch;
-	ppc_md.show_cpuinfo	= lite5200_show_cpuinfo;
-	ppc_md.show_percpuinfo	= NULL;
-	ppc_md.init_IRQ		= mpc52xx_init_irq;
-	ppc_md.get_irq		= mpc52xx_get_irq;
-
-#ifdef CONFIG_PCI
-	ppc_md.pci_map_irq	= lite5200_map_irq;
-#endif
-
-	ppc_md.find_end_of_memory = mpc52xx_find_end_of_memory;
-	ppc_md.setup_io_mappings  = mpc52xx_map_io;
-
-	ppc_md.restart		= mpc52xx_restart;
-	ppc_md.power_off	= mpc52xx_power_off;
-	ppc_md.halt		= mpc52xx_halt;
-
-		/* No time keeper on the LITE5200 */
-	ppc_md.time_init	= NULL;
-	ppc_md.get_rtc_time	= NULL;
-	ppc_md.set_rtc_time	= NULL;
-
-	ppc_md.calibrate_decr	= mpc52xx_calibrate_decr;
-#ifdef CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.progress		= mpc52xx_progress;
-#endif
-}
-
diff --git a/arch/ppc/platforms/lite5200.h b/arch/ppc/platforms/lite5200.h
deleted file mode 100644
index 852a18e24d0..00000000000
--- a/arch/ppc/platforms/lite5200.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Definitions for Freescale LITE5200 : MPC52xx Standard Development
- * Platform board support
- * 
- * Maintainer : Sylvain Munaut <tnt@246tNt.com>
- * 
- * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#ifndef __PLATFORMS_LITE5200_H__
-#define __PLATFORMS_LITE5200_H__
-
-/* Serial port used for low-level debug */
-#define MPC52xx_PF_CONSOLE_PORT 1	/* PSC1 */
-
-
-#endif /* __PLATFORMS_LITE5200_H__ */
diff --git a/arch/ppc/platforms/lopec.c b/arch/ppc/platforms/lopec.c
deleted file mode 100644
index 1e3aa6e9b6c..00000000000
--- a/arch/ppc/platforms/lopec.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Setup routines for the Motorola LoPEC.
- *
- * Author: Dan Cox
- * Maintainer: Tom Rini <trini@kernel.crashing.org>
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/types.h>
-#include <linux/delay.h>
-#include <linux/pci_ids.h>
-#include <linux/ioport.h>
-#include <linux/init.h>
-#include <linux/seq_file.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/root_dev.h>
-#include <linux/pci.h>
-
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/io.h>
-#include <asm/open_pic.h>
-#include <asm/i8259.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/mpc10x.h>
-#include <asm/hw_irq.h>
-#include <asm/prep_nvram.h>
-#include <asm/kgdb.h>
-
-/*
- * Define all of the IRQ senses and polarities.  Taken from the
- * LoPEC Programmer's Reference Guide.
- */
-static u_char lopec_openpic_initsenses[16] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ 0 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ 2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 3 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ 4 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ 5 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 6 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 7 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 8 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 9 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 10 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 11 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* IRQ 12 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),	/* IRQ 13 */
-	(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),	/* IRQ 14 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)	/* IRQ 15 */
-};
-
-static inline int __init
-lopec_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	int irq;
-	static char pci_irq_table[][4] = {
-		{16, 0, 0, 0}, /* ID 11 - Winbond */
-		{22, 0, 0, 0}, /* ID 12 - SCSI */
-		{0, 0, 0, 0}, /* ID 13 - nothing */
-		{17, 0, 0, 0}, /* ID 14 - 82559 Ethernet */
-		{27, 0, 0, 0}, /* ID 15 - USB */
-		{23, 0, 0, 0}, /* ID 16 - PMC slot 1 */
-		{24, 0, 0, 0}, /* ID 17 - PMC slot 2 */
-		{25, 0, 0, 0}, /* ID 18 - PCI slot */
-		{0, 0, 0, 0}, /* ID 19 - nothing */
-		{0, 0, 0, 0}, /* ID 20 - nothing */
-		{0, 0, 0, 0}, /* ID 21 - nothing */
-		{0, 0, 0, 0}, /* ID 22 - nothing */
-		{0, 0, 0, 0}, /* ID 23 - nothing */
-		{0, 0, 0, 0}, /* ID 24 - PMC slot 1b */
-		{0, 0, 0, 0}, /* ID 25 - nothing */
-		{0, 0, 0, 0}  /* ID 26 - PMC Slot 2b */
-	};
-	const long min_idsel = 11, max_idsel = 26, irqs_per_slot = 4;
-
-	irq = PCI_IRQ_TABLE_LOOKUP;
-	if (!irq)
-		return 0;
-
-	return irq;
-}
-
-static void __init
-lopec_setup_winbond_83553(struct pci_controller *hose)
-{
-	int devfn;
-
-	devfn = PCI_DEVFN(11,0);
-
-	/* IDE interrupt routing (primary 14, secondary 15) */
-	early_write_config_byte(hose, 0, devfn, 0x43, 0xef);
-	/* PCI interrupt routing */
-	early_write_config_word(hose, 0, devfn, 0x44, 0x0000);
-
-	/* ISA-PCI address decoder */
-	early_write_config_byte(hose, 0, devfn, 0x48, 0xf0);
-
-	/* RTC, kb, not used in PPC */
-	early_write_config_byte(hose, 0, devfn, 0x4d, 0x00);
-	early_write_config_byte(hose, 0, devfn, 0x4e, 0x04);
-	devfn = PCI_DEVFN(11, 1);
-	early_write_config_byte(hose, 0, devfn, 0x09, 0x8f);
-	early_write_config_dword(hose, 0, devfn, 0x40, 0x00ff0011);
-}
-
-static void __init
-lopec_find_bridges(void)
-{
-	struct pci_controller *hose;
-
-	hose = pcibios_alloc_controller();
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	if (mpc10x_bridge_init(hose, MPC10X_MEM_MAP_B, MPC10X_MEM_MAP_B,
-				MPC10X_MAPB_EUMB_BASE) == 0) {
-
-		hose->mem_resources[0].end = 0xffffffff;
-		lopec_setup_winbond_83553(hose);
-		hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-		ppc_md.pci_swizzle = common_swizzle;
-		ppc_md.pci_map_irq = lopec_map_irq;
-	}
-}
-
-static int
-lopec_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "machine\t\t: Motorola LoPEC\n");
-	return 0;
-}
-
-static void
-lopec_restart(char *cmd)
-{
-#define LOPEC_SYSSTAT1 0xffe00000
-	/* force a hard reset, if possible */
-	unsigned char reg = *((unsigned char *) LOPEC_SYSSTAT1);
-	reg |= 0x80;
-	*((unsigned char *) LOPEC_SYSSTAT1) = reg;
-
-	local_irq_disable();
-	while(1);
-#undef LOPEC_SYSSTAT1
-}
-
-static void
-lopec_halt(void)
-{
-	local_irq_disable();
-	while(1);
-}
-
-static void
-lopec_power_off(void)
-{
-	lopec_halt();
-}
-
-static void __init
-lopec_init_IRQ(void)
-{
-	int i;
-
-	/*
-	 * Provide the open_pic code with the correct table of interrupts.
-	 */
-	OpenPIC_InitSenses = lopec_openpic_initsenses;
-	OpenPIC_NumInitSenses = sizeof(lopec_openpic_initsenses);
-
-	mpc10x_set_openpic();
-
-	/* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
-	openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
-			&i8259_irq);
-
-	/*
-	 * The EPIC allows for a read in the range of 0xFEF00000 ->
-	 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
-	 */
-	i8259_init(0xfef00000, 0);
-}
-
-static int __init
-lopec_request_io(void)
-{
-	outb(0x00, 0x4d0);
-	outb(0xc0, 0x4d1);
-
-	request_region(0x00, 0x20, "dma1");
-	request_region(0x20, 0x20, "pic1");
-	request_region(0x40, 0x20, "timer");
-	request_region(0x80, 0x10, "dma page reg");
-	request_region(0xa0, 0x20, "pic2");
-	request_region(0xc0, 0x20, "dma2");
-
-	return 0;
-}
-
-device_initcall(lopec_request_io);
-
-static void __init
-lopec_map_io(void)
-{
-	io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
-	io_block_mapping(0xb0000000, 0xb0000000, 0x10000000, _PAGE_IO);
-}
-
-/*
- * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
- */
-static __inline__ void
-lopec_set_bat(void)
-{
-	mb();
-	mtspr(SPRN_DBAT1U, 0xf8000ffe);
-	mtspr(SPRN_DBAT1L, 0xf800002a);
-	mb();
-}
-
-TODC_ALLOC();
-
-static void __init
-lopec_setup_arch(void)
-{
-
-	TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
-		  ioremap(0xffe80000, 0x8000), 8);
-
-	loops_per_jiffy = 100000000/HZ;
-
-	lopec_find_bridges();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#elif defined(CONFIG_ROOT_NFS)
-        	ROOT_DEV = Root_NFS;
-#elif defined(CONFIG_BLK_DEV_IDEDISK)
-	        ROOT_DEV = Root_HDA1;
-#else
-        	ROOT_DEV = Root_SDA1;
-#endif
-
-#ifdef CONFIG_PPCBUG_NVRAM
-	/* Read in NVRAM data */
-	init_prep_nvram();
-
-	/* if no bootargs, look in NVRAM */
-	if ( cmd_line[0] == '\0' ) {
-		char *bootargs;
-		 bootargs = prep_nvram_get_var("bootargs");
-		 if (bootargs != NULL) {
-			 strcpy(cmd_line, bootargs);
-			 /* again.. */
-			 strcpy(boot_command_line, cmd_line);
-		}
-	}
-#endif
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-	lopec_set_bat();
-
-	isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
-	isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
-	pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
-	ISA_DMA_THRESHOLD = 0x00ffffff;
-	DMA_MODE_READ = 0x44;
-	DMA_MODE_WRITE = 0x48;
-	ppc_do_canonicalize_irqs = 1;
-
-	ppc_md.setup_arch = lopec_setup_arch;
-	ppc_md.show_cpuinfo = lopec_show_cpuinfo;
-	ppc_md.init_IRQ = lopec_init_IRQ;
-	ppc_md.get_irq = openpic_get_irq;
-
-	ppc_md.restart = lopec_restart;
-	ppc_md.power_off = lopec_power_off;
-	ppc_md.halt = lopec_halt;
-
-	ppc_md.setup_io_mappings = lopec_map_io;
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.calibrate_decr = todc_calibrate_decr;
-
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-
-#ifdef CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.progress = gen550_progress;
-#endif
-}
diff --git a/arch/ppc/platforms/lopec.h b/arch/ppc/platforms/lopec.h
deleted file mode 100644
index d597b687869..00000000000
--- a/arch/ppc/platforms/lopec.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * arch/ppc/platforms/lopec.h
- *
- * Definitions for Motorola LoPEC board.
- *
- * Author: Dan Cox
- *         danc@mvista.com (or, alternately, source@mvista.com)
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __H_LOPEC_SERIAL
-#define __H_LOPEC_SERIAL
-
-#define RS_TABLE_SIZE 3
-
-#define BASE_BAUD (1843200 / 16)
-
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
-#endif
-
-#define SERIAL_PORT_DFNS \
-         { 0, BASE_BAUD, 0xffe10000, 29, STD_COM_FLAGS, \
-           iomem_base: (u8 *) 0xffe10000, \
-           io_type: SERIAL_IO_MEM }, \
-         { 0, BASE_BAUD, 0xffe11000, 20, STD_COM_FLAGS, \
-           iomem_base: (u8 *) 0xffe11000, \
-           io_type: SERIAL_IO_MEM }, \
-         { 0, BASE_BAUD, 0xffe12000, 21, STD_COM_FLAGS, \
-           iomem_base: (u8 *) 0xffe12000, \
-           io_type: SERIAL_IO_MEM }
-
-#endif
diff --git a/arch/ppc/platforms/lwmon.h b/arch/ppc/platforms/lwmon.h
deleted file mode 100644
index e63f3b07a5d..00000000000
--- a/arch/ppc/platforms/lwmon.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Liebherr LWMON board specific definitions
- *
- * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
- */
-
-#ifndef __MACH_LWMON_H
-#define __MACH_LWMON_H
-
-
-#include <asm/ppcboot.h>
-
-#define	IMAP_ADDR	0xFFF00000	/* physical base address of IMMR area	*/
-#define IMAP_SIZE	(64 * 1024)	/* mapped size of IMMR area		*/
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define PCMCIA_MEM_SIZE		( 64 << 20 )
-
-#define	MAX_HWIFS	1	/* overwrite default in include/asm-ppc/ide.h	*/
-
-/*
- * Definitions for IDE0 Interface
- */
-#define IDE0_BASE_OFFSET		0
-#define IDE0_DATA_REG_OFFSET		(PCMCIA_MEM_SIZE + 0x320)
-#define IDE0_ERROR_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 1)
-#define IDE0_NSECTOR_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 2)
-#define IDE0_SECTOR_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 3)
-#define IDE0_LCYL_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 4)
-#define IDE0_HCYL_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 5)
-#define IDE0_SELECT_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 6)
-#define IDE0_STATUS_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 7)
-#define IDE0_CONTROL_REG_OFFSET		0x0106
-#define IDE0_IRQ_REG_OFFSET		0x000A	/* not used			*/
-
-#define	IDE0_INTERRUPT			13
-
-/*
- * Definitions for I2C devices
- */
-#define I2C_ADDR_AUDIO		0x28	/* Audio volume control			*/
-#define I2C_ADDR_SYSMON		0x2E	/* LM87 System Monitor			*/
-#define I2C_ADDR_RTC		0x51	/* PCF8563 RTC				*/
-#define I2C_ADDR_POWER_A	0x52	/* PCMCIA/USB power switch, channel A	*/
-#define I2C_ADDR_POWER_B	0x53	/* PCMCIA/USB power switch, channel B	*/
-#define I2C_ADDR_KEYBD		0x56	/* PIC LWE keyboard			*/
-#define I2C_ADDR_PICIO		0x57	/* PIC IO Expander			*/
-#define I2C_ADDR_EEPROM		0x58	/* EEPROM AT24C164			*/
-
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif	/* __MACH_LWMON_H */
diff --git a/arch/ppc/platforms/mbx.h b/arch/ppc/platforms/mbx.h
deleted file mode 100644
index 1cf36fa3592..00000000000
--- a/arch/ppc/platforms/mbx.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * A collection of structures, addresses, and values associated with
- * the Motorola MBX boards.  This was originally created for the
- * MBX860, and probably needs revisions for other boards (like the 821).
- * When this file gets out of control, we can split it up into more
- * meaningful pieces.
- *
- * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
- */
-#ifdef __KERNEL__
-#ifndef __MACH_MBX_DEFS
-#define __MACH_MBX_DEFS
-
-#ifndef __ASSEMBLY__
-/* A Board Information structure that is given to a program when
- * EPPC-Bug starts it up.
- */
-typedef struct bd_info {
-	unsigned int	bi_tag;		/* Should be 0x42444944 "BDID" */
-	unsigned int	bi_size;	/* Size of this structure */
-	unsigned int	bi_revision;	/* revision of this structure */
-	unsigned int	bi_bdate;	/* EPPCbug date, i.e. 0x11061997 */
-	unsigned int	bi_memstart;	/* Memory start address */
-	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
-	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
-	unsigned int	bi_busfreq;	/* Bus Freq, in Hz */
-	unsigned int	bi_clun;	/* Boot device controller */
-	unsigned int	bi_dlun;	/* Boot device logical dev */
-
-	/* These fields are not part of the board information structure
-	 * provided by the boot rom.  They are filled in by embed_config.c
-	 * so we have the information consistent with other platforms.
-	 */
-	unsigned char	bi_enetaddr[6];
-	unsigned int	bi_baudrate;
-} bd_t;
-
-/* Memory map for the MBX as configured by EPPC-Bug.  We could reprogram
- * The SIU and PCI bridge, and try to use larger MMU pages, but the
- * performance gain is not measurable and it certainly complicates the
- * generic MMU model.
- *
- * In a effort to minimize memory usage for embedded applications, any
- * PCI driver or ISA driver must request or map the region required by
- * the device.  For convenience (and since we can map up to 4 Mbytes with
- * a single page table page), the MMU initialization will map the
- * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI
- * Bridge CSRs 1:1 into the kernel address space.
- */
-#define PCI_ISA_IO_ADDR		((unsigned)0x80000000)
-#define PCI_ISA_IO_SIZE		((uint)(512 * 1024 * 1024))
-#define PCI_IDE_ADDR		((unsigned)0x81000000)
-#define PCI_ISA_MEM_ADDR	((unsigned)0xc0000000)
-#define PCI_ISA_MEM_SIZE	((uint)(512 * 1024 * 1024))
-#define PCMCIA_MEM_ADDR		((uint)0xe0000000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024 * 1024))
-#define PCMCIA_DMA_ADDR		((uint)0xe4000000)
-#define PCMCIA_DMA_SIZE		((uint)(64 * 1024 * 1024))
-#define PCMCIA_ATTRB_ADDR	((uint)0xe8000000)
-#define PCMCIA_ATTRB_SIZE	((uint)(64 * 1024 * 1024))
-#define PCMCIA_IO_ADDR		((uint)0xec000000)
-#define PCMCIA_IO_SIZE		((uint)(64 * 1024 * 1024))
-#define NVRAM_ADDR		((uint)0xfa000000)
-#define NVRAM_SIZE		((uint)(1 * 1024 * 1024))
-#define MBX_CSR_ADDR		((uint)0xfa100000)
-#define MBX_CSR_SIZE		((uint)(1 * 1024 * 1024))
-#define IMAP_ADDR		((uint)0xfa200000)
-#define IMAP_SIZE		((uint)(64 * 1024))
-#define PCI_CSR_ADDR		((uint)0xfa210000)
-#define PCI_CSR_SIZE		((uint)(64 * 1024))
-
-/* Map additional physical space into well known virtual addresses.  Due
- * to virtual address mapping, these physical addresses are not accessible
- * in a 1:1 virtual to physical mapping.
- */
-#define ISA_IO_VIRT_ADDR	((uint)0xfa220000)
-#define ISA_IO_VIRT_SIZE	((uint)64 * 1024)
-
-/* Interrupt assignments.
- * These are defined (and fixed) by the MBX hardware implementation.
- */
-#define POWER_FAIL_INT	SIU_IRQ0	/* Power fail */
-#define TEMP_HILO_INT	SIU_IRQ1	/* Temperature sensor */
-#define QSPAN_INT	SIU_IRQ2	/* PCI Bridge (DMA CTLR?) */
-#define ISA_BRIDGE_INT	SIU_IRQ3	/* All those PC things */
-#define COMM_L_INT	SIU_IRQ6	/* MBX Comm expansion connector pin */
-#define STOP_ABRT_INT	SIU_IRQ7	/* Stop/Abort header pin */
-
-/* CPM Ethernet through SCCx.
- *
- * Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
- * to the MBX860 board.  Any two of the four available clocks could be
- * used, and the MPC860 cookbook manual has an example using different
- * clock pins.
- */
-#define PA_ENET_RXD	((ushort)0x0001)
-#define PA_ENET_TXD	((ushort)0x0002)
-#define PA_ENET_TCLK	((ushort)0x0200)
-#define PA_ENET_RCLK	((ushort)0x0800)
-#define PC_ENET_TENA	((ushort)0x0001)
-#define PC_ENET_CLSN	((ushort)0x0010)
-#define PC_ENET_RENA	((ushort)0x0020)
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK	((uint)0x000000ff)
-#define SICR_ENET_CLKRT	((uint)0x0000003d)
-
-/* The MBX uses the 8259.
-*/
-#define NR_8259_INTS	16
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __MACH_MBX_DEFS */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/mpc866ads_setup.c b/arch/ppc/platforms/mpc866ads_setup.c
deleted file mode 100644
index 62370f4a5a0..00000000000
--- a/arch/ppc/platforms/mpc866ads_setup.c
+++ /dev/null
@@ -1,413 +0,0 @@
-/*arch/ppc/platforms/mpc866ads_setup.c
- *
- * Platform setup for the Freescale mpc866ads board
- *
- * Vitaly Bordug <vbordug@ru.mvista.com>
- *
- * Copyright 2005-2006 MontaVista Software Inc.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/param.h>
-#include <linux/string.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-
-#include <linux/fs_enet_pd.h>
-#include <linux/fs_uart_pd.h>
-#include <linux/mii.h>
-#include <linux/phy.h>
-
-#include <asm/delay.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/page.h>
-#include <asm/processor.h>
-#include <asm/system.h>
-#include <asm/time.h>
-#include <asm/ppcboot.h>
-#include <asm/8xx_immap.h>
-#include <asm/cpm1.h>
-#include <asm/ppc_sys.h>
-#include <asm/mpc8xx.h>
-
-extern unsigned char __res[];
-
-static void setup_fec1_ioports(struct fs_platform_info*);
-static void setup_scc1_ioports(struct fs_platform_info*);
-static void setup_smc1_ioports(struct fs_uart_platform_info*);
-static void setup_smc2_ioports(struct fs_uart_platform_info*);
-
-static struct fs_mii_fec_platform_info	mpc8xx_mdio_fec_pdata;
-
-static struct fs_mii_fec_platform_info mpc8xx_mdio_fec_pdata;
-
-static struct fs_platform_info mpc8xx_enet_pdata[] = {
-	[fsid_fec1] = {
-		.rx_ring = 128,
-		.tx_ring = 16,
-		.rx_copybreak = 240,
-
-		.use_napi = 1,
-		.napi_weight = 17,
-
-		.init_ioports = setup_fec1_ioports,
-
-		.bus_id = "0:0f",
-		.has_phy = 1,
-	},
-	[fsid_scc1] = {
-		.rx_ring = 64,
-		.tx_ring = 8,
-		.rx_copybreak = 240,
-		.use_napi = 1,
-		.napi_weight = 17,
-
-
-		.init_ioports = setup_scc1_ioports,
-
-		.bus_id = "fixed@100:1",
-	},
-};
-
-static struct fs_uart_platform_info mpc866_uart_pdata[] = {
-	[fsid_smc1_uart] = {
-		.brg		= 1,
- 		.fs_no 		= fsid_smc1_uart,
- 		.init_ioports	= setup_smc1_ioports,
-		.tx_num_fifo	= 4,
-		.tx_buf_size	= 32,
-		.rx_num_fifo	= 4,
-		.rx_buf_size	= 32,
- 	},
- 	[fsid_smc2_uart] = {
- 		.brg		= 2,
- 		.fs_no 		= fsid_smc2_uart,
- 		.init_ioports	= setup_smc2_ioports,
-		.tx_num_fifo	= 4,
-		.tx_buf_size	= 32,
-		.rx_num_fifo	= 4,
-		.rx_buf_size	= 32,
- 	},
-};
-
-void __init board_init(void)
-{
-	volatile cpm8xx_t *cp = cpmp;
-	unsigned *bcsr_io;
-
-	bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
-
-	if (bcsr_io == NULL) {
-		printk(KERN_CRIT "Could not remap BCSR1\n");
-		return;
-	}
-
-#ifdef CONFIG_SERIAL_CPM_SMC1
-	cp->cp_simode &= ~(0xe0000000 >> 17);	/* brg1 */
-	clrbits32(bcsr_io,(0x80000000 >> 7));
-	cp->cp_smc[0].smc_smcm |= (SMCM_RX | SMCM_TX);
-	cp->cp_smc[0].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
-#else
-	setbits32(bcsr_io,(0x80000000 >> 7));
-
-	cp->cp_pbpar &= ~(0x000000c0);
-	cp->cp_pbdir |= 0x000000c0;
-	cp->cp_smc[0].smc_smcmr = 0;
-	cp->cp_smc[0].smc_smce = 0;
-#endif
-
-#ifdef CONFIG_SERIAL_CPM_SMC2
-	cp->cp_simode &= ~(0xe0000000 >> 1);
-	cp->cp_simode |= (0x20000000 >> 1);	/* brg2 */
-	clrbits32(bcsr_io,(0x80000000 >> 13));
-	cp->cp_smc[1].smc_smcm |= (SMCM_RX | SMCM_TX);
-	cp->cp_smc[1].smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
-#else
-	clrbits32(bcsr_io,(0x80000000 >> 13));
-	cp->cp_pbpar &= ~(0x00000c00);
-	cp->cp_pbdir |= 0x00000c00;
-	cp->cp_smc[1].smc_smcmr = 0;
-	cp->cp_smc[1].smc_smce = 0;
-#endif
-	iounmap(bcsr_io);
-}
-
-static void setup_fec1_ioports(struct fs_platform_info* pdata)
-{
-	immap_t *immap = (immap_t *) IMAP_ADDR;
-
-	setbits16(&immap->im_ioport.iop_pdpar, 0x1fff);
-	setbits16(&immap->im_ioport.iop_pddir, 0x1fff);
-}
-
-static void setup_scc1_ioports(struct fs_platform_info* pdata)
-{
-	immap_t *immap = (immap_t *) IMAP_ADDR;
-	unsigned *bcsr_io;
-
-	bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
-
-	if (bcsr_io == NULL) {
-		printk(KERN_CRIT "Could not remap BCSR1\n");
-		return;
-	}
-
-	/* Enable the PHY.
-	 */
-	clrbits32(bcsr_io,BCSR1_ETHEN);
-
-	/* Configure port A pins for Txd and Rxd.
-	 */
-	/* Disable receive and transmit in case EPPC-Bug started it.
-	 */
-	setbits16(&immap->im_ioport.iop_papar, PA_ENET_RXD | PA_ENET_TXD);
-	clrbits16(&immap->im_ioport.iop_padir, PA_ENET_RXD | PA_ENET_TXD);
-	clrbits16(&immap->im_ioport.iop_paodr, PA_ENET_TXD);
-
-	/* Configure port C pins to enable CLSN and RENA.
-	 */
-	clrbits16(&immap->im_ioport.iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
-	clrbits16(&immap->im_ioport.iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
-	setbits16(&immap->im_ioport.iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
-	/* Configure port A for TCLK and RCLK.
-	 */
-	setbits16(&immap->im_ioport.iop_papar, PA_ENET_TCLK | PA_ENET_RCLK);
-	clrbits16(&immap->im_ioport.iop_padir, PA_ENET_TCLK | PA_ENET_RCLK);
-	clrbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
-	clrbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
-
-	/* Configure Serial Interface clock routing.
-	 * First, clear all SCC bits to zero, then set the ones we want.
-	 */
-	clrbits32(&immap->im_cpm.cp_sicr, SICR_ENET_MASK);
-	setbits32(&immap->im_cpm.cp_sicr, SICR_ENET_CLKRT);
-
-	/* In the original SCC enet driver the following code is placed at
-	the end of the initialization */
-	setbits32(&immap->im_cpm.cp_pbpar, PB_ENET_TENA);
-	setbits32(&immap->im_cpm.cp_pbdir, PB_ENET_TENA);
-
-}
-
-static void setup_smc1_ioports(struct fs_uart_platform_info* pdata)
-{
-	immap_t *immap = (immap_t *) IMAP_ADDR;
-	unsigned *bcsr_io;
-	unsigned int iobits = 0x000000c0;
-
-	bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
-
-	if (bcsr_io == NULL) {
-		printk(KERN_CRIT "Could not remap BCSR1\n");
-		return;
-	}
-
-	clrbits32(bcsr_io,BCSR1_RS232EN_1);
-	iounmap(bcsr_io);
-
-	setbits32(&immap->im_cpm.cp_pbpar, iobits);
-	clrbits32(&immap->im_cpm.cp_pbdir, iobits);
-	clrbits16(&immap->im_cpm.cp_pbodr, iobits);
-
-}
-
-static void setup_smc2_ioports(struct fs_uart_platform_info* pdata)
-{
-	immap_t *immap = (immap_t *) IMAP_ADDR;
-	unsigned *bcsr_io;
-	unsigned int iobits = 0x00000c00;
-
-	bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
-
-	if (bcsr_io == NULL) {
-		printk(KERN_CRIT "Could not remap BCSR1\n");
-		return;
-	}
-
-	clrbits32(bcsr_io,BCSR1_RS232EN_2);
-
-	iounmap(bcsr_io);
-
-#ifndef CONFIG_SERIAL_CPM_ALT_SMC2
-	setbits32(&immap->im_cpm.cp_pbpar, iobits);
-	clrbits32(&immap->im_cpm.cp_pbdir, iobits);
-	clrbits16(&immap->im_cpm.cp_pbodr, iobits);
-#else
-	setbits16(&immap->im_ioport.iop_papar, iobits);
-	clrbits16(&immap->im_ioport.iop_padir, iobits);
-	clrbits16(&immap->im_ioport.iop_paodr, iobits);
-#endif
-
-}
-
-static int ma_count = 0;
-
-static void mpc866ads_fixup_enet_pdata(struct platform_device *pdev, int fs_no)
-{
-	struct fs_platform_info *fpi;
-
-	volatile cpm8xx_t *cp;
-	bd_t *bd = (bd_t *) __res;
-	char *e;
-	int i;
-
-	/* Get pointer to Communication Processor */
-	cp = cpmp;
-
-	if(fs_no >= ARRAY_SIZE(mpc8xx_enet_pdata)) {
-		printk(KERN_ERR"No network-suitable #%d device on bus", fs_no);
-		return;
-	}
-
-
-	fpi = &mpc8xx_enet_pdata[fs_no];
-	fpi->fs_no = fs_no;
-	pdev->dev.platform_data = fpi;
-
-	e = (unsigned char *)&bd->bi_enetaddr;
-	for (i = 0; i < 6; i++)
-		fpi->macaddr[i] = *e++;
-
-	fpi->macaddr[5] += ma_count++;
-}
-
-static void mpc866ads_fixup_fec_enet_pdata(struct platform_device *pdev,
-					   int idx)
-{
-	/* This is for FEC devices only */
-	if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-fec")))
-		return;
-	mpc866ads_fixup_enet_pdata(pdev, fsid_fec1 + pdev->id - 1);
-}
-
-static void mpc866ads_fixup_scc_enet_pdata(struct platform_device *pdev,
-					   int idx)
-{
-	/* This is for SCC devices only */
-	if (!pdev || !pdev->name || (!strstr(pdev->name, "fsl-cpm-scc")))
-		return;
-
-	mpc866ads_fixup_enet_pdata(pdev, fsid_scc1 + pdev->id - 1);
-}
-
-static void __init mpc866ads_fixup_uart_pdata(struct platform_device *pdev,
-                                              int idx)
-{
-	bd_t *bd = (bd_t *) __res;
-	struct fs_uart_platform_info *pinfo;
-	int num = ARRAY_SIZE(mpc866_uart_pdata);
-
-	int id = fs_uart_id_smc2fsid(idx);
-
-	/* no need to alter anything if console */
-	if ((id < num) && (!pdev->dev.platform_data)) {
-		pinfo = &mpc866_uart_pdata[id];
-		pinfo->uart_clk = bd->bi_intfreq;
-		pdev->dev.platform_data = pinfo;
-	}
-}
-
-static int mpc866ads_platform_notify(struct device *dev)
-{
-	static const struct platform_notify_dev_map dev_map[] = {
-		{
-			.bus_id = "fsl-cpm-fec",
-			.rtn = mpc866ads_fixup_fec_enet_pdata,
-		},
-		{
-			.bus_id = "fsl-cpm-scc",
-			.rtn = mpc866ads_fixup_scc_enet_pdata,
-		},
-		{
-			.bus_id = "fsl-cpm-smc:uart",
-			.rtn = mpc866ads_fixup_uart_pdata
-		},
-		{
-			.bus_id = NULL
-		}
-	};
-
-	platform_notify_map(dev_map,dev);
-
-	return 0;
-}
-
-int __init mpc866ads_init(void)
-{
-	bd_t *bd = (bd_t *) __res;
-	struct fs_mii_fec_platform_info* fmpi;
-
-	printk(KERN_NOTICE "mpc866ads: Init\n");
-
-	platform_notify = mpc866ads_platform_notify;
-
-	ppc_sys_device_initfunc();
-	ppc_sys_device_disable_all();
-
-#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC1
-	ppc_sys_device_enable(MPC8xx_CPM_SCC1);
-#endif
-	ppc_sys_device_enable(MPC8xx_CPM_FEC1);
-
-	ppc_sys_device_enable(MPC8xx_MDIO_FEC);
-
-	fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
-		&mpc8xx_mdio_fec_pdata;
-
-	fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
-	/* No PHY interrupt line here */
-	fmpi->irq[0xf] = PHY_POLL;
-
-/* Since either of the uarts could be used as console, they need to ready */
-#ifdef CONFIG_SERIAL_CPM_SMC1
-	ppc_sys_device_enable(MPC8xx_CPM_SMC1);
-	ppc_sys_device_setfunc(MPC8xx_CPM_SMC1, PPC_SYS_FUNC_UART);
-#endif
-
-#ifdef CONFIG_SERIAL_CPM_SMC2
-	ppc_sys_device_enable(MPC8xx_CPM_SMC2);
-	ppc_sys_device_setfunc(MPC8xx_CPM_SMC2, PPC_SYS_FUNC_UART);
-#endif
-	ppc_sys_device_enable(MPC8xx_MDIO_FEC);
-
-	fmpi = ppc_sys_platform_devices[MPC8xx_MDIO_FEC].dev.platform_data =
-		&mpc8xx_mdio_fec_pdata;
-
-	fmpi->mii_speed = ((((bd->bi_intfreq + 4999999) / 2500000) / 2) & 0x3F) << 1;
-	/* No PHY interrupt line here */
-	fmpi->irq[0xf] = PHY_POLL;
-
-	return 0;
-}
-
-/*
-   To prevent confusion, console selection is gross:
-   by 0 assumed SMC1 and by 1 assumed SMC2
- */
-struct platform_device* early_uart_get_pdev(int index)
-{
-	bd_t *bd = (bd_t *) __res;
-	struct fs_uart_platform_info *pinfo;
-
-	struct platform_device* pdev = NULL;
-	if(index) { /*assume SMC2 here*/
-		pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC2];
-		pinfo = &mpc866_uart_pdata[1];
-	} else { /*over SMC1*/
-		pdev = &ppc_sys_platform_devices[MPC8xx_CPM_SMC1];
-		pinfo = &mpc866_uart_pdata[0];
-	}
-
-	pinfo->uart_clk = bd->bi_intfreq;
-	pdev->dev.platform_data = pinfo;
-	ppc_sys_fixup_mem_resource(pdev, IMAP_ADDR);
-	return NULL;
-}
-
-arch_initcall(mpc866ads_init);
diff --git a/arch/ppc/platforms/mvme5100.c b/arch/ppc/platforms/mvme5100.c
deleted file mode 100644
index 053b54ac88f..00000000000
--- a/arch/ppc/platforms/mvme5100.c
+++ /dev/null
@@ -1,340 +0,0 @@
-/*
- * Board setup routines for the Motorola MVME5100.
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/pci.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/kdev_t.h>
-#include <linux/root_dev.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/open_pic.h>
-#include <asm/i8259.h>
-#include <asm/todc.h>
-#include <asm/pci-bridge.h>
-#include <asm/bootinfo.h>
-#include <asm/hawk.h>
-
-#include <platforms/pplus.h>
-#include <platforms/mvme5100.h>
-
-static u_char mvme5100_openpic_initsenses[16] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* i8259 cascade */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* TL16C550 UART 1,2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet1 front panel or P2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Hawk Watchdog 1,2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* DS1621 thermal alarm */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT0# */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT1# */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT2# */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Universe II LINT3# */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTA#, PMC2 INTB# */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTB#, PMC2 INTC# */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTC#, PMC2 INTD# */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* PMC1 INTD#, PMC2 INTA# */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Enet 2 (front panel) */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* Abort Switch */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* RTC Alarm */
-};
-
-static inline int
-mvme5100_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	int irq;
-
-	static char pci_irq_table[][4] =
-	/*
-	 *	PCI IDSEL/INTPIN->INTLINE
-	 * 	   A   B   C   D
-	 */
-	{
-		{  0,  0,  0,  0 },	/* IDSEL 11 - Winbond */
-		{  0,  0,  0,  0 },	/* IDSEL 12 - unused */
-		{ 21, 22, 23, 24 },	/* IDSEL 13 - Universe II */
-		{ 18,  0,  0,  0 },	/* IDSEL 14 - Enet 1 */
-		{  0,  0,  0,  0 },	/* IDSEL 15 - unused */
-		{ 25, 26, 27, 28 },	/* IDSEL 16 - PMC Slot 1 */
-		{ 28, 25, 26, 27 },	/* IDSEL 17 - PMC Slot 2 */
-		{  0,  0,  0,  0 },	/* IDSEL 18 - unused */
-		{ 29,  0,  0,  0 },	/* IDSEL 19 - Enet 2 */
-		{  0,  0,  0,  0 },	/* IDSEL 20 - PMCSPAN */
-	};
-
-	const long min_idsel = 11, max_idsel = 20, irqs_per_slot = 4;
-	irq = PCI_IRQ_TABLE_LOOKUP;
-	/* If lookup is zero, always return 0 */
-	if (!irq)
-		return 0;
-	else
-#ifdef CONFIG_MVME5100_IPMC761_PRESENT
-	/* If IPMC761 present, return table value */
-	return irq;
-#else
-	/* If IPMC761 not present, we don't have an i8259 so adjust */
-	return (irq - NUM_8259_INTERRUPTS);
-#endif
-}
-
-static void
-mvme5100_pcibios_fixup_resources(struct pci_dev *dev)
-{
-	int i;
-
-	if ((dev->vendor == PCI_VENDOR_ID_MOTOROLA) &&
-			(dev->device == PCI_DEVICE_ID_MOTOROLA_HAWK))
-		for (i=0; i<DEVICE_COUNT_RESOURCE; i++)
-		{
-			dev->resource[i].start = 0;
-			dev->resource[i].end = 0;
-		}
-}
-
-static void __init
-mvme5100_setup_bridge(void)
-{
-	struct pci_controller*	hose;
-
-	hose = pcibios_alloc_controller();
-
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-	hose->pci_mem_offset = MVME5100_PCI_MEM_OFFSET;
-
-	pci_init_resource(&hose->io_resource, MVME5100_PCI_LOWER_IO,
-			MVME5100_PCI_UPPER_IO, IORESOURCE_IO,
-			"PCI host bridge");
-
-	pci_init_resource(&hose->mem_resources[0], MVME5100_PCI_LOWER_MEM,
-			MVME5100_PCI_UPPER_MEM, IORESOURCE_MEM,
-			"PCI host bridge");
-
-	hose->io_space.start = MVME5100_PCI_LOWER_IO;
-	hose->io_space.end = MVME5100_PCI_UPPER_IO;
-	hose->mem_space.start = MVME5100_PCI_LOWER_MEM;
-	hose->mem_space.end = MVME5100_PCI_UPPER_MEM;
-	hose->io_base_virt = (void *)MVME5100_ISA_IO_BASE;
-
-	/* Use indirect method of Hawk */
-	setup_indirect_pci(hose, MVME5100_PCI_CONFIG_ADDR,
-			MVME5100_PCI_CONFIG_DATA);
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pcibios_fixup_resources = mvme5100_pcibios_fixup_resources;
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = mvme5100_map_irq;
-}
-
-static void __init
-mvme5100_setup_arch(void)
-{
-	if ( ppc_md.progress )
-		ppc_md.progress("mvme5100_setup_arch: enter", 0);
-
-	loops_per_jiffy = 50000000 / HZ;
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef	CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	if ( ppc_md.progress )
-		ppc_md.progress("mvme5100_setup_arch: find_bridges", 0);
-
-	/* Setup PCI host bridge */
-	mvme5100_setup_bridge();
-
-	/* Find and map our OpenPIC */
-	hawk_mpic_init(MVME5100_PCI_MEM_OFFSET);
-	OpenPIC_InitSenses = mvme5100_openpic_initsenses;
-	OpenPIC_NumInitSenses = sizeof(mvme5100_openpic_initsenses);
-
-	printk("MVME5100 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
-
-	if ( ppc_md.progress )
-		ppc_md.progress("mvme5100_setup_arch: exit", 0);
-
-	return;
-}
-
-static void __init
-mvme5100_init2(void)
-{
-#ifdef CONFIG_MVME5100_IPMC761_PRESENT
-		request_region(0x00,0x20,"dma1");
-		request_region(0x20,0x20,"pic1");
-		request_region(0x40,0x20,"timer");
-		request_region(0x80,0x10,"dma page reg");
-		request_region(0xa0,0x20,"pic2");
-		request_region(0xc0,0x20,"dma2");
-#endif
-	return;
-}
-
-/*
- * Interrupt setup and service.
- * Have MPIC on HAWK and cascaded 8259s on Winbond cascaded to MPIC.
- */
-static void __init
-mvme5100_init_IRQ(void)
-{
-#ifdef CONFIG_MVME5100_IPMC761_PRESENT
-	int i;
-#endif
-
-	if ( ppc_md.progress )
-		ppc_md.progress("init_irq: enter", 0);
-
-	openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
-#ifdef CONFIG_MVME5100_IPMC761_PRESENT
-	openpic_init(NUM_8259_INTERRUPTS);
-	openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
-			&i8259_irq);
-
-	i8259_init(0, 0);
-#else
-	openpic_init(0);
-#endif
-
-	if ( ppc_md.progress )
-		ppc_md.progress("init_irq: exit", 0);
-
-	return;
-}
-
-/*
- * Set BAT 3 to map 0xf0000000 to end of physical memory space.
- */
-static __inline__ void
-mvme5100_set_bat(void)
-{
-	mb();
-	mtspr(SPRN_DBAT1U, 0xf0001ffe);
-	mtspr(SPRN_DBAT1L, 0xf000002a);
-	mb();
-}
-
-static unsigned long __init
-mvme5100_find_end_of_memory(void)
-{
-	return hawk_get_mem_size(MVME5100_HAWK_SMC_BASE);
-}
-
-static void __init
-mvme5100_map_io(void)
-{
-	io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
-	ioremap_base = 0xfe000000;
-}
-
-static void
-mvme5100_reset_board(void)
-{
-	local_irq_disable();
-
-	/* Set exception prefix high - to the firmware */
-	_nmask_and_or_msr(0, MSR_IP);
-
-	out_8((u_char *)MVME5100_BOARD_MODRST_REG, 0x01);
-
-	return;
-}
-
-static void
-mvme5100_restart(char *cmd)
-{
-	volatile ulong i = 10000000;
-
-	mvme5100_reset_board();
-
-	while (i-- > 0);
-	panic("restart failed\n");
-}
-
-static void
-mvme5100_halt(void)
-{
-	local_irq_disable();
-	while (1);
-}
-
-static void
-mvme5100_power_off(void)
-{
-	mvme5100_halt();
-}
-
-static int
-mvme5100_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: Motorola\n");
-	seq_printf(m, "machine\t\t: MVME5100\n");
-
-	return 0;
-}
-
-TODC_ALLOC();
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-	mvme5100_set_bat();
-
-	isa_io_base = MVME5100_ISA_IO_BASE;
-	isa_mem_base = MVME5100_ISA_MEM_BASE;
-	pci_dram_offset = MVME5100_PCI_DRAM_OFFSET;
-
-	ppc_md.setup_arch = mvme5100_setup_arch;
-	ppc_md.show_cpuinfo = mvme5100_show_cpuinfo;
-	ppc_md.init_IRQ = mvme5100_init_IRQ;
-	ppc_md.get_irq = openpic_get_irq;
-	ppc_md.init = mvme5100_init2;
-
-	ppc_md.restart = mvme5100_restart;
-	ppc_md.power_off = mvme5100_power_off;
-	ppc_md.halt = mvme5100_halt;
-
-	ppc_md.find_end_of_memory = mvme5100_find_end_of_memory;
-	ppc_md.setup_io_mappings = mvme5100_map_io;
-
-	TODC_INIT(TODC_TYPE_MK48T37, MVME5100_NVRAM_AS0, MVME5100_NVRAM_AS1,
-			MVME5100_NVRAM_DATA, 8);
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.calibrate_decr = todc_calibrate_decr;
-
-	ppc_md.nvram_read_val = todc_m48txx_read_val;
-	ppc_md.nvram_write_val = todc_m48txx_write_val;
-}
diff --git a/arch/ppc/platforms/mvme5100.h b/arch/ppc/platforms/mvme5100.h
deleted file mode 100644
index fbb5495165c..00000000000
--- a/arch/ppc/platforms/mvme5100.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * arch/ppc/platforms/mvme5100.h
- *
- * Definitions for Motorola MVME5100.
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_MVME5100_H__
-#define __ASM_MVME5100_H__
-
-#define MVME5100_HAWK_SMC_BASE		0xfef80000
-
-#define	MVME5100_PCI_CONFIG_ADDR	0xfe000cf8
-#define	MVME5100_PCI_CONFIG_DATA	0xfe000cfc
-
-#define MVME5100_PCI_IO_BASE		0xfe000000
-#define MVME5100_PCI_MEM_BASE		0x80000000
-
-#define MVME5100_PCI_MEM_OFFSET		0x00000000
-
-#define MVME5100_PCI_DRAM_OFFSET	0x00000000
-#define MVME5100_ISA_MEM_BASE		0x00000000
-#define MVME5100_ISA_IO_BASE		MVME5100_PCI_IO_BASE
-
-#define MVME5100_PCI_LOWER_MEM		0x80000000
-#define MVME5100_PCI_UPPER_MEM		0xf3f7ffff
-#define MVME5100_PCI_LOWER_IO		0x00000000
-#define MVME5100_PCI_UPPER_IO		0x0077ffff
-
-/* MVME5100 board register addresses. */
-#define	MVME5100_BOARD_STATUS_REG	0xfef88080
-#define	MVME5100_BOARD_MODFAIL_REG	0xfef88090
-#define	MVME5100_BOARD_MODRST_REG	0xfef880a0
-#define	MVME5100_BOARD_TBEN_REG		0xfef880c0
-#define MVME5100_BOARD_SW_READ_REG	0xfef880e0
-#define	MVME5100_BOARD_GEO_ADDR_REG	0xfef880e8
-#define	MVME5100_BOARD_EXT_FEATURE1_REG	0xfef880f0
-#define	MVME5100_BOARD_EXT_FEATURE2_REG	0xfef88100
-
-/* Define the NVRAM/RTC address strobe & data registers */
-#define MVME5100_PHYS_NVRAM_AS0		0xfef880c8
-#define MVME5100_PHYS_NVRAM_AS1		0xfef880d0
-#define MVME5100_PHYS_NVRAM_DATA	0xfef880d8
-
-#define MVME5100_NVRAM_AS0	(MVME5100_PHYS_NVRAM_AS0 - MVME5100_ISA_IO_BASE)
-#define MVME5100_NVRAM_AS1	(MVME5100_PHYS_NVRAM_AS1 - MVME5100_ISA_IO_BASE)
-#define MVME5100_NVRAM_DATA	(MVME5100_PHYS_NVRAM_DATA - MVME5100_ISA_IO_BASE)
-
-/* UART clock, addresses, and irq */
-#define MVME5100_BASE_BAUD		1843200
-#define	MVME5100_SERIAL_1		0xfef88000
-#define	MVME5100_SERIAL_2		0xfef88200
-#ifdef CONFIG_MVME5100_IPMC761_PRESENT
-#define MVME5100_SERIAL_IRQ		17
-#else
-#define MVME5100_SERIAL_IRQ		1
-#endif
-
-#define RS_TABLE_SIZE  4
-
-#define BASE_BAUD ( MVME5100_BASE_BAUD / 16 )
-
-#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
-
-/* All UART IRQs are wire-OR'd to one MPIC IRQ */
-#define STD_SERIAL_PORT_DFNS \
-        { 0, BASE_BAUD, MVME5100_SERIAL_1, \
-		MVME5100_SERIAL_IRQ, \
-		STD_COM_FLAGS, /* ttyS0 */ \
-		iomem_base: (unsigned char *)MVME5100_SERIAL_1,		\
-		iomem_reg_shift: 4,					\
-		io_type: SERIAL_IO_MEM },				\
-        { 0, BASE_BAUD, MVME5100_SERIAL_2, \
-		MVME5100_SERIAL_IRQ, \
-		STD_COM_FLAGS, /* ttyS1 */ \
-		iomem_base: (unsigned char *)MVME5100_SERIAL_2,		\
-		iomem_reg_shift: 4,					\
-		io_type: SERIAL_IO_MEM },
-
-#define SERIAL_PORT_DFNS \
-        STD_SERIAL_PORT_DFNS
-
-#endif /* __ASM_MVME5100_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/pal4.h b/arch/ppc/platforms/pal4.h
deleted file mode 100644
index 8569c423d88..00000000000
--- a/arch/ppc/platforms/pal4.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Definitions for SBS Palomar IV board
- *
- * Author: Dan Cox
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PPC_PLATFORMS_PAL4_H
-#define __PPC_PLATFORMS_PAL4_H
-
-#define PAL4_NVRAM             0xfffc0000
-#define PAL4_NVRAM_SIZE        0x8000
-
-#define PAL4_DRAM              0xfff80000
-#define  PAL4_DRAM_BR_MASK     0xc0
-#define  PAL4_DRAM_BR_SHIFT    6
-#define  PAL4_DRAM_RESET       0x10
-#define  PAL4_DRAM_EREADY      0x40
-
-#define PAL4_MISC              0xfff80004
-#define  PAL4_MISC_FB_MASK     0xc0
-#define  PAL4_MISC_FLASH       0x20  /* StratFlash mapping: 1->0xff80, 0->0xfff0 */
-#define  PAL4_MISC_MISC        0x08
-#define  PAL4_MISC_BITF        0x02
-#define  PAL4_MISC_NVKS        0x01
-
-#define PAL4_L2                0xfff80008
-#define  PAL4_L2_MASK          0x07
-
-#define PAL4_PLDR              0xfff8000c
-
-/* Only two Ethernet devices on the board... */
-#define PAL4_ETH               31
-#define PAL4_INTA              20
-
-#endif /* __PPC_PLATFORMS_PAL4_H */
diff --git a/arch/ppc/platforms/pal4_pci.c b/arch/ppc/platforms/pal4_pci.c
deleted file mode 100644
index d81ae1c7e1c..00000000000
--- a/arch/ppc/platforms/pal4_pci.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * PCI support for SBS Palomar IV
- *
- * Author: Dan Cox
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/byteorder.h>
-#include <asm/machdep.h>
-#include <asm/io.h>
-#include <asm/pci-bridge.h>
-#include <asm/uaccess.h>
-
-#include <syslib/cpc700.h>
-
-#include "pal4.h"
-
-/* not much to this.... */
-static inline int __init
-pal4_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	if (idsel == 9)
-		return PAL4_ETH;
-	else
-		return PAL4_INTA + (idsel - 3);
-}
-
-void __init
-pal4_find_bridges(void)
-{
-	struct pci_controller *hose;
-
-	hose = pcibios_alloc_controller();
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-	hose->pci_mem_offset = 0;
-
-	/* Could snatch these from the CPC700.... */
-	pci_init_resource(&hose->io_resource,
-			  0x0,
-			  0x03ffffff,
-			  IORESOURCE_IO,
-			  "PCI host bridge");
-
-	pci_init_resource(&hose->mem_resources[0],
-			  0x90000000,
-			  0x9fffffff,
-			  IORESOURCE_MEM,
-			  "PCI host bridge");
-
-	hose->io_space.start = 0x00800000;
-	hose->io_space.end = 0x03ffffff;
-	hose->mem_space.start = 0x90000000;
-	hose->mem_space.end = 0x9fffffff;
-	hose->io_base_virt = (void *) 0xf8000000;
-
-	setup_indirect_pci(hose, CPC700_PCI_CONFIG_ADDR,
-			   CPC700_PCI_CONFIG_DATA);
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = pal4_map_irq;
-}
diff --git a/arch/ppc/platforms/pal4_serial.h b/arch/ppc/platforms/pal4_serial.h
deleted file mode 100644
index a75343224cf..00000000000
--- a/arch/ppc/platforms/pal4_serial.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Definitions for SBS PalomarIV serial support
- *
- * Author: Dan Cox
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PPC_PAL4_SERIAL_H
-#define __PPC_PAL4_SERIAL_H
-
-#define CPC700_SERIAL_1       0xff600300
-#define CPC700_SERIAL_2       0xff600400
-
-#define RS_TABLE_SIZE     2
-#define BASE_BAUD         (33333333 / 4 / 16)
-
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF)
-#endif
-
-#define SERIAL_PORT_DFNS \
-      {0, BASE_BAUD, CPC700_SERIAL_1, 3, STD_COM_FLAGS, \
-       iomem_base: (unsigned char *) CPC700_SERIAL_1, \
-       io_type: SERIAL_IO_MEM},   /* ttyS0 */ \
-      {0, BASE_BAUD, CPC700_SERIAL_2, 4, STD_COM_FLAGS, \
-       iomem_base: (unsigned char *) CPC700_SERIAL_2, \
-       io_type: SERIAL_IO_MEM}
-
-#endif
diff --git a/arch/ppc/platforms/pal4_setup.c b/arch/ppc/platforms/pal4_setup.c
deleted file mode 100644
index 3da47d9ec7a..00000000000
--- a/arch/ppc/platforms/pal4_setup.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Board setup routines for the SBS PalomarIV.
- *
- * Author: Dan Cox
- *
- * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/time.h>
-#include <linux/irq.h>
-#include <linux/kdev_t.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-
-#include <asm/io.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/machdep.h>
-
-#include <syslib/cpc700.h>
-
-#include "pal4.h"
-
-extern void pal4_find_bridges(void);
-
-unsigned int cpc700_irq_assigns[][2] = {
-        {1, 1},    /* IRQ 0: ECC correctable error */
-        {1, 1},    /* IRQ 1: PCI write to memory range */
-        {0, 1},    /* IRQ 2: PCI write to command register */
-        {0, 1},    /* IRQ 3: UART 0 */
-        {0, 1},    /* IRQ 4: UART 1 */
-        {0, 1},    /* IRQ 5: ICC 0 */
-        {0, 1},    /* IRQ 6: ICC 1 */
-        {0, 1},    /* IRQ 7: GPT compare 0 */
-        {0, 1},    /* IRQ 8: GPT compare 1 */
-        {0, 1},    /* IRQ 9: GPT compare 2 */
-        {0, 1},    /* IRQ 10: GPT compare 3 */
-        {0, 1},    /* IRQ 11: GPT compare 4 */
-        {0, 1},    /* IRQ 12: GPT capture 0 */
-        {0, 1},    /* IRQ 13: GPT capture 1 */
-        {0, 1},    /* IRQ 14: GPT capture 2 */
-        {0, 1},    /* IRQ 15: GPT capture 3 */
-        {0, 1},    /* IRQ 16: GPT capture 4 */
-        {0, 0},    /* IRQ 17: reserved */
-        {0, 0},    /* IRQ 18: reserved */
-        {0, 0},    /* IRQ 19: reserved */
-        {0, 0},    /* IRQ 20: reserved */
-        {0, 1},    /* IRQ 21: Ethernet */
-        {0, 0},    /* IRQ 22: reserved */
-        {0, 0},    /* IRQ 23: reserved */
-        {0, 0},    /* IRQ 24: resreved */
-        {0, 0},    /* IRQ 25: reserved */
-        {0, 0},    /* IRQ 26: reserved */
-        {0, 0},    /* IRQ 27: reserved */
-        {0, 0},    /* IRQ 28: reserved */
-        {0, 0},    /* IRQ 29: reserved */
-        {0, 0},    /* IRQ 30: reserved */
-        {0, 0},    /* IRQ 31: reserved */
-};
-
-static int
-pal4_show_cpuinfo(struct seq_file *m)
-{
-        seq_printf(m, "board\t\t: SBS Palomar IV\n");
-
-        return 0;
-}
-
-static void
-pal4_restart(char *cmd)
-{
-        local_irq_disable();
-        __asm__ __volatile__("lis  3,0xfff0\n \
-                              ori  3,3,0x100\n \
-                              mtspr 26,3\n \
-                              li   3,0\n \
-                              mtspr 27,3\n \
-                              rfi");
-
-        for(;;);
-}
-
-static void
-pal4_power_off(void)
-{
-	local_irq_disable();
-	for(;;);
-}
-
-static void
-pal4_halt(void)
-{
-	pal4_power_off();
-}
-
-TODC_ALLOC();
-
-static void __init
-pal4_setup_arch(void)
-{
-	unsigned long l2;
-
-	TODC_INIT(TODC_TYPE_MK48T37, 0, 0,
-		  ioremap(PAL4_NVRAM, PAL4_NVRAM_SIZE), 8);
-
-	pal4_find_bridges();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-		ROOT_DEV = Root_NFS;
-
-	/* The L2 gets disabled in the bootloader, but all the proper
-	   bits should be present from the fw, so just re-enable it */
-	l2 = _get_L2CR();
-	if (!(l2 & L2CR_L2E)) {
-		/* presume that it was initially set if the size is
-		   still present. */
-		if (l2 ^ L2CR_L2SIZ_MASK)
-			_set_L2CR(l2 | L2CR_L2E);
-		else
-			printk("L2 not set by firmware; left disabled.\n");
-	}
-}
-
-static void __init
-pal4_map_io(void)
-{
-	io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	isa_io_base = 0 /*PAL4_ISA_IO_BASE*/;
-	pci_dram_offset = 0 /*PAL4_PCI_SYS_MEM_BASE*/;
-
-	ppc_md.setup_arch = pal4_setup_arch;
-	ppc_md.show_cpuinfo = pal4_show_cpuinfo;
-
-	ppc_md.setup_io_mappings = pal4_map_io;
-
-	ppc_md.init_IRQ = cpc700_init_IRQ;
-	ppc_md.get_irq = cpc700_get_irq;
-
-	ppc_md.restart = pal4_restart;
-	ppc_md.halt = pal4_halt;
-	ppc_md.power_off = pal4_power_off;
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.calibrate_decr = todc_calibrate_decr;
-
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-}
-
diff --git a/arch/ppc/platforms/pcu_e.h b/arch/ppc/platforms/pcu_e.h
deleted file mode 100644
index a2c03a22875..00000000000
--- a/arch/ppc/platforms/pcu_e.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Siemens PCU E board specific definitions
- *
- * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
- */
-
-#ifndef __MACH_PCU_E_H
-#define __MACH_PCU_E_H
-
-
-#include <asm/ppcboot.h>
-
-#define	PCU_E_IMMR_BASE    0xFE000000	/* phys. addr of IMMR			*/
-#define	PCU_E_IMAP_SIZE   (64 * 1024)	/* size of mapped area			*/
-
-#define	IMAP_ADDR     PCU_E_IMMR_BASE	/* physical base address of IMMR area	*/
-#define IMAP_SIZE     PCU_E_IMAP_SIZE	/* mapped size of IMMR area		*/
-
-#define	FEC_INTERRUPT	15		/* = SIU_LEVEL7				*/
-#define	DEC_INTERRUPT	13		/* = SIU_LEVEL6				*/
-#define	CPM_INTERRUPT	11		/* = SIU_LEVEL5 (was: SIU_LEVEL2)	*/
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif	/* __MACH_PCU_E_H */
diff --git a/arch/ppc/platforms/powerpmc250.c b/arch/ppc/platforms/powerpmc250.c
deleted file mode 100644
index 162dc85ff7b..00000000000
--- a/arch/ppc/platforms/powerpmc250.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Board setup routines for Force PowerPMC-250 Processor PMC
- *
- * Author: Troy Benjegerdes <tbenjegerdes@mvista.com>
- * Borrowed heavily from prpmc750_*.c by
- * 	Matt Porter <mporter@mvista.com>
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/slab.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-
-#include <asm/byteorder.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/machdep.h>
-#include <asm/time.h>
-#include <platforms/powerpmc250.h>
-#include <asm/open_pic.h>
-#include <asm/pci-bridge.h>
-#include <asm/mpc10x.h>
-#include <asm/uaccess.h>
-#include <asm/bootinfo.h>
-
-extern void powerpmc250_find_bridges(void);
-extern unsigned long loops_per_jiffy;
-
-static u_char powerpmc250_openpic_initsenses[] __initdata =
-{
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    1,	/* PMC INTA (also MPC107 output interrupt INTA) */
-    1,	/* PMC INTB (also I82559 Ethernet controller) */
-    1,	/* PMC INTC */
-    1,	/* PMC INTD */
-    0,	/* DUART interrupt (active high) */
-};
-
-static int
-powerpmc250_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m,"machine\t\t: Force PowerPMC250\n");
-
-	return 0;
-}
-
-static void __init
-powerpmc250_setup_arch(void)
-{
-	/* init to some ~sane value until calibrate_delay() runs */
-	loops_per_jiffy = 50000000/HZ;
-
-	/* Lookup PCI host bridges */
-	powerpmc250_find_bridges();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	printk("Force PowerPMC250 port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
-}
-
-#if 0
-/*
- * Compute the PrPMC750's bus speed using the baud clock as a
- * reference.
- */
-unsigned long __init powerpmc250_get_bus_speed(void)
-{
-	unsigned long tbl_start, tbl_end;
-	unsigned long current_state, old_state, bus_speed;
-	unsigned char lcr, dll, dlm;
-	int baud_divisor, count;
-
-	/* Read the UART's baud clock divisor */
-	lcr = readb(PRPMC750_SERIAL_0_LCR);
-	writeb(lcr | UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
-	dll = readb(PRPMC750_SERIAL_0_DLL);
-	dlm = readb(PRPMC750_SERIAL_0_DLM);
-	writeb(lcr & ~UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
-	baud_divisor = (dlm << 8) | dll;
-
-	/*
-	 * Use the baud clock divisor and base baud clock
-	 * to determine the baud rate and use that as
-	 * the number of baud clock edges we use for
-	 * the time base sample.  Make it half the baud
-	 * rate.
-	 */
-	count = PRPMC750_BASE_BAUD / (baud_divisor * 16);
-
-	/* Find the first edge of the baud clock */
-	old_state = readb(PRPMC750_STATUS_REG) & PRPMC750_BAUDOUT_MASK;
-	do {
-		current_state = readb(PRPMC750_STATUS_REG) &
-			PRPMC750_BAUDOUT_MASK;
-	} while(old_state == current_state);
-
-	old_state = current_state;
-
-	/* Get the starting time base value */
-	tbl_start = get_tbl();
-
-	/*
-	 * Loop until we have found a number of edges equal
-	 * to half the count (half the baud rate)
-	 */
-	do {
-		do {
-			current_state = readb(PRPMC750_STATUS_REG) &
-				PRPMC750_BAUDOUT_MASK;
-		} while(old_state == current_state);
-		old_state = current_state;
-	} while (--count);
-
-	/* Get the ending time base value */
-	tbl_end = get_tbl();
-
-	/* Compute bus speed */
-	bus_speed = (tbl_end-tbl_start)*128;
-
-	return bus_speed;
-}
-#endif
-
-static void __init
-powerpmc250_calibrate_decr(void)
-{
-	unsigned long freq;
-	int divisor = 4;
-
-	//freq = powerpmc250_get_bus_speed();
-#warning hardcoded bus freq
-	freq = 100000000;
-
-	tb_ticks_per_jiffy = freq / (HZ * divisor);
-	tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
-}
-
-static void
-powerpmc250_restart(char *cmd)
-{
-	local_irq_disable();
-	/* Hard reset */
-	writeb(0x11, 0xfe000332);
-	while(1);
-}
-
-static void
-powerpmc250_halt(void)
-{
-	local_irq_disable();
-	while (1);
-}
-
-static void
-powerpmc250_power_off(void)
-{
-	powerpmc250_halt();
-}
-
-static void __init
-powerpmc250_init_IRQ(void)
-{
-
-	OpenPIC_InitSenses = powerpmc250_openpic_initsenses;
-	OpenPIC_NumInitSenses = sizeof(powerpmc250_openpic_initsenses);
-	mpc10x_set_openpic();
-}
-
-/*
- * Set BAT 3 to map 0xf0000000 to end of physical memory space.
- */
-static __inline__ void
-powerpmc250_set_bat(void)
-{
-	unsigned long   bat3u, bat3l;
-	static int	mapping_set = 0;
-
-	if (!mapping_set)
-	{
-		__asm__ __volatile__(
-				" lis %0,0xf000\n \
-				ori %1,%0,0x002a\n \
-				ori %0,%0,0x1ffe\n \
-				mtspr 0x21e,%0\n \
-				mtspr 0x21f,%1\n \
-				isync\n \
-				sync "
-				: "=r" (bat3u), "=r" (bat3l));
-
-		mapping_set = 1;
-	}
-	return;
-}
-
-static unsigned long __init
-powerpmc250_find_end_of_memory(void)
-{
-	/* Cover I/O space with a BAT */
-	/* yuck, better hope your ram size is a power of 2  -- paulus */
-	powerpmc250_set_bat();
-
-	return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
-}
-
-static void __init
-powerpmc250_map_io(void)
-{
-	io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if ( r4 )
-	{
-		initrd_start = r4 + KERNELBASE;
-		initrd_end = r5 + KERNELBASE;
-	}
-#endif
-
-	/* Copy cmd_line parameters */
-	if ( r6)
-	{
-		*(char *)(r7 + KERNELBASE) = 0;
-		strcpy(cmd_line, (char *)(r6 + KERNELBASE));
-	}
-
-	isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
-	isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
-	pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
-
-	ppc_md.setup_arch	= powerpmc250_setup_arch;
-	ppc_md.show_cpuinfo	= powerpmc250_show_cpuinfo;
-	ppc_md.init_IRQ		= powerpmc250_init_IRQ;
-	ppc_md.get_irq		= openpic_get_irq;
-
-	ppc_md.find_end_of_memory = powerpmc250_find_end_of_memory;
-	ppc_md.setup_io_mappings = powerpmc250_map_io;
-
-	ppc_md.restart		= powerpmc250_restart;
-	ppc_md.power_off	= powerpmc250_power_off;
-	ppc_md.halt		= powerpmc250_halt;
-
-	/* PowerPMC250 has no timekeeper part */
-	ppc_md.time_init	= NULL;
-	ppc_md.get_rtc_time	= NULL;
-	ppc_md.set_rtc_time	= NULL;
-	ppc_md.calibrate_decr	= powerpmc250_calibrate_decr;
-}
-
-
-/*
- * (This used to be arch/ppc/platforms/powerpmc250_pci.c)
- *
- * PCI support for Force PowerPMC250
- *
- */
-
-#undef DEBUG
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif /* DEBUG */
-
-static inline int __init
-powerpmc250_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *      PCI IDSEL/INTPIN->INTLINE
-	 *      A       B       C       D
-	 */
-	{
-		{17,	0,	0,	0},	/* Device 11 - 82559 */
-		{0,	0,	0,	0},	/* 12 */
-		{0,	0,	0,	0},	/* 13 */
-		{0,	0,	0,	0},	/* 14 */
-		{0,	0,	0,	0},	/* 15 */
-		{16,	17,	18,	19},	/* Device 16 - PMC A1?? */
-		};
-	const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-};
-
-static int
-powerpmc250_exclude_device(u_char bus, u_char devfn)
-{
-	/*
-	 * While doing PCI Scan  the MPC107 will 'detect' itself as
-	 * device on the PCI Bus, will create an incorrect response and
-	 * later will respond incorrectly to Configuration read coming
-	 * from another device.
-	 *
-	 * The work around is that when doing a PCI Scan one
-	 * should skip its own device number in the scan.
-	 *
-	 * The top IDsel is AD13 and the middle is AD14.
-	 *
-	 * -- Note from force
-	 */
-
-	if ((bus == 0) && (PCI_SLOT(devfn) == 13 || PCI_SLOT(devfn) == 14)) {
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	}
-	else {
-		return PCIBIOS_SUCCESSFUL;
-	}
-}
-
-void __init
-powerpmc250_find_bridges(void)
-{
-	struct pci_controller* hose;
-
-	hose = pcibios_alloc_controller();
-	if (!hose){
-		printk("Can't allocate PCI 'hose' structure!!!\n");
-		return;
-	}
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	if (mpc10x_bridge_init(hose,
-			MPC10X_MEM_MAP_B,
-			MPC10X_MEM_MAP_B,
-			MPC10X_MAPB_EUMB_BASE) == 0) {
-
-		hose->mem_resources[0].end = 0xffffffff;
-
-		hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-		/* ppc_md.pcibios_fixup = pcore_pcibios_fixup; */
-		ppc_md.pci_swizzle = common_swizzle;
-
-		ppc_md.pci_exclude_device = powerpmc250_exclude_device;
-		ppc_md.pci_map_irq = powerpmc250_map_irq;
-	} else {
-		if (ppc_md.progress)
-			ppc_md.progress("Bridge init failed", 0x100);
-		printk("Host bridge init failed\n");
-	}
-
-}
diff --git a/arch/ppc/platforms/powerpmc250.h b/arch/ppc/platforms/powerpmc250.h
deleted file mode 100644
index d33ad8dc043..00000000000
--- a/arch/ppc/platforms/powerpmc250.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * arch/ppc/platforms/powerpmc250.h
- *
- * Definitions for Force PowerPMC-250 board support
- *
- * Author: Troy Benjegerdes <tbenjegerdes@mvista.com>
- *
- * Borrowed heavily from prpmc750.h by Matt Porter <mporter@mvista.com>
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASMPPC_POWERPMC250_H
-#define __ASMPPC_POWERPMC250_H
-
-#define POWERPMC250_PCI_CONFIG_ADDR	0x80000cf8
-#define POWERPMC250_PCI_CONFIG_DATA	0x80000cfc
-
-#define POWERPMC250_PCI_PHY_MEM_BASE	0xc0000000
-#define POWERPMC250_PCI_MEM_BASE		0xf0000000
-#define POWERPMC250_PCI_IO_BASE		0x80000000
-
-#define POWERPMC250_ISA_IO_BASE		POWERPMC250_PCI_IO_BASE
-#define POWERPMC250_ISA_MEM_BASE		POWERPMC250_PCI_MEM_BASE
-#define POWERPMC250_PCI_MEM_OFFSET		POWERPMC250_PCI_PHY_MEM_BASE
-
-#define POWERPMC250_SYS_MEM_BASE		0x80000000
-
-#define POWERPMC250_HAWK_SMC_BASE		0xfef80000
-
-#define POWERPMC250_BASE_BAUD		12288000
-#define POWERPMC250_SERIAL		0xff000000
-#define POWERPMC250_SERIAL_IRQ		20
-
-/* UART Defines. */
-#define RS_TABLE_SIZE  1
-
-#define BASE_BAUD  (POWERPMC250_BASE_BAUD / 16)
-
-#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
-
-#define SERIAL_PORT_DFNS \
-	{ 0, BASE_BAUD, POWERPMC250_SERIAL, POWERPMC250_SERIAL_IRQ,	\
-		STD_COM_FLAGS, 				/* ttyS0 */	\
-		iomem_base: (u8 *)POWERPMC250_SERIAL,			\
-		iomem_reg_shift: 0,					\
-		io_type: SERIAL_IO_MEM }
-
-#endif /* __ASMPPC_POWERPMC250_H */
diff --git a/arch/ppc/platforms/pplus.c b/arch/ppc/platforms/pplus.c
deleted file mode 100644
index cbcac85c7a7..00000000000
--- a/arch/ppc/platforms/pplus.c
+++ /dev/null
@@ -1,844 +0,0 @@
-/*
- * Board and PCI setup routines for MCG PowerPlus
- *
- * Author: Randy Vinson <rvinson@mvista.com>
- *
- * Derived from original PowerPlus PReP work by
- * Cort Dougan, Johnnie Peters, Matt Porter, and
- * Troy Benjegerdes.
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/console.h>
-#include <linux/pci.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/dma.h>
-#include <asm/machdep.h>
-#include <asm/prep_nvram.h>
-#include <asm/vga.h>
-#include <asm/i8259.h>
-#include <asm/open_pic.h>
-#include <asm/hawk.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/kgdb.h>
-#include <asm/reg.h>
-
-#include "pplus.h"
-
-#undef DUMP_DBATS
-
-TODC_ALLOC();
-
-extern void pplus_setup_hose(void);
-extern void pplus_set_VIA_IDE_native(void);
-
-extern unsigned long loops_per_jiffy;
-unsigned char *Motherboard_map_name;
-
-/* Tables for known hardware */
-
-/* Motorola Mesquite */
-static inline int
-mesquite_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	    /*
-	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
-	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *         A   B   C   D
-	     */
-	{
-		{18,  0,  0,  0},	/* IDSEL 14 - Enet 0 */
-		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
-		{19, 19, 19, 19},	/* IDSEL 16 - PMC Slot 1 */
-		{ 0,  0,  0,  0},	/* IDSEL 17 - unused */
-		{ 0,  0,  0,  0},	/* IDSEL 18 - unused */
-		{ 0,  0,  0,  0},	/* IDSEL 19 - unused */
-		{24, 25, 26, 27},	/* IDSEL 20 - P2P bridge (to cPCI 1) */
-		{ 0,  0,  0,  0},	/* IDSEL 21 - unused */
-		{28, 29, 30, 31}	/* IDSEL 22 - P2P bridge (to cPCI 2) */
-	};
-
-	const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-/* Motorola Sitka */
-static inline int
-sitka_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	    /*
-	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
-	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *         A   B   C   D
-	     */
-	{
-		{18,  0,  0,  0},	/* IDSEL 14 - Enet 0 */
-		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
-		{25, 26, 27, 28},	/* IDSEL 16 - PMC Slot 1 */
-		{28, 25, 26, 27},	/* IDSEL 17 - PMC Slot 2 */
-		{ 0,  0,  0,  0},	/* IDSEL 18 - unused */
-		{ 0,  0,  0,  0},	/* IDSEL 19 - unused */
-		{20,  0,  0,  0}	/* IDSEL 20 - P2P bridge (to cPCI) */
-	};
-
-	const long min_idsel = 14, max_idsel = 20, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-/* Motorola MTX */
-static inline int
-MTX_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	    /*
-	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
-	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *         A   B   C   D
-	     */
-	{
-		{19,  0,  0,  0},	/* IDSEL 12 - SCSI   */
-		{ 0,  0,  0,  0},	/* IDSEL 13 - unused */
-		{18,  0,  0,  0},	/* IDSEL 14 - Enet   */
-		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
-		{25, 26, 27, 28},	/* IDSEL 16 - PMC Slot 1 */
-		{26, 27, 28, 25},	/* IDSEL 17 - PMC Slot 2 */
-		{27, 28, 25, 26}	/* IDSEL 18 - PCI Slot 3 */
-	};
-
-	const long min_idsel = 12, max_idsel = 18, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-/* Motorola MTX Plus */
-/* Secondary bus interrupt routing is not supported yet */
-static inline int
-MTXplus_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	    /*
-	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
-	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *         A   B   C   D
-	     */
-	{
-		{19,  0,  0,  0},	/* IDSEL 12 - SCSI   */
-		{ 0,  0,  0,  0},	/* IDSEL 13 - unused */
-		{18,  0,  0,  0},	/* IDSEL 14 - Enet 1 */
-		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
-		{25, 26, 27, 28},	/* IDSEL 16 - PCI Slot 1P */
-		{26, 27, 28, 25},	/* IDSEL 17 - PCI Slot 2P */
-		{27, 28, 25, 26},	/* IDSEL 18 - PCI Slot 3P */
-		{26,  0,  0,  0},	/* IDSEL 19 - Enet 2 */
-		{ 0,  0,  0,  0}	/* IDSEL 20 - P2P Bridge */
-	};
-
-	const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static inline int
-Genesis2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	/* 2600
-	 * Raven 31
-	 * ISA   11
-	 * SCSI  12 - IRQ3
-	 * Univ  13
-	 * eth   14 - IRQ2
-	 * VGA   15 - IRQ4
-	 * PMC1  16 - IRQ9,10,11,12 = PMC1 A-D
-	 * PMC2  17 - IRQ12,9,10,11 = A-D
-	 * SCSI2 18 - IRQ11
-	 * eth2  19 - IRQ10
-	 * PCIX  20 - IRQ9,10,11,12 = PCI A-D
-	 */
-
-	/* 2400
-	 * Hawk 31
-	 * ISA  11
-	 * Univ 13
-	 * eth  14 - IRQ2
-	 * PMC1 16 - IRQ9,10,11,12 = PMC A-D
-	 * PMC2 17 - IRQ12,9,10,11 = PMC A-D
-	 * PCIX 20 - IRQ9,10,11,12 = PMC A-D
-	 */
-
-	/* 2300
-	 * Raven 31
-	 * ISA   11
-	 * Univ  13
-	 * eth   14 - IRQ2
-	 * PMC1  16 - 9,10,11,12 = A-D
-	 * PMC2  17 - 9,10,11,12 = B,C,D,A
-	 */
-
-	static char pci_irq_table[][4] =
-	    /*
-	     *      MPIC interrupts for various IDSEL values (MPIC IRQ0 =
-	     *      Linux IRQ16 (to leave room for ISA IRQs at 0-15).
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *         A   B   C   D
-	     */
-	{
-		{19,  0,  0,  0},	/* IDSEL 12 - SCSI   */
-		{ 0,  0,  0,  0},	/* IDSEL 13 - Universe PCI - VME */
-		{18,  0,  0,  0},	/* IDSEL 14 - Enet 1 */
-		{ 0,  0,  0,  0},	/* IDSEL 15 - unused */
-		{25, 26, 27, 28},	/* IDSEL 16 - PCI/PMC Slot 1P */
-		{28, 25, 26, 27},	/* IDSEL 17 - PCI/PMC Slot 2P */
-		{27, 28, 25, 26},	/* IDSEL 18 - PCI Slot 3P */
-		{26,  0,  0,  0},	/* IDSEL 19 - Enet 2 */
-		{25, 26, 27, 28}	/* IDSEL 20 - P2P Bridge */
-	};
-
-	const long min_idsel = 12, max_idsel = 20, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-#define MOTOROLA_CPUTYPE_REG	0x800
-#define MOTOROLA_BASETYPE_REG	0x803
-#define MPIC_RAVEN_ID		0x48010000
-#define	MPIC_HAWK_ID		0x48030000
-#define	MOT_PROC2_BIT		0x800
-
-static u_char pplus_openpic_initsenses[] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
-	(IRQ_SENSE_EDGE | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_FALCN_ECC_ERR */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_ETHERNET */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),/*MVME2600_INT_PCI_GRAPHICS */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),
-};
-
-int mot_entry = -1;
-int prep_keybd_present = 1;
-int mot_multi = 0;
-
-struct brd_info {
-	/* 0x100 mask assumes for Raven and Hawk boards that the level/edge
-	 * are set */
-	int cpu_type;
-	/* 0x200 if this board has a Hawk chip. */
-	int base_type;
-	/* or'ed with 0x80 if this board should be checked for multi CPU */
-	int max_cpu;
-	const char *name;
-	int (*map_irq) (struct pci_dev *, unsigned char, unsigned char);
-};
-struct brd_info mot_info[] = {
-	{0x300, 0x00, 0x00, "MVME 2400", Genesis2_map_irq},
-	{0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)", mesquite_map_irq},
-	{0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)", sitka_map_irq},
-	{0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC", mesquite_map_irq},
-	{0x1E0, 0xF6, 0x80, "MTX Plus", MTXplus_map_irq},
-	{0x1E0, 0xF6, 0x81, "Dual MTX Plus", MTXplus_map_irq},
-	{0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port", MTX_map_irq},
-	{0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port", MTX_map_irq},
-	{0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port", MTX_map_irq},
-	{0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port", MTX_map_irq},
-	{0x1E0, 0xF9, 0x00, "MVME 2300", Genesis2_map_irq},
-	{0x1E0, 0xFA, 0x00, "MVME 2300SC/2600", Genesis2_map_irq},
-	{0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M", Genesis2_map_irq},
-	{0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761", Genesis2_map_irq},
-	{0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M", Genesis2_map_irq},
-	{0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M", Genesis2_map_irq},
-	{0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761", Genesis2_map_irq},
-	{0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761", Genesis2_map_irq},
-	{0x000, 0x00, 0x00, "", NULL}
-};
-
-void __init pplus_set_board_type(void)
-{
-	unsigned char cpu_type;
-	unsigned char base_mod;
-	int entry;
-	unsigned short devid;
-	unsigned long *ProcInfo = NULL;
-
-	cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
-	base_mod = inb(MOTOROLA_BASETYPE_REG);
-	early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
-
-	for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
-		/* Check for Hawk chip */
-		if (mot_info[entry].cpu_type & 0x200) {
-			if (devid != PCI_DEVICE_ID_MOTOROLA_HAWK)
-				continue;
-		} else {
-			/* store the system config register for later use. */
-			ProcInfo =
-			    (unsigned long *)ioremap(PPLUS_SYS_CONFIG_REG, 4);
-
-			/* Check non hawk boards */
-			if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
-				continue;
-
-			if (mot_info[entry].base_type == 0) {
-				mot_entry = entry;
-				break;
-			}
-
-			if (mot_info[entry].base_type != base_mod)
-				continue;
-		}
-
-		if (!(mot_info[entry].max_cpu & 0x80)) {
-			mot_entry = entry;
-			break;
-		}
-
-		/* processor 1 not present and max processor zero indicated */
-		if ((*ProcInfo & MOT_PROC2_BIT)
-		    && !(mot_info[entry].max_cpu & 0x7f)) {
-			mot_entry = entry;
-			break;
-		}
-
-		/* processor 1 present and max processor zero indicated */
-		if (!(*ProcInfo & MOT_PROC2_BIT)
-		    && (mot_info[entry].max_cpu & 0x7f)) {
-			mot_entry = entry;
-			break;
-		}
-
-		/* Indicate to system if this is a multiprocessor board */
-		if (!(*ProcInfo & MOT_PROC2_BIT))
-			mot_multi = 1;
-	}
-
-	if (mot_entry == -1)
-		/* No particular cpu type found - assume Mesquite (MCP750) */
-		mot_entry = 1;
-
-	Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
-	ppc_md.pci_map_irq = mot_info[mot_entry].map_irq;
-}
-void __init pplus_pib_init(void)
-{
-	unsigned char reg;
-	unsigned short short_reg;
-
-	struct pci_dev *dev = NULL;
-
-	/*
-	 * Perform specific configuration for the Via Tech or
-	 * or Winbond PCI-ISA-Bridge part.
-	 */
-	if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
-				   PCI_DEVICE_ID_VIA_82C586_1, dev))) {
-		/*
-		 * PPCBUG does not set the enable bits
-		 * for the IDE device. Force them on here.
-		 */
-		pci_read_config_byte(dev, 0x40, &reg);
-
-		reg |= 0x03;	/* IDE: Chip Enable Bits */
-		pci_write_config_byte(dev, 0x40, reg);
-	}
-
-	if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
-				   PCI_DEVICE_ID_VIA_82C586_2,
-				   dev)) && (dev->devfn = 0x5a)) {
-		/* Force correct USB interrupt */
-		dev->irq = 11;
-		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-	}
-
-	if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
-				   PCI_DEVICE_ID_WINBOND_83C553, dev))) {
-		/* Clear PCI Interrupt Routing Control Register. */
-		short_reg = 0x0000;
-		pci_write_config_word(dev, 0x44, short_reg);
-		/* Route IDE interrupts to IRQ 14 */
-		reg = 0xEE;
-		pci_write_config_byte(dev, 0x43, reg);
-	}
-
-	if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
-				   PCI_DEVICE_ID_WINBOND_82C105, dev))) {
-		/*
-		 * Disable LEGIRQ mode so PCI INTS are routed
-		 * directly to the 8259 and enable both channels
-		 */
-		pci_write_config_dword(dev, 0x40, 0x10ff0033);
-
-		/* Force correct IDE interrupt */
-		dev->irq = 14;
-		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-	}
-	pci_dev_put(dev);
-}
-
-void __init pplus_set_VIA_IDE_legacy(void)
-{
-	unsigned short vend, dev;
-
-	early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
-	early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
-
-	if ((vend == PCI_VENDOR_ID_VIA) &&
-			(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
-		unsigned char temp;
-
-		/* put back original "standard" port base addresses */
-		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
-					 PCI_BASE_ADDRESS_0, 0x1f1);
-		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
-					 PCI_BASE_ADDRESS_1, 0x3f5);
-		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
-					 PCI_BASE_ADDRESS_2, 0x171);
-		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
-					 PCI_BASE_ADDRESS_3, 0x375);
-		early_write_config_dword(0, 0, PCI_DEVFN(0xb, 1),
-					 PCI_BASE_ADDRESS_4, 0xcc01);
-
-		/* put into legacy mode */
-		early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
-				       &temp);
-		temp &= ~0x05;
-		early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
-					temp);
-	}
-}
-
-void pplus_set_VIA_IDE_native(void)
-{
-	unsigned short vend, dev;
-
-	early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_VENDOR_ID, &vend);
-	early_read_config_word(0, 0, PCI_DEVFN(0xb, 1), PCI_DEVICE_ID, &dev);
-
-	if ((vend == PCI_VENDOR_ID_VIA) &&
-			(dev == PCI_DEVICE_ID_VIA_82C586_1)) {
-		unsigned char temp;
-
-		/* put into native mode */
-		early_read_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
-				       &temp);
-		temp |= 0x05;
-		early_write_config_byte(0, 0, PCI_DEVFN(0xb, 1), PCI_CLASS_PROG,
-					temp);
-	}
-}
-
-void __init pplus_pcibios_fixup(void)
-{
-
-	unsigned char reg;
-	unsigned short devid;
-	unsigned char base_mod;
-
-	printk(KERN_INFO "Setting PCI interrupts for a \"%s\"\n",
-			Motherboard_map_name);
-
-	/* Setup the Winbond or Via PIB */
-	pplus_pib_init();
-
-	/* Set up floppy in PS/2 mode */
-	outb(0x09, SIO_CONFIG_RA);
-	reg = inb(SIO_CONFIG_RD);
-	reg = (reg & 0x3F) | 0x40;
-	outb(reg, SIO_CONFIG_RD);
-	outb(reg, SIO_CONFIG_RD);	/* Have to write twice to change! */
-
-	/* This is a hack.  If this is a 2300 or 2400 mot board then there is
-	 * no keyboard controller and we have to indicate that.
-	 */
-
-	early_read_config_word(0, 0, 0, PCI_VENDOR_ID, &devid);
-	base_mod = inb(MOTOROLA_BASETYPE_REG);
-	if ((devid == PCI_DEVICE_ID_MOTOROLA_HAWK) ||
-	    (base_mod == 0xF9) || (base_mod == 0xFA) || (base_mod == 0xE1))
-		prep_keybd_present = 0;
-}
-
-void __init pplus_find_bridges(void)
-{
-	struct pci_controller *hose;
-
-	hose = pcibios_alloc_controller();
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	hose->pci_mem_offset = PREP_ISA_MEM_BASE;
-	hose->io_base_virt = (void *)PREP_ISA_IO_BASE;
-
-	pci_init_resource(&hose->io_resource, PPLUS_PCI_IO_START,
-			  PPLUS_PCI_IO_END, IORESOURCE_IO, "PCI host bridge");
-	pci_init_resource(&hose->mem_resources[0], PPLUS_PROC_PCI_MEM_START,
-			  PPLUS_PROC_PCI_MEM_END, IORESOURCE_MEM,
-			  "PCI host bridge");
-
-	hose->io_space.start = PPLUS_PCI_IO_START;
-	hose->io_space.end = PPLUS_PCI_IO_END;
-	hose->mem_space.start = PPLUS_PCI_MEM_START;
-	hose->mem_space.end = PPLUS_PCI_MEM_END - HAWK_MPIC_SIZE;
-
-	if (hawk_init(hose, PPLUS_HAWK_PPC_REG_BASE, PPLUS_PROC_PCI_MEM_START,
-				PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
-				PPLUS_PROC_PCI_IO_START, PPLUS_PROC_PCI_IO_END,
-				PPLUS_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
-			!= 0) {
-		printk(KERN_CRIT "Could not initialize host bridge\n");
-
-	}
-
-	pplus_set_VIA_IDE_legacy();
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pcibios_fixup = pplus_pcibios_fixup;
-	ppc_md.pci_swizzle = common_swizzle;
-}
-
-static int pplus_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: Motorola MCG\n");
-	seq_printf(m, "machine\t\t: %s\n", Motherboard_map_name);
-
-	return 0;
-}
-
-static void __init pplus_setup_arch(void)
-{
-	struct pci_controller *hose;
-
-	if (ppc_md.progress)
-		ppc_md.progress("pplus_setup_arch: enter", 0);
-
-	/* init to some ~sane value until calibrate_delay() runs */
-	loops_per_jiffy = 50000000;
-
-	if (ppc_md.progress)
-		ppc_md.progress("pplus_setup_arch: find_bridges", 0);
-
-	/* Setup PCI host bridge */
-	pplus_find_bridges();
-
-	hose = pci_bus_to_hose(0);
-	isa_io_base = (ulong) hose->io_base_virt;
-
-	if (ppc_md.progress)
-		ppc_md.progress("pplus_setup_arch: set_board_type", 0);
-
-	pplus_set_board_type();
-
-	/* Enable L2.  Assume we don't need to flush -- Cort */
-	*(unsigned char *)(PPLUS_L2_CONTROL_REG) |= 3;
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	printk(KERN_INFO "Motorola PowerPlus Platform\n");
-	printk(KERN_INFO
-	       "Port by MontaVista Software, Inc. (source@mvista.com)\n");
-
-#ifdef CONFIG_VGA_CONSOLE
-	/* remap the VGA memory */
-	vgacon_remap_base = (unsigned long)ioremap(PPLUS_ISA_MEM_BASE,
-						   0x08000000);
-	conswitchp = &vga_con;
-#endif
-#ifdef CONFIG_PPCBUG_NVRAM
-	/* Read in NVRAM data */
-	init_prep_nvram();
-
-	/* if no bootargs, look in NVRAM */
-	if (cmd_line[0] == '\0') {
-		char *bootargs;
-		bootargs = prep_nvram_get_var("bootargs");
-		if (bootargs != NULL) {
-			strcpy(cmd_line, bootargs);
-			/* again.. */
-			strcpy(boot_command_line, cmd_line);
-		}
-	}
-#endif
-	if (ppc_md.progress)
-		ppc_md.progress("pplus_setup_arch: exit", 0);
-}
-
-static void pplus_restart(char *cmd)
-{
-	unsigned long i = 10000;
-
-	local_irq_disable();
-
-	/* set VIA IDE controller into native mode */
-	pplus_set_VIA_IDE_native();
-
-	/* set exception prefix high - to the prom */
-	_nmask_and_or_msr(0, MSR_IP);
-
-	/* make sure bit 0 (reset) is a 0 */
-	outb(inb(0x92) & ~1L, 0x92);
-	/* signal a reset to system control port A - soft reset */
-	outb(inb(0x92) | 1, 0x92);
-
-	while (i != 0)
-		i++;
-	panic("restart failed\n");
-}
-
-static void pplus_halt(void)
-{
-	/* set exception prefix high - to the prom */
-	_nmask_and_or_msr(MSR_EE, MSR_IP);
-
-	/* make sure bit 0 (reset) is a 0 */
-	outb(inb(0x92) & ~1L, 0x92);
-	/* signal a reset to system control port A - soft reset */
-	outb(inb(0x92) | 1, 0x92);
-
-	while (1) ;
-	/*
-	 * Not reached
-	 */
-}
-
-static void pplus_power_off(void)
-{
-	pplus_halt();
-}
-
-static void __init pplus_init_IRQ(void)
-{
-	int i;
-
-	if (ppc_md.progress)
-		ppc_md.progress("init_irq: enter", 0);
-
-	OpenPIC_InitSenses = pplus_openpic_initsenses;
-	OpenPIC_NumInitSenses = sizeof(pplus_openpic_initsenses);
-
-	if (OpenPIC_Addr != NULL) {
-
-		openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
-		openpic_init(NUM_8259_INTERRUPTS);
-		openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
-					i8259_irq);
-		ppc_md.get_irq = openpic_get_irq;
-	}
-
-	i8259_init(0, 0);
-
-	if (ppc_md.progress)
-		ppc_md.progress("init_irq: exit", 0);
-}
-
-#ifdef CONFIG_SMP
-/* PowerPlus (MTX) support */
-static int __init smp_pplus_probe(void)
-{
-	extern int mot_multi;
-
-	if (mot_multi) {
-		openpic_request_IPIs();
-		smp_hw_index[1] = 1;
-		return 2;
-	}
-
-	return 1;
-}
-
-static void __init smp_pplus_kick_cpu(int nr)
-{
-	*(unsigned long *)KERNELBASE = nr;
-	asm volatile ("dcbf 0,%0"::"r" (KERNELBASE):"memory");
-	printk(KERN_INFO "CPU1 reset, waiting\n");
-}
-
-static void __init smp_pplus_setup_cpu(int cpu_nr)
-{
-	if (OpenPIC_Addr)
-		do_openpic_setup_cpu();
-}
-
-static struct smp_ops_t pplus_smp_ops = {
-	smp_openpic_message_pass,
-	smp_pplus_probe,
-	smp_pplus_kick_cpu,
-	smp_pplus_setup_cpu,
-	.give_timebase = smp_generic_give_timebase,
-	.take_timebase = smp_generic_take_timebase,
-};
-#endif				/* CONFIG_SMP */
-
-#ifdef DUMP_DBATS
-static void print_dbat(int idx, u32 bat)
-{
-
-	char str[64];
-
-	sprintf(str, "DBAT%c%c = 0x%08x\n",
-		(char)((idx - DBAT0U) / 2) + '0', (idx & 1) ? 'L' : 'U', bat);
-	ppc_md.progress(str, 0);
-}
-
-#define DUMP_DBAT(x) \
-	do { \
-	u32 __temp = mfspr(x);\
-	print_dbat(x, __temp); \
-	} while (0)
-
-static void dump_dbats(void)
-{
-	if (ppc_md.progress) {
-		DUMP_DBAT(DBAT0U);
-		DUMP_DBAT(DBAT0L);
-		DUMP_DBAT(DBAT1U);
-		DUMP_DBAT(DBAT1L);
-		DUMP_DBAT(DBAT2U);
-		DUMP_DBAT(DBAT2L);
-		DUMP_DBAT(DBAT3U);
-		DUMP_DBAT(DBAT3L);
-	}
-}
-#endif
-
-static unsigned long __init pplus_find_end_of_memory(void)
-{
-	unsigned long total;
-
-	if (ppc_md.progress)
-		ppc_md.progress("pplus_find_end_of_memory", 0);
-
-#ifdef DUMP_DBATS
-	dump_dbats();
-#endif
-
-	total = hawk_get_mem_size(PPLUS_HAWK_SMC_BASE);
-	return (total);
-}
-
-static void __init pplus_map_io(void)
-{
-	io_block_mapping(PPLUS_ISA_IO_BASE, PPLUS_ISA_IO_BASE, 0x10000000,
-			 _PAGE_IO);
-	io_block_mapping(0xfef80000, 0xfef80000, 0x00080000, _PAGE_IO);
-}
-
-static void __init pplus_init2(void)
-{
-#ifdef CONFIG_NVRAM
-	request_region(PREP_NVRAM_AS0, 0x8, "nvram");
-#endif
-	request_region(0x20, 0x20, "pic1");
-	request_region(0xa0, 0x20, "pic2");
-	request_region(0x00, 0x20, "dma1");
-	request_region(0x40, 0x20, "timer");
-	request_region(0x80, 0x10, "dma page reg");
-	request_region(0xc0, 0x20, "dma2");
-}
-
-/*
- * Set BAT 2 to access 0x8000000 so progress messages will work and set BAT 3
- * to 0xf0000000 to access Falcon/Raven or Hawk registers
- */
-static __inline__ void pplus_set_bat(void)
-{
-	/* wait for all outstanding memory accesses to complete */
-	mb();
-
-	/* setup DBATs */
-	mtspr(SPRN_DBAT2U, 0x80001ffe);
-	mtspr(SPRN_DBAT2L, 0x8000002a);
-	mtspr(SPRN_DBAT3U, 0xf0001ffe);
-	mtspr(SPRN_DBAT3L, 0xf000002a);
-
-	/* wait for updates */
-	mb();
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	/* Map in board regs, etc. */
-	pplus_set_bat();
-
-	isa_io_base = PREP_ISA_IO_BASE;
-	isa_mem_base = PREP_ISA_MEM_BASE;
-	pci_dram_offset = PREP_PCI_DRAM_OFFSET;
-	ISA_DMA_THRESHOLD = 0x00ffffff;
-	DMA_MODE_READ = 0x44;
-	DMA_MODE_WRITE = 0x48;
-	ppc_do_canonicalize_irqs = 1;
-
-	ppc_md.setup_arch = pplus_setup_arch;
-	ppc_md.show_cpuinfo = pplus_show_cpuinfo;
-	ppc_md.init_IRQ = pplus_init_IRQ;
-	/* this gets changed later on if we have an OpenPIC -- Cort */
-	ppc_md.get_irq = i8259_irq;
-	ppc_md.init = pplus_init2;
-
-	ppc_md.restart = pplus_restart;
-	ppc_md.power_off = pplus_power_off;
-	ppc_md.halt = pplus_halt;
-
-	TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
-		  PREP_NVRAM_DATA, 8);
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.calibrate_decr = todc_calibrate_decr;
-	ppc_md.nvram_read_val = todc_m48txx_read_val;
-	ppc_md.nvram_write_val = todc_m48txx_write_val;
-
-	ppc_md.find_end_of_memory = pplus_find_end_of_memory;
-	ppc_md.setup_io_mappings = pplus_map_io;
-
-#ifdef CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.progress = gen550_progress;
-#endif				/* CONFIG_SERIAL_TEXT_DEBUG */
-#ifdef CONFIG_KGDB
-	ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
-#endif
-#ifdef CONFIG_SMP
-	smp_ops = &pplus_smp_ops;
-#endif				/* CONFIG_SMP */
-}
diff --git a/arch/ppc/platforms/pplus.h b/arch/ppc/platforms/pplus.h
deleted file mode 100644
index a4bbaa8d858..00000000000
--- a/arch/ppc/platforms/pplus.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
- *
- * Author: Mark A. Greerinclude/asm-ppc/hawk.h
- *         mgreer@mvista.com
- *
- * Modified by Randy Vinson (rvinson@mvista.com)
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PPC_PPLUS_H
-#define __PPC_PPLUS_H
-
-#include <asm/io.h>
-
-/*
- * Due to limitations imposed by legacy hardware (primarily IDE controllers),
- * the PPLUS boards operate using a PReP address map.
- *
- * From Processor (physical) -> PCI:
- *   PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
- *   PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
- *	Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
- *
- * From PCI -> Processor (physical):
- *   System Memory: 0x80000000 -> 0x00000000
- */
-
-#define PPLUS_ISA_MEM_BASE		PREP_ISA_MEM_BASE
-#define PPLUS_ISA_IO_BASE		PREP_ISA_IO_BASE
-
-/* PCI Memory space mapping info */
-#define PPLUS_PCI_MEM_SIZE		0x30000000U
-#define PPLUS_PROC_PCI_MEM_START	PPLUS_ISA_MEM_BASE
-#define PPLUS_PROC_PCI_MEM_END		(PPLUS_PROC_PCI_MEM_START +	\
-					 PPLUS_PCI_MEM_SIZE - 1)
-#define PPLUS_PCI_MEM_START		0x00000000U
-#define PPLUS_PCI_MEM_END		(PPLUS_PCI_MEM_START +	\
-					 PPLUS_PCI_MEM_SIZE - 1)
-
-/* PCI I/O space mapping info */
-#define PPLUS_PCI_IO_SIZE		0x10000000U
-#define PPLUS_PROC_PCI_IO_START		PPLUS_ISA_IO_BASE
-#define PPLUS_PROC_PCI_IO_END		(PPLUS_PROC_PCI_IO_START +	\
-					 PPLUS_PCI_IO_SIZE - 1)
-#define PPLUS_PCI_IO_START		0x00000000U
-#define PPLUS_PCI_IO_END		(PPLUS_PCI_IO_START + 	\
-					 PPLUS_PCI_IO_SIZE - 1)
-/* System memory mapping info */
-#define PPLUS_PCI_DRAM_OFFSET		PREP_PCI_DRAM_OFFSET
-#define PPLUS_PCI_PHY_MEM_OFFSET	(PPLUS_ISA_MEM_BASE-PPLUS_PCI_MEM_START)
-
-/* Define base addresses for important sets of registers */
-#define PPLUS_HAWK_SMC_BASE		0xfef80000U
-#define PPLUS_HAWK_PPC_REG_BASE		0xfeff0000U
-#define PPLUS_SYS_CONFIG_REG		0xfef80400U
-#define PPLUS_L2_CONTROL_REG		0x8000081cU
-
-#define PPLUS_VGA_MEM_BASE		0xf0000000U
-
-#endif	/* __PPC_PPLUS_H */
diff --git a/arch/ppc/platforms/prep_pci.c b/arch/ppc/platforms/prep_pci.c
deleted file mode 100644
index 8ed433e2a5c..00000000000
--- a/arch/ppc/platforms/prep_pci.c
+++ /dev/null
@@ -1,1339 +0,0 @@
-/*
- * PReP pci functions.
- * Originally by Gary Thomas
- * rewritten and updated by Cort Dougan (cort@cs.nmt.edu)
- *
- * The motherboard routes/maps will disappear shortly. -- Cort
- */
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#include <asm/sections.h>
-#include <asm/byteorder.h>
-#include <asm/io.h>
-#include <asm/ptrace.h>
-#include <asm/prom.h>
-#include <asm/pci-bridge.h>
-#include <asm/residual.h>
-#include <asm/irq.h>
-#include <asm/machdep.h>
-#include <asm/open_pic.h>
-
-extern void (*setup_ibm_pci)(char *irq_lo, char *irq_hi);
-
-/* Which PCI interrupt line does a given device [slot] use? */
-/* Note: This really should be two dimensional based in slot/pin used */
-static unsigned char *Motherboard_map;
-unsigned char *Motherboard_map_name;
-
-/* How is the 82378 PIRQ mapping setup? */
-static unsigned char *Motherboard_routes;
-
-static void (*Motherboard_non0)(struct pci_dev *);
-
-static void Powerplus_Map_Non0(struct pci_dev *);
-
-/* Used for Motorola to store system config register */
-static unsigned long	*ProcInfo;
-
-/* Tables for known hardware */
-
-/* Motorola PowerStackII - Utah */
-static char Utah_pci_IRQ_map[23] =
-{
-        0,   /* Slot 0  - unused */
-        0,   /* Slot 1  - unused */
-        5,   /* Slot 2  - SCSI - NCR825A  */
-        0,   /* Slot 3  - unused */
-        3,   /* Slot 4  - Ethernet - DEC2114x */
-        0,   /* Slot 5  - unused */
-        2,   /* Slot 6  - PCI Card slot #1 */
-        3,   /* Slot 7  - PCI Card slot #2 */
-        5,   /* Slot 8  - PCI Card slot #3 */
-        5,   /* Slot 9  - PCI Bridge */
-             /* added here in case we ever support PCI bridges */
-             /* Secondary PCI bus cards are at slot-9,6 & slot-9,7 */
-        0,   /* Slot 10 - unused */
-        0,   /* Slot 11 - unused */
-        5,   /* Slot 12 - SCSI - NCR825A */
-        0,   /* Slot 13 - unused */
-        3,   /* Slot 14 - enet */
-        0,   /* Slot 15 - unused */
-        2,   /* Slot 16 - unused */
-        3,   /* Slot 17 - unused */
-        5,   /* Slot 18 - unused */
-        0,   /* Slot 19 - unused */
-        0,   /* Slot 20 - unused */
-        0,   /* Slot 21 - unused */
-        0,   /* Slot 22 - unused */
-};
-
-static char Utah_pci_IRQ_routes[] =
-{
-        0,   /* Line 0 - Unused */
-        9,   /* Line 1 */
-	10,  /* Line 2 */
-        11,  /* Line 3 */
-        14,  /* Line 4 */
-        15,  /* Line 5 */
-};
-
-/* Motorola PowerStackII - Omaha */
-/* no integrated SCSI or ethernet */
-static char Omaha_pci_IRQ_map[23] =
-{
-        0,   /* Slot 0  - unused */
-        0,   /* Slot 1  - unused */
-        3,   /* Slot 2  - Winbond EIDE */
-        0,   /* Slot 3  - unused */
-        0,   /* Slot 4  - unused */
-        0,   /* Slot 5  - unused */
-        1,   /* Slot 6  - PCI slot 1 */
-        2,   /* Slot 7  - PCI slot 2  */
-        3,   /* Slot 8  - PCI slot 3 */
-        4,   /* Slot 9  - PCI slot 4 */ /* needs indirect access */
-        0,   /* Slot 10 - unused */
-        0,   /* Slot 11 - unused */
-        0,   /* Slot 12 - unused */
-        0,   /* Slot 13 - unused */
-        0,   /* Slot 14 - unused */
-        0,   /* Slot 15 - unused */
-        1,   /* Slot 16  - PCI slot 1 */
-        2,   /* Slot 17  - PCI slot 2  */
-        3,   /* Slot 18  - PCI slot 3 */
-        4,   /* Slot 19  - PCI slot 4 */ /* needs indirect access */
-        0,
-        0,
-        0,
-};
-
-static char Omaha_pci_IRQ_routes[] =
-{
-        0,   /* Line 0 - Unused */
-        9,   /* Line 1 */
-        11,  /* Line 2 */
-        14,  /* Line 3 */
-        15   /* Line 4 */
-};
-
-/* Motorola PowerStack */
-static char Blackhawk_pci_IRQ_map[19] =
-{
-  	0,	/* Slot 0  - unused */
-  	0,	/* Slot 1  - unused */
-  	0,	/* Slot 2  - unused */
-  	0,	/* Slot 3  - unused */
-  	0,	/* Slot 4  - unused */
-  	0,	/* Slot 5  - unused */
-  	0,	/* Slot 6  - unused */
-  	0,	/* Slot 7  - unused */
-  	0,	/* Slot 8  - unused */
-  	0,	/* Slot 9  - unused */
-  	0,	/* Slot 10 - unused */
-  	0,	/* Slot 11 - unused */
-  	3,	/* Slot 12 - SCSI */
-  	0,	/* Slot 13 - unused */
-  	1,	/* Slot 14 - Ethernet */
-  	0,	/* Slot 15 - unused */
- 	1,	/* Slot P7 */
- 	2,	/* Slot P6 */
- 	3,	/* Slot P5 */
-};
-
-static char Blackhawk_pci_IRQ_routes[] =
-{
-   	0,	/* Line 0 - Unused */
-   	9,	/* Line 1 */
-   	11,	/* Line 2 */
-   	15,	/* Line 3 */
-   	15	/* Line 4 */
-};
-
-/* Motorola Mesquite */
-static char Mesquite_pci_IRQ_map[23] =
-{
-	0,	/* Slot 0  - unused */
-	0,	/* Slot 1  - unused */
-	0,	/* Slot 2  - unused */
-	0,	/* Slot 3  - unused */
-	0,	/* Slot 4  - unused */
-	0,	/* Slot 5  - unused */
-	0,	/* Slot 6  - unused */
-	0,	/* Slot 7  - unused */
-	0,	/* Slot 8  - unused */
-	0,	/* Slot 9  - unused */
-	0,	/* Slot 10 - unused */
-	0,	/* Slot 11 - unused */
-	0,	/* Slot 12 - unused */
-	0,	/* Slot 13 - unused */
-	2,	/* Slot 14 - Ethernet */
-	0,	/* Slot 15 - unused */
-	3,	/* Slot 16 - PMC */
-	0,	/* Slot 17 - unused */
-	0,	/* Slot 18 - unused */
-	0,	/* Slot 19 - unused */
-	0,	/* Slot 20 - unused */
-	0,	/* Slot 21 - unused */
-	0,	/* Slot 22 - unused */
-};
-
-/* Motorola Sitka */
-static char Sitka_pci_IRQ_map[21] =
-{
-	0,      /* Slot 0  - unused */
-	0,      /* Slot 1  - unused */
-	0,      /* Slot 2  - unused */
-	0,      /* Slot 3  - unused */
-	0,      /* Slot 4  - unused */
-	0,      /* Slot 5  - unused */
-	0,      /* Slot 6  - unused */
-	0,      /* Slot 7  - unused */
-	0,      /* Slot 8  - unused */
-	0,      /* Slot 9  - unused */
-	0,      /* Slot 10 - unused */
-	0,      /* Slot 11 - unused */
-	0,      /* Slot 12 - unused */
-	0,      /* Slot 13 - unused */
-	2,      /* Slot 14 - Ethernet */
-	0,      /* Slot 15 - unused */
-	9,      /* Slot 16 - PMC 1  */
-	12,     /* Slot 17 - PMC 2  */
-	0,      /* Slot 18 - unused */
-	0,      /* Slot 19 - unused */
-	4,      /* Slot 20 - NT P2P bridge */
-};
-
-/* Motorola MTX */
-static char MTX_pci_IRQ_map[23] =
-{
-	0,	/* Slot 0  - unused */
-	0,	/* Slot 1  - unused */
-	0,	/* Slot 2  - unused */
-	0,	/* Slot 3  - unused */
-	0,	/* Slot 4  - unused */
-	0,	/* Slot 5  - unused */
-	0,	/* Slot 6  - unused */
-	0,	/* Slot 7  - unused */
-	0,	/* Slot 8  - unused */
-	0,	/* Slot 9  - unused */
-	0,	/* Slot 10 - unused */
-	0,	/* Slot 11 - unused */
-	3,	/* Slot 12 - SCSI */
-	0,	/* Slot 13 - unused */
-	2,	/* Slot 14 - Ethernet */
-	0,	/* Slot 15 - unused */
-	9,      /* Slot 16 - PCI/PMC slot 1 */
-	10,     /* Slot 17 - PCI/PMC slot 2 */
-	11,     /* Slot 18 - PCI slot 3 */
-	0,	/* Slot 19 - unused */
-	0,	/* Slot 20 - unused */
-	0,	/* Slot 21 - unused */
-	0,	/* Slot 22 - unused */
-};
-
-/* Motorola MTX Plus */
-/* Secondary bus interrupt routing is not supported yet */
-static char MTXplus_pci_IRQ_map[23] =
-{
-        0,      /* Slot 0  - unused */
-        0,      /* Slot 1  - unused */
-        0,      /* Slot 2  - unused */
-        0,      /* Slot 3  - unused */
-        0,      /* Slot 4  - unused */
-        0,      /* Slot 5  - unused */
-        0,      /* Slot 6  - unused */
-        0,      /* Slot 7  - unused */
-        0,      /* Slot 8  - unused */
-        0,      /* Slot 9  - unused */
-        0,      /* Slot 10 - unused */
-        0,      /* Slot 11 - unused */
-        3,      /* Slot 12 - SCSI */
-        0,      /* Slot 13 - unused */
-        2,      /* Slot 14 - Ethernet 1 */
-        0,      /* Slot 15 - unused */
-        9,      /* Slot 16 - PCI slot 1P */
-        10,     /* Slot 17 - PCI slot 2P */
-        11,     /* Slot 18 - PCI slot 3P */
-        10,     /* Slot 19 - Ethernet 2 */
-        0,      /* Slot 20 - P2P Bridge */
-        0,      /* Slot 21 - unused */
-        0,      /* Slot 22 - unused */
-};
-
-static char Raven_pci_IRQ_routes[] =
-{
-   	0,	/* This is a dummy structure */
-};
-
-/* Motorola MVME16xx */
-static char Genesis_pci_IRQ_map[16] =
-{
-  	0,	/* Slot 0  - unused */
-  	0,	/* Slot 1  - unused */
-  	0,	/* Slot 2  - unused */
-  	0,	/* Slot 3  - unused */
-  	0,	/* Slot 4  - unused */
-  	0,	/* Slot 5  - unused */
-  	0,	/* Slot 6  - unused */
-  	0,	/* Slot 7  - unused */
-  	0,	/* Slot 8  - unused */
-  	0,	/* Slot 9  - unused */
-  	0,	/* Slot 10 - unused */
-  	0,	/* Slot 11 - unused */
-  	3,	/* Slot 12 - SCSI */
-  	0,	/* Slot 13 - unused */
-  	1,	/* Slot 14 - Ethernet */
-  	0,	/* Slot 15 - unused */
-};
-
-static char Genesis_pci_IRQ_routes[] =
-{
-   	0,	/* Line 0 - Unused */
-   	10,	/* Line 1 */
-   	11,	/* Line 2 */
-   	14,	/* Line 3 */
-   	15	/* Line 4 */
-};
-
-static char Genesis2_pci_IRQ_map[23] =
-{
-	0,	/* Slot 0  - unused */
-	0,	/* Slot 1  - unused */
-	0,	/* Slot 2  - unused */
-	0,	/* Slot 3  - unused */
-	0,	/* Slot 4  - unused */
-	0,	/* Slot 5  - unused */
-	0,	/* Slot 6  - unused */
-	0,	/* Slot 7  - unused */
-	0,	/* Slot 8  - unused */
-	0,	/* Slot 9  - unused */
-	0,	/* Slot 10 - unused */
-	0,	/* Slot 11 - IDE */
-	3,	/* Slot 12 - SCSI */
-	5,	/* Slot 13 - Universe PCI - VME Bridge */
-	2,	/* Slot 14 - Ethernet */
-	0,	/* Slot 15 - unused */
-	9,	/* Slot 16 - PMC 1 */
-	12,	/* Slot 17 - pci */
-	11,	/* Slot 18 - pci */
-	10,	/* Slot 19 - pci */
-	0,	/* Slot 20 - pci */
-	0,	/* Slot 21 - unused */
-	0,	/* Slot 22 - unused */
-};
-
-/* Motorola Series-E */
-static char Comet_pci_IRQ_map[23] =
-{
-  	0,	/* Slot 0  - unused */
-  	0,	/* Slot 1  - unused */
-  	0,	/* Slot 2  - unused */
-  	0,	/* Slot 3  - unused */
-  	0,	/* Slot 4  - unused */
-  	0,	/* Slot 5  - unused */
-  	0,	/* Slot 6  - unused */
-  	0,	/* Slot 7  - unused */
-  	0,	/* Slot 8  - unused */
-  	0,	/* Slot 9  - unused */
-  	0,	/* Slot 10 - unused */
-  	0,	/* Slot 11 - unused */
-  	3,	/* Slot 12 - SCSI */
-  	0,	/* Slot 13 - unused */
-  	1,	/* Slot 14 - Ethernet */
-  	0,	/* Slot 15 - unused */
-	1,	/* Slot 16 - PCI slot 1 */
-	2,	/* Slot 17 - PCI slot 2 */
-	3,	/* Slot 18 - PCI slot 3 */
-	4,	/* Slot 19 - PCI bridge */
-	0,
-	0,
-	0,
-};
-
-static char Comet_pci_IRQ_routes[] =
-{
-   	0,	/* Line 0 - Unused */
-   	10,	/* Line 1 */
-   	11,	/* Line 2 */
-   	14,	/* Line 3 */
-   	15	/* Line 4 */
-};
-
-/* Motorola Series-EX */
-static char Comet2_pci_IRQ_map[23] =
-{
-	0,	/* Slot 0  - unused */
-	0,	/* Slot 1  - unused */
-	3,	/* Slot 2  - SCSI - NCR825A */
-	0,	/* Slot 3  - unused */
-	1,	/* Slot 4  - Ethernet - DEC2104X */
-	0,	/* Slot 5  - unused */
-	1,	/* Slot 6  - PCI slot 1 */
-	2,	/* Slot 7  - PCI slot 2 */
-	3,	/* Slot 8  - PCI slot 3 */
-	4,	/* Slot 9  - PCI bridge  */
-	0,	/* Slot 10 - unused */
-	0,	/* Slot 11 - unused */
-	3,	/* Slot 12 - SCSI - NCR825A */
-	0,	/* Slot 13 - unused */
-	1,	/* Slot 14 - Ethernet - DEC2104X */
-	0,	/* Slot 15 - unused */
-	1,	/* Slot 16 - PCI slot 1 */
-	2,	/* Slot 17 - PCI slot 2 */
-	3,	/* Slot 18 - PCI slot 3 */
-	4,	/* Slot 19 - PCI bridge */
-	0,
-	0,
-	0,
-};
-
-static char Comet2_pci_IRQ_routes[] =
-{
-	0,	/* Line 0 - Unused */
-	10,	/* Line 1 */
-	11,	/* Line 2 */
-	14,	/* Line 3 */
-	15,	/* Line 4 */
-};
-
-/*
- * ibm 830 (and 850?).
- * This is actually based on the Carolina motherboard
- * -- Cort
- */
-static char ibm8xx_pci_IRQ_map[23] = {
-        0, /* Slot 0  - unused */
-        0, /* Slot 1  - unused */
-        0, /* Slot 2  - unused */
-        0, /* Slot 3  - unused */
-        0, /* Slot 4  - unused */
-        0, /* Slot 5  - unused */
-        0, /* Slot 6  - unused */
-        0, /* Slot 7  - unused */
-        0, /* Slot 8  - unused */
-        0, /* Slot 9  - unused */
-        0, /* Slot 10 - unused */
-        0, /* Slot 11 - FireCoral */
-        4, /* Slot 12 - Ethernet  PCIINTD# */
-        2, /* Slot 13 - PCI Slot #2 */
-        2, /* Slot 14 - S3 Video PCIINTD# */
-        0, /* Slot 15 - onboard SCSI (INDI) [1] */
-        3, /* Slot 16 - NCR58C810 RS6000 Only PCIINTC# */
-        0, /* Slot 17 - unused */
-        2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
-        0, /* Slot 19 - unused */
-        0, /* Slot 20 - unused */
-        0, /* Slot 21 - unused */
-        2, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
-};
-
-static char ibm8xx_pci_IRQ_routes[] = {
-        0,      /* Line 0 - unused */
-        15,     /* Line 1 */
-        15,     /* Line 2 */
-        15,     /* Line 3 */
-        15,     /* Line 4 */
-};
-
-/*
- * a 6015 ibm board
- * -- Cort
- */
-static char ibm6015_pci_IRQ_map[23] = {
-        0, /* Slot 0  - unused */
-        0, /* Slot 1  - unused */
-        0, /* Slot 2  - unused */
-        0, /* Slot 3  - unused */
-        0, /* Slot 4  - unused */
-        0, /* Slot 5  - unused */
-        0, /* Slot 6  - unused */
-        0, /* Slot 7  - unused */
-        0, /* Slot 8  - unused */
-        0, /* Slot 9  - unused */
-        0, /* Slot 10 - unused */
-        0, /* Slot 11 -  */
-        1, /* Slot 12 - SCSI */
-        2, /* Slot 13 -  */
-        2, /* Slot 14 -  */
-        1, /* Slot 15 -  */
-        1, /* Slot 16 -  */
-        0, /* Slot 17 -  */
-        2, /* Slot 18 -  */
-        0, /* Slot 19 -  */
-        0, /* Slot 20 -  */
-        0, /* Slot 21 -  */
-        2, /* Slot 22 -  */
-};
-
-static char ibm6015_pci_IRQ_routes[] = {
-        0,      /* Line 0 - unused */
-        13,     /* Line 1 */
-        15,     /* Line 2 */
-        15,     /* Line 3 */
-        15,     /* Line 4 */
-};
-
-
-/* IBM Nobis and Thinkpad 850 */
-static char Nobis_pci_IRQ_map[23] ={
-        0, /* Slot 0  - unused */
-        0, /* Slot 1  - unused */
-        0, /* Slot 2  - unused */
-        0, /* Slot 3  - unused */
-        0, /* Slot 4  - unused */
-        0, /* Slot 5  - unused */
-        0, /* Slot 6  - unused */
-        0, /* Slot 7  - unused */
-        0, /* Slot 8  - unused */
-        0, /* Slot 9  - unused */
-        0, /* Slot 10 - unused */
-        0, /* Slot 11 - unused */
-        3, /* Slot 12 - SCSI */
-        0, /* Slot 13 - unused */
-        0, /* Slot 14 - unused */
-        0, /* Slot 15 - unused */
-};
-
-static char Nobis_pci_IRQ_routes[] = {
-        0, /* Line 0 - Unused */
-        13, /* Line 1 */
-        13, /* Line 2 */
-        13, /* Line 3 */
-        13      /* Line 4 */
-};
-
-/*
- * IBM RS/6000 43p/140  -- paulus
- * XXX we should get all this from the residual data
- */
-static char ibm43p_pci_IRQ_map[23] = {
-        0, /* Slot 0  - unused */
-        0, /* Slot 1  - unused */
-        0, /* Slot 2  - unused */
-        0, /* Slot 3  - unused */
-        0, /* Slot 4  - unused */
-        0, /* Slot 5  - unused */
-        0, /* Slot 6  - unused */
-        0, /* Slot 7  - unused */
-        0, /* Slot 8  - unused */
-        0, /* Slot 9  - unused */
-        0, /* Slot 10 - unused */
-        0, /* Slot 11 - FireCoral ISA bridge */
-        6, /* Slot 12 - Ethernet  */
-        0, /* Slot 13 - openpic */
-        0, /* Slot 14 - unused */
-        0, /* Slot 15 - unused */
-        7, /* Slot 16 - NCR58C825a onboard scsi */
-        0, /* Slot 17 - unused */
-        2, /* Slot 18 - PCI Slot 2 PCIINTx# (See below) */
-        0, /* Slot 19 - unused */
-        0, /* Slot 20 - unused */
-        0, /* Slot 21 - unused */
-        1, /* Slot 22 - PCI slot 1 PCIINTx# (See below) */
-};
-
-static char ibm43p_pci_IRQ_routes[] = {
-        0,      /* Line 0 - unused */
-        15,     /* Line 1 */
-        15,     /* Line 2 */
-        15,     /* Line 3 */
-        15,     /* Line 4 */
-};
-
-/* Motorola PowerPlus architecture PCI IRQ tables */
-/* Interrupt line values for INTA-D on primary/secondary MPIC inputs */
-
-struct powerplus_irq_list
-{
-	unsigned char primary[4];       /* INT A-D */
-	unsigned char secondary[4];     /* INT A-D */
-};
-
-/*
- * For standard PowerPlus boards, bus 0 PCI INTs A-D are routed to
- * OpenPIC inputs 9-12.  PCI INTs A-D from the on board P2P bridge
- * are routed to OpenPIC inputs 5-8.  These values are offset by
- * 16 in the table to reflect the Linux kernel interrupt value.
- */
-struct powerplus_irq_list Powerplus_pci_IRQ_list =
-{
-	{25, 26, 27, 28},
-	{21, 22, 23, 24}
-};
-
-/*
- * For the MCP750 (system slot board), cPCI INTs A-D are routed to
- * OpenPIC inputs 8-11 and the PMC INTs A-D are routed to OpenPIC
- * input 3.  On a hot swap MCP750, the companion card PCI INTs A-D
- * are routed to OpenPIC inputs 12-15. These values are offset by
- * 16 in the table to reflect the Linux kernel interrupt value.
- */
-struct powerplus_irq_list Mesquite_pci_IRQ_list =
-{
-	{24, 25, 26, 27},
-	{28, 29, 30, 31}
-};
-
-/*
- * This table represents the standard PCI swizzle defined in the
- * PCI bus specification.
- */
-static unsigned char prep_pci_intpins[4][4] =
-{
-	{ 1, 2, 3, 4},  /* Buses 0, 4, 8, ... */
-	{ 2, 3, 4, 1},  /* Buses 1, 5, 9, ... */
-	{ 3, 4, 1, 2},  /* Buses 2, 6, 10 ... */
-	{ 4, 1, 2, 3},  /* Buses 3, 7, 11 ... */
-};
-
-/* We have to turn on LEVEL mode for changed IRQs */
-/* All PCI IRQs need to be level mode, so this should be something
- * other than hard-coded as well... IRQs are individually mappable
- * to either edge or level.
- */
-
-/*
- * 8259 edge/level control definitions
- */
-#define ISA8259_M_ELCR 0x4d0
-#define ISA8259_S_ELCR 0x4d1
-
-#define ELCRS_INT15_LVL         0x80
-#define ELCRS_INT14_LVL         0x40
-#define ELCRS_INT12_LVL         0x10
-#define ELCRS_INT11_LVL         0x08
-#define ELCRS_INT10_LVL         0x04
-#define ELCRS_INT9_LVL          0x02
-#define ELCRS_INT8_LVL          0x01
-#define ELCRM_INT7_LVL          0x80
-#define ELCRM_INT5_LVL          0x20
-
-#if 0
-/*
- * PCI config space access.
- */
-#define CFGADDR(dev)	((1<<(dev>>3)) | ((dev&7)<<8))
-#define DEVNO(dev)	(dev>>3)
-
-#define MIN_DEVNR	11
-#define MAX_DEVNR	22
-
-static int
-prep_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
-		 int len, u32 *val)
-{
-	struct pci_controller *hose = bus->sysdata;
-	volatile void __iomem *cfg_data;
-
-	if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR
-	    || DEVNO(devfn) > MAX_DEVNR)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	/*
-	 * Note: the caller has already checked that offset is
-	 * suitably aligned and that len is 1, 2 or 4.
-	 */
-	cfg_data = hose->cfg_data + CFGADDR(devfn) + offset;
-	switch (len) {
-	case 1:
-		*val = in_8(cfg_data);
-		break;
-	case 2:
-		*val = in_le16(cfg_data);
-		break;
-	default:
-		*val = in_le32(cfg_data);
-		break;
-	}
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static int
-prep_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
-		  int len, u32 val)
-{
-	struct pci_controller *hose = bus->sysdata;
-	volatile void __iomem *cfg_data;
-
-	if (bus->number != 0 || DEVNO(devfn) < MIN_DEVNR
-	    || DEVNO(devfn) > MAX_DEVNR)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	/*
-	 * Note: the caller has already checked that offset is
-	 * suitably aligned and that len is 1, 2 or 4.
-	 */
-	cfg_data = hose->cfg_data + CFGADDR(devfn) + offset;
-	switch (len) {
-	case 1:
-		out_8(cfg_data, val);
-		break;
-	case 2:
-		out_le16(cfg_data, val);
-		break;
-	default:
-		out_le32(cfg_data, val);
-		break;
-	}
-	return PCIBIOS_SUCCESSFUL;
-}
-
-static struct pci_ops prep_pci_ops =
-{
-	prep_read_config,
-	prep_write_config
-};
-#endif
-
-#define MOTOROLA_CPUTYPE_REG	0x800
-#define MOTOROLA_BASETYPE_REG	0x803
-#define MPIC_RAVEN_ID		0x48010000
-#define	MPIC_HAWK_ID		0x48030000
-#define	MOT_PROC2_BIT		0x800
-
-static u_char prep_openpic_initsenses[] __initdata = {
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* MVME2600_INT_SIO */
-    (IRQ_SENSE_EDGE  | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_FALCN_ECC_ERR */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_ETHERNET */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_SCSI */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_GRAPHICS */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME0 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME1 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME2 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_VME3 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTA */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTB */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTC */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_PCI_INTD */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG0 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* MVME2600_INT_LM_SIG1 */
-};
-
-#define MOT_RAVEN_PRESENT	0x1
-#define MOT_HAWK_PRESENT	0x2
-
-int mot_entry = -1;
-int prep_keybd_present = 1;
-int MotMPIC;
-int mot_multi;
-
-int __init
-raven_init(void)
-{
-	unsigned int	devid;
-	unsigned int	pci_membase;
-	unsigned char	base_mod;
-
-	/* Check to see if the Raven chip exists. */
-	if ( _prep_type != _PREP_Motorola) {
-		OpenPIC_Addr = NULL;
-		return 0;
-	}
-
-	/* Check to see if this board is a type that might have a Raven. */
-	if ((inb(MOTOROLA_CPUTYPE_REG) & 0xF0) != 0xE0) {
-		OpenPIC_Addr = NULL;
-		return 0;
-	}
-
-	/* Check the first PCI device to see if it is a Raven. */
-	early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &devid);
-
-	switch (devid & 0xffff0000) {
-	case MPIC_RAVEN_ID:
-		MotMPIC = MOT_RAVEN_PRESENT;
-		break;
-	case MPIC_HAWK_ID:
-		MotMPIC = MOT_HAWK_PRESENT;
-		break;
-	default:
-		OpenPIC_Addr = NULL;
-		return 0;
-	}
-
-
-	/* Read the memory base register. */
-	early_read_config_dword(NULL, 0, 0, PCI_BASE_ADDRESS_1, &pci_membase);
-
-	if (pci_membase == 0) {
-		OpenPIC_Addr = NULL;
-		return 0;
-	}
-
-	/* Map the Raven MPIC registers to virtual memory. */
-	OpenPIC_Addr = ioremap(pci_membase+0xC0000000, 0x22000);
-
-	OpenPIC_InitSenses = prep_openpic_initsenses;
-	OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
-
-	ppc_md.get_irq = openpic_get_irq;
-
-	/* If raven is present on Motorola store the system config register
-	 * for later use.
-	 */
-	ProcInfo = (unsigned long *)ioremap(0xfef80400, 4);
-
-	/* Indicate to system if this is a multiprocessor board */
-	if (!(*ProcInfo & MOT_PROC2_BIT)) {
-		mot_multi = 1;
-	}
-
-	/* This is a hack.  If this is a 2300 or 2400 mot board then there is
-	 * no keyboard controller and we have to indicate that.
-	 */
-	base_mod = inb(MOTOROLA_BASETYPE_REG);
-	if ((MotMPIC == MOT_HAWK_PRESENT) || (base_mod == 0xF9) ||
-	    (base_mod == 0xFA) || (base_mod == 0xE1))
-		prep_keybd_present = 0;
-
-	return 1;
-}
-
-struct mot_info {
-	int		cpu_type;	/* 0x100 mask assumes for Raven and Hawk boards that the level/edge are set */
-					/* 0x200 if this board has a Hawk chip. */
-	int		base_type;
-	int		max_cpu;	/* ored with 0x80 if this board should be checked for multi CPU */
-	const char	*name;
-	unsigned char	*map;
-	unsigned char	*routes;
-	void            (*map_non0_bus)(struct pci_dev *);      /* For boards with more than bus 0 devices. */
-	struct powerplus_irq_list *pci_irq_list; /* List of PCI MPIC inputs */
-	unsigned char   secondary_bridge_devfn; /* devfn of secondary bus transparent bridge */
-} mot_info[] = {
-	{0x300, 0x00, 0x00, "MVME 2400",			Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x010, 0x00, 0x00, "Genesis",				Genesis_pci_IRQ_map,	Genesis_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
-	{0x020, 0x00, 0x00, "Powerstack (Series E)",		Comet_pci_IRQ_map,	Comet_pci_IRQ_routes, NULL, NULL, 0x00},
-	{0x040, 0x00, 0x00, "Blackhawk (Powerstack)",		Blackhawk_pci_IRQ_map,	Blackhawk_pci_IRQ_routes, NULL, NULL, 0x00},
-	{0x050, 0x00, 0x00, "Omaha (PowerStack II Pro3000)",	Omaha_pci_IRQ_map,	Omaha_pci_IRQ_routes, NULL, NULL, 0x00},
-	{0x060, 0x00, 0x00, "Utah (Powerstack II Pro4000)",	Utah_pci_IRQ_map,	Utah_pci_IRQ_routes, NULL, NULL, 0x00},
-	{0x0A0, 0x00, 0x00, "Powerstack (Series EX)",		Comet2_pci_IRQ_map,	Comet2_pci_IRQ_routes, NULL, NULL, 0x00},
-	{0x1E0, 0xE0, 0x00, "Mesquite cPCI (MCP750)",		Mesquite_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xE1, 0x00, "Sitka cPCI (MCPN750)",		Sitka_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xE2, 0x00, "Mesquite cPCI (MCP750) w/ HAC",	Mesquite_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Mesquite_pci_IRQ_list, 0xC0},
-	{0x1E0, 0xF6, 0x80, "MTX Plus",				MTXplus_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
-	{0x1E0, 0xF6, 0x81, "Dual MTX Plus",			MTXplus_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xA0},
-	{0x1E0, 0xF7, 0x80, "MTX wo/ Parallel Port",		MTX_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
-	{0x1E0, 0xF7, 0x81, "Dual MTX wo/ Parallel Port",	MTX_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
-	{0x1E0, 0xF8, 0x80, "MTX w/ Parallel Port",		MTX_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
-	{0x1E0, 0xF8, 0x81, "Dual MTX w/ Parallel Port",	MTX_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
-	{0x1E0, 0xF9, 0x00, "MVME 2300",			Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xFA, 0x00, "MVME 2300SC/2600",			Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xFB, 0x00, "MVME 2600 with MVME712M",		Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xFC, 0x00, "MVME 2600/2700 with MVME761",	Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xFD, 0x80, "MVME 3600 with MVME712M",		Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0x00},
-	{0x1E0, 0xFD, 0x81, "MVME 4600 with MVME712M",		Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xFE, 0x80, "MVME 3600 with MVME761",		Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xFE, 0x81, "MVME 4600 with MVME761",		Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x1E0, 0xFF, 0x00, "MVME 1600-001 or 1600-011",	Genesis2_pci_IRQ_map,	Raven_pci_IRQ_routes, Powerplus_Map_Non0, &Powerplus_pci_IRQ_list, 0xFF},
-	{0x000, 0x00, 0x00, "",					NULL,			NULL, NULL, NULL, 0x00}
-};
-
-void __init
-ibm_prep_init(void)
-{
-	if (have_residual_data) {
-		u32 addr, real_addr, len, offset;
-		PPC_DEVICE *mpic;
-		PnP_TAG_PACKET *pkt;
-
-		/* Use the PReP residual data to determine if an OpenPIC is
-		 * present.  If so, get the large vendor packet which will
-		 * tell us the base address and length in memory.
-		 * If we are successful, ioremap the memory area and set
-		 * OpenPIC_Addr (this indicates that the OpenPIC was found).
-		 */
-		mpic = residual_find_device(-1, NULL, SystemPeripheral,
-				    ProgrammableInterruptController, MPIC, 0);
-		if (!mpic)
-			return;
-
-		pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap +
-				mpic->AllocatedOffset, 9, 0);
-
-		if (!pkt)
-			return;
-
-#define p pkt->L4_Pack.L4_Data.L4_PPCPack
-	 	if (p.PPCData[1] == 32) {
-			switch (p.PPCData[0]) {
-				case 1:  offset = PREP_ISA_IO_BASE;  break;
-				case 2:  offset = PREP_ISA_MEM_BASE; break;
-				default: return; /* Not I/O or memory?? */
-			}
-		}
-		else
-			return; /* Not a 32-bit address */
-
-		real_addr = ld_le32((unsigned int *) (p.PPCData + 4));
-		if (real_addr == 0xffffffff)
-			return;
-
-		/* Adjust address to be as seen by CPU */
-		addr = real_addr + offset;
-
-		len = ld_le32((unsigned int *) (p.PPCData + 12));
-		if (!len)
-			return;
-#undef p
-		OpenPIC_Addr = ioremap(addr, len);
-		ppc_md.get_irq = openpic_get_irq;
-
-		OpenPIC_InitSenses = prep_openpic_initsenses;
-		OpenPIC_NumInitSenses = sizeof(prep_openpic_initsenses);
-
-		printk(KERN_INFO "MPIC at 0x%08x (0x%08x), length 0x%08x "
-		       "mapped to 0x%p\n", addr, real_addr, len, OpenPIC_Addr);
-	}
-}
-
-static void __init
-ibm43p_pci_map_non0(struct pci_dev *dev)
-{
-	unsigned char intpin;
-	static unsigned char bridge_intrs[4] = { 3, 4, 5, 8 };
-
-	if (dev == NULL)
-		return;
-	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin);
-	if (intpin < 1 || intpin > 4)
-		return;
-	intpin = (PCI_SLOT(dev->devfn) + intpin - 1) & 3;
-	dev->irq = openpic_to_irq(bridge_intrs[intpin]);
-	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-}
-
-void __init
-prep_residual_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
-{
-	if (have_residual_data) {
-		Motherboard_map_name = res->VitalProductData.PrintableModel;
-		Motherboard_map = NULL;
-		Motherboard_routes = NULL;
-		residual_irq_mask(irq_edge_mask_lo, irq_edge_mask_hi);
-	}
-}
-
-void __init
-prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
-{
-	Motherboard_map_name = "IBM 6015/7020 (Sandalfoot/Sandalbow)";
-	Motherboard_map = ibm6015_pci_IRQ_map;
-	Motherboard_routes = ibm6015_pci_IRQ_routes;
-	*irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
-	*irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
-}
-
-void __init
-prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
-{
-	Motherboard_map_name = "IBM Thinkpad 850/860";
-	Motherboard_map = Nobis_pci_IRQ_map;
-	Motherboard_routes = Nobis_pci_IRQ_routes;
-	*irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
-	*irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
-}
-
-void __init
-prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
-{
-	Motherboard_map_name = "IBM 7248, PowerSeries 830/850 (Carolina)";
-	Motherboard_map = ibm8xx_pci_IRQ_map;
-	Motherboard_routes = ibm8xx_pci_IRQ_routes;
-	*irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
-	*irq_edge_mask_hi = 0xA4; /* IRQs 10, 13, 15 level-triggered */
-}
-
-void __init
-prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
-{
-	Motherboard_map_name = "IBM 43P-140 (Tiger1)";
-	Motherboard_map = ibm43p_pci_IRQ_map;
-	Motherboard_routes = ibm43p_pci_IRQ_routes;
-	Motherboard_non0 = ibm43p_pci_map_non0;
-	*irq_edge_mask_lo = 0x00; /* IRQs 0-7 all edge-triggered */
-	*irq_edge_mask_hi = 0xA0; /* IRQs 13, 15 level-triggered */
-}
-
-void __init
-prep_route_pci_interrupts(void)
-{
-	unsigned char *ibc_pirq = (unsigned char *)0x80800860;
-	unsigned char *ibc_pcicon = (unsigned char *)0x80800840;
-	int i;
-
-	if ( _prep_type == _PREP_Motorola)
-	{
-		unsigned short irq_mode;
-		unsigned char  cpu_type;
-		unsigned char  base_mod;
-		int	       entry;
-
-		cpu_type = inb(MOTOROLA_CPUTYPE_REG) & 0xF0;
-		base_mod = inb(MOTOROLA_BASETYPE_REG);
-
-		for (entry = 0; mot_info[entry].cpu_type != 0; entry++) {
-			if (mot_info[entry].cpu_type & 0x200) {		 	/* Check for Hawk chip */
-				if (!(MotMPIC & MOT_HAWK_PRESENT))
-					continue;
-			} else {						/* Check non hawk boards */
-				if ((mot_info[entry].cpu_type & 0xff) != cpu_type)
-					continue;
-
-				if (mot_info[entry].base_type == 0) {
-					mot_entry = entry;
-					break;
-				}
-
-				if (mot_info[entry].base_type != base_mod)
-					continue;
-			}
-
-			if (!(mot_info[entry].max_cpu & 0x80)) {
-				mot_entry = entry;
-				break;
-			}
-
-			/* processor 1 not present and max processor zero indicated */
-			if ((*ProcInfo & MOT_PROC2_BIT) && !(mot_info[entry].max_cpu & 0x7f)) {
-				mot_entry = entry;
-				break;
-			}
-
-			/* processor 1 present and max processor zero indicated */
-			if (!(*ProcInfo & MOT_PROC2_BIT) && (mot_info[entry].max_cpu & 0x7f)) {
-				mot_entry = entry;
-				break;
-			}
-		}
-
-		if (mot_entry == -1) 	/* No particular cpu type found - assume Blackhawk */
-			mot_entry = 3;
-
-		Motherboard_map_name = (unsigned char *)mot_info[mot_entry].name;
-		Motherboard_map = mot_info[mot_entry].map;
-		Motherboard_routes = mot_info[mot_entry].routes;
-		Motherboard_non0 = mot_info[mot_entry].map_non0_bus;
-
-		if (!(mot_info[entry].cpu_type & 0x100)) {
-			/* AJF adjust level/edge control according to routes */
-			irq_mode = 0;
-			for (i = 1;  i <= 4;  i++)
-				irq_mode |= ( 1 << Motherboard_routes[i] );
-			outb( irq_mode & 0xff, 0x4d0 );
-			outb( (irq_mode >> 8) & 0xff, 0x4d1 );
-		}
-	} else if ( _prep_type == _PREP_IBM ) {
-		unsigned char irq_edge_mask_lo, irq_edge_mask_hi;
-		unsigned short irq_edge_mask;
-		int i;
-
-		setup_ibm_pci(&irq_edge_mask_lo, &irq_edge_mask_hi);
-
-		outb(inb(0x04d0)|irq_edge_mask_lo, 0x4d0); /* primary 8259 */
-		outb(inb(0x04d1)|irq_edge_mask_hi, 0x4d1); /* cascaded 8259 */
-
-		irq_edge_mask = (irq_edge_mask_hi << 8) | irq_edge_mask_lo;
-		for (i = 0; i < 16; ++i, irq_edge_mask >>= 1)
-			if (irq_edge_mask & 1)
-				irq_desc[i].status |= IRQ_LEVEL;
-	} else {
-		printk("No known machine pci routing!\n");
-		return;
-	}
-
-	/* Set up mapping from slots */
-	if (Motherboard_routes) {
-		for (i = 1;  i <= 4;  i++)
-			ibc_pirq[i-1] = Motherboard_routes[i];
-
-		/* Enable PCI interrupts */
-		*ibc_pcicon |= 0x20;
-	}
-}
-
-void __init
-prep_pib_init(void)
-{
-	unsigned char   reg;
-	unsigned short  short_reg;
-
-	struct pci_dev *dev = NULL;
-
-	if (( _prep_type == _PREP_Motorola) && (OpenPIC_Addr)) {
-		/*
-		 * Perform specific configuration for the Via Tech or
-		 * or Winbond PCI-ISA-Bridge part.
-		 */
-		if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
-					PCI_DEVICE_ID_VIA_82C586_1, dev))) {
-			/*
-			 * PPCBUG does not set the enable bits
-			 * for the IDE device. Force them on here.
-			 */
-			pci_read_config_byte(dev, 0x40, &reg);
-
-			reg |= 0x03; /* IDE: Chip Enable Bits */
-			pci_write_config_byte(dev, 0x40, reg);
-		}
-		if ((dev = pci_get_device(PCI_VENDOR_ID_VIA,
-						PCI_DEVICE_ID_VIA_82C586_2,
-						dev)) && (dev->devfn = 0x5a)) {
-			/* Force correct USB interrupt */
-			dev->irq = 11;
-			pci_write_config_byte(dev,
-					PCI_INTERRUPT_LINE,
-					dev->irq);
-		}
-		if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
-					PCI_DEVICE_ID_WINBOND_83C553, dev))) {
-			 /* Clear PCI Interrupt Routing Control Register. */
-			short_reg = 0x0000;
-			pci_write_config_word(dev, 0x44, short_reg);
-			if (OpenPIC_Addr){
-				/* Route IDE interrupts to IRQ 14 */
-				reg = 0xEE;
-				pci_write_config_byte(dev, 0x43, reg);
-			}
-		}
-	}
-
-	if ((dev = pci_get_device(PCI_VENDOR_ID_WINBOND,
-				   PCI_DEVICE_ID_WINBOND_82C105, dev))){
-		if (OpenPIC_Addr){
-			/*
-			 * Disable LEGIRQ mode so PCI INTS are routed
-			 * directly to the 8259 and enable both channels
-			 */
-			pci_write_config_dword(dev, 0x40, 0x10ff0033);
-
-			/* Force correct IDE interrupt */
-			dev->irq = 14;
-			pci_write_config_byte(dev,
-					PCI_INTERRUPT_LINE,
-					dev->irq);
-		} else {
-			/* Enable LEGIRQ for PCI INT -> 8259 IRQ routing */
-			pci_write_config_dword(dev, 0x40, 0x10ff08a1);
-		}
-	}
-	pci_dev_put(dev);
-}
-
-static void __init
-Powerplus_Map_Non0(struct pci_dev *dev)
-{
-	struct pci_bus  *pbus;          /* Parent bus structure pointer */
-	struct pci_dev  *tdev = dev;    /* Temporary device structure */
-	unsigned int    devnum;         /* Accumulated device number */
-	unsigned char   intline;        /* Linux interrupt value */
-	unsigned char   intpin;         /* PCI interrupt pin */
-
-	/* Check for valid PCI dev pointer */
-	if (dev == NULL) return;
-
-	/* Initialize bridge IDSEL variable */
-	devnum = PCI_SLOT(tdev->devfn);
-
-	/* Read the interrupt pin of the device and adjust for indexing */
-	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &intpin);
-
-	/* If device doesn't request an interrupt, return */
-	if ( (intpin < 1) || (intpin > 4) )
-		return;
-
-	intpin--;
-
-	/*
-	 * Walk up to bus 0, adjusting the interrupt pin for the standard
-	 * PCI bus swizzle.
-	 */
-	do {
-		intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
-		pbus = tdev->bus;        /* up one level */
-		tdev = pbus->self;
-		devnum = PCI_SLOT(tdev->devfn);
-	} while(tdev->bus->number);
-
-	/* Use the primary interrupt inputs by default */
-	intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
-
-	/*
-	 * If the board has secondary interrupt inputs, walk the bus and
-	 * note the devfn of the bridge from bus 0.  If it is the same as
-	 * the devfn of the bus bridge with secondary inputs, use those.
-	 * Otherwise, assume it's a PMC site and get the interrupt line
-	 * value from the interrupt routing table.
-	 */
-	if (mot_info[mot_entry].secondary_bridge_devfn) {
-		pbus = dev->bus;
-
-		while (pbus->primary != 0)
-			pbus = pbus->parent;
-
-		if ((pbus->self)->devfn != 0xA0) {
-			if ((pbus->self)->devfn == mot_info[mot_entry].secondary_bridge_devfn)
-				intline = mot_info[mot_entry].pci_irq_list->secondary[intpin];
-			else {
-				if ((char *)(mot_info[mot_entry].map) == (char *)Mesquite_pci_IRQ_map)
-					intline = mot_info[mot_entry].map[((pbus->self)->devfn)/8] + 16;
-				else {
-					int i;
-					for (i=0;i<3;i++)
-						intpin = (prep_pci_intpins[devnum % 4][intpin]) - 1;
-					intline = mot_info[mot_entry].pci_irq_list->primary[intpin];
-				}
-			}
-		}
-	}
-
-	/* Write calculated interrupt value to header and device list */
-	dev->irq = intline;
-	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, (u8)dev->irq);
-}
-
-void __init
-prep_pcibios_fixup(void)
-{
-        struct pci_dev *dev = NULL;
-	int irq;
-	int have_openpic = (OpenPIC_Addr != NULL);
-
-	prep_route_pci_interrupts();
-
-	printk("Setting PCI interrupts for a \"%s\"\n", Motherboard_map_name);
-
-	/* Iterate through all the PCI devices, setting the IRQ */
-	for_each_pci_dev(dev) {
-		/*
-		 * If we have residual data, then this is easy: query the
-		 * residual data for the IRQ line allocated to the device.
-		 * This works the same whether we have an OpenPic or not.
-		 */
-		if (have_residual_data) {
-			irq = residual_pcidev_irq(dev);
-			dev->irq = have_openpic ? openpic_to_irq(irq) : irq;
-		}
-		/*
-		 * If we don't have residual data, then we need to use
-		 * tables to determine the IRQ.  The table organisation
-		 * is different depending on whether there is an OpenPIC
-		 * or not.  The tables are only used for bus 0, so check
-		 * this first.
-		 */
-		else if (dev->bus->number == 0) {
-			irq = Motherboard_map[PCI_SLOT(dev->devfn)];
-			dev->irq = have_openpic ? openpic_to_irq(irq)
-						: Motherboard_routes[irq];
-		}
-		/*
-		 * Finally, if we don't have residual data and the bus is
-		 * non-zero, use the callback (if provided)
-		 */
-		else {
-			if (Motherboard_non0 != NULL)
-				Motherboard_non0(dev);
-
-			continue;
-		}
-
-		pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
-	}
-
-	/* Setup the Winbond or Via PIB - prep_pib_init() is coded for
-	 * the non-openpic case, but it breaks (at least) the Utah
-	 * (Powerstack II Pro4000), so only call it if we have an
-	 * openpic.
-	 */
-	if (have_openpic)
-		prep_pib_init();
-}
-
-static void __init
-prep_pcibios_after_init(void)
-{
-#if 0
-	struct pci_dev *dev;
-
-	/* If there is a WD 90C, reset the IO BAR to 0x0 (it started that
-	 * way, but the PCI layer relocated it because it thought 0x0 was
-	 * invalid for a BAR).
-	 * If you don't do this, the card's VGA base will be <IO BAR>+0xc0000
-	 * instead of 0xc0000. vgacon.c (for example) is completely unaware of
-	 * this little quirk.
-	 */
-	dev = pci_get_device(PCI_VENDOR_ID_WD, PCI_DEVICE_ID_WD_90C, NULL);
-	if (dev) {
-		dev->resource[1].end -= dev->resource[1].start;
-		dev->resource[1].start = 0;
-		/* tell the hardware */
-		pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0x0);
-		pci_dev_put(dev);
-	}
-#endif
-}
-
-static void __init
-prep_init_resource(struct resource *res, unsigned long start,
-		   unsigned long end, int flags)
-{
-	res->flags = flags;
-	res->start = start;
-	res->end = end;
-	res->name = "PCI host bridge";
-	res->parent = NULL;
-	res->sibling = NULL;
-	res->child = NULL;
-}
-
-void __init
-prep_find_bridges(void)
-{
-	struct pci_controller* hose;
-
-	hose = pcibios_alloc_controller();
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-	hose->pci_mem_offset = PREP_ISA_MEM_BASE;
-	hose->io_base_phys = PREP_ISA_IO_BASE;
-	hose->io_base_virt = ioremap(PREP_ISA_IO_BASE, 0x800000);
-	prep_init_resource(&hose->io_resource, 0, 0x007fffff, IORESOURCE_IO);
-	prep_init_resource(&hose->mem_resources[0], 0xc0000000, 0xfeffffff,
-			   IORESOURCE_MEM);
-	setup_indirect_pci(hose, PREP_ISA_IO_BASE + 0xcf8,
-			   PREP_ISA_IO_BASE + 0xcfc);
-
-	printk("PReP architecture\n");
-
-	if (have_residual_data) {
-		PPC_DEVICE *hostbridge;
-
-		hostbridge = residual_find_device(PROCESSORDEVICE, NULL,
-			BridgeController, PCIBridge, -1, 0);
-		if (hostbridge &&
-			((hostbridge->DeviceId.Interface == PCIBridgeIndirect) ||
-			 (hostbridge->DeviceId.Interface == PCIBridgeRS6K))) {
-			PnP_TAG_PACKET * pkt;
-			pkt = PnP_find_large_vendor_packet(
-				res->DevicePnPHeap+hostbridge->AllocatedOffset,
-				3, 0);
-			if(pkt) {
-#define p pkt->L4_Pack.L4_Data.L4_PPCPack
-				setup_indirect_pci(hose,
-					ld_le32((unsigned *) (p.PPCData)),
-					ld_le32((unsigned *) (p.PPCData+8)));
-#undef p
-			} else
-				setup_indirect_pci(hose, 0x80000cf8, 0x80000cfc);
-		}
-	}
-
-	ppc_md.pcibios_fixup = prep_pcibios_fixup;
-	ppc_md.pcibios_after_init = prep_pcibios_after_init;
-}
diff --git a/arch/ppc/platforms/prep_setup.c b/arch/ppc/platforms/prep_setup.c
deleted file mode 100644
index 465b658c927..00000000000
--- a/arch/ppc/platforms/prep_setup.c
+++ /dev/null
@@ -1,1043 +0,0 @@
-/*
- *  Copyright (C) 1995  Linus Torvalds
- *  Adapted from 'alpha' version by Gary Thomas
- *  Modified by Cort Dougan (cort@cs.nmt.edu)
- *
- * Support for PReP (Motorola MTX/MVME)
- * by Troy Benjegerdes (hozer@drgw.net)
- */
-
-/*
- * bootup setup stuff..
- */
-
-#include <linux/delay.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/user.h>
-#include <linux/a.out.h>
-#include <linux/screen_info.h>
-#include <linux/major.h>
-#include <linux/interrupt.h>
-#include <linux/reboot.h>
-#include <linux/init.h>
-#include <linux/initrd.h>
-#include <linux/ioport.h>
-#include <linux/console.h>
-#include <linux/timex.h>
-#include <linux/pci.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-
-#include <asm/sections.h>
-#include <asm/mmu.h>
-#include <asm/processor.h>
-#include <asm/residual.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/cache.h>
-#include <asm/dma.h>
-#include <asm/machdep.h>
-#include <asm/mc146818rtc.h>
-#include <asm/mk48t59.h>
-#include <asm/prep_nvram.h>
-#include <asm/raven.h>
-#include <asm/vga.h>
-#include <asm/time.h>
-#include <asm/mpc10x.h>
-#include <asm/i8259.h>
-#include <asm/open_pic.h>
-#include <asm/pci-bridge.h>
-#include <asm/todc.h>
-
-/* prep registers for L2 */
-#define CACHECRBA       0x80000823      /* Cache configuration register address */
-#define L2CACHE_MASK	0x03	/* Mask for 2 L2 Cache bits */
-#define L2CACHE_512KB	0x00	/* 512KB */
-#define L2CACHE_256KB	0x01	/* 256KB */
-#define L2CACHE_1MB	0x02	/* 1MB */
-#define L2CACHE_NONE	0x03	/* NONE */
-#define L2CACHE_PARITY  0x08    /* Mask for L2 Cache Parity Protected bit */
-
-TODC_ALLOC();
-
-extern unsigned char prep_nvram_read_val(int addr);
-extern void prep_nvram_write_val(int addr,
-				 unsigned char val);
-extern unsigned char rs_nvram_read_val(int addr);
-extern void rs_nvram_write_val(int addr,
-				 unsigned char val);
-extern void ibm_prep_init(void);
-
-extern void prep_find_bridges(void);
-
-int _prep_type;
-
-extern void prep_residual_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
-extern void prep_sandalfoot_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
-extern void prep_thinkpad_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
-extern void prep_carolina_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
-extern void prep_tiger1_setup_pci(char *irq_edge_mask_lo, char *irq_edge_mask_hi);
-
-
-#define cached_21	(((char *)(ppc_cached_irq_mask))[3])
-#define cached_A1	(((char *)(ppc_cached_irq_mask))[2])
-
-extern PTE *Hash, *Hash_end;
-extern unsigned long Hash_size, Hash_mask;
-extern int probingmem;
-extern unsigned long loops_per_jiffy;
-
-/* useful ISA ports */
-#define PREP_SYSCTL	0x81c
-/* present in the IBM reference design; possibly identical in Mot boxes: */
-#define PREP_IBM_SIMM_ID	0x803	/* SIMM size: 32 or 8 MiB */
-#define PREP_IBM_SIMM_PRESENCE	0x804
-#define PREP_IBM_EQUIPMENT	0x80c
-#define PREP_IBM_L2INFO	0x80d
-#define PREP_IBM_PM1	0x82a	/* power management register 1 */
-#define PREP_IBM_PLANAR	0x852	/* planar ID - identifies the motherboard */
-#define PREP_IBM_DISP	0x8c0	/* 4-digit LED display */
-
-/* Equipment Present Register masks: */
-#define PREP_IBM_EQUIPMENT_RESERVED	0x80
-#define PREP_IBM_EQUIPMENT_SCSIFUSE	0x40
-#define PREP_IBM_EQUIPMENT_L2_COPYBACK	0x08
-#define PREP_IBM_EQUIPMENT_L2_256	0x04
-#define PREP_IBM_EQUIPMENT_CPU	0x02
-#define PREP_IBM_EQUIPMENT_L2	0x01
-
-/* planar ID values: */
-/* Sandalfoot/Sandalbow (6015/7020) */
-#define PREP_IBM_SANDALFOOT	0xfc
-/* Woodfield, Thinkpad 850/860 (6042/7249) */
-#define PREP_IBM_THINKPAD	0xff /* planar ID unimplemented */
-/* PowerSeries 830/850 (6050/6070) */
-#define PREP_IBM_CAROLINA_IDE_0	0xf0
-#define PREP_IBM_CAROLINA_IDE_1	0xf1
-#define PREP_IBM_CAROLINA_IDE_2	0xf2
-#define PREP_IBM_CAROLINA_IDE_3	0xf3
-/* 7248-43P */
-#define PREP_IBM_CAROLINA_SCSI_0	0xf4
-#define PREP_IBM_CAROLINA_SCSI_1	0xf5
-#define PREP_IBM_CAROLINA_SCSI_2	0xf6
-#define PREP_IBM_CAROLINA_SCSI_3	0xf7 /* missing from Carolina Tech Spec */
-/* Tiger1 (7043-140) */
-#define PREP_IBM_TIGER1_133		0xd1
-#define PREP_IBM_TIGER1_166		0xd2
-#define PREP_IBM_TIGER1_180		0xd3
-#define PREP_IBM_TIGER1_xxx		0xd4 /* unknown, but probably exists */
-#define PREP_IBM_TIGER1_333		0xd5 /* missing from Tiger Tech Spec */
-
-/* setup_ibm_pci:
- * 	set Motherboard_map_name, Motherboard_map, Motherboard_routes.
- * 	return 8259 edge/level masks.
- */
-void (*setup_ibm_pci)(char *irq_lo, char *irq_hi);
-
-extern char *Motherboard_map_name; /* for use in *_cpuinfo */
-
-/*
- * As found in the PReP reference implementation.
- * Used by Thinkpad, Sandalfoot (6015/7020), and all Motorola PReP.
- */
-static void __init
-prep_gen_enable_l2(void)
-{
-	outb(inb(PREP_SYSCTL) | 0x3, PREP_SYSCTL);
-}
-
-/* Used by Carolina and Tiger1 */
-static void __init
-prep_carolina_enable_l2(void)
-{
-	outb(inb(PREP_SYSCTL) | 0xc0, PREP_SYSCTL);
-}
-
-/* cpuinfo code common to all IBM PReP */
-static void
-prep_ibm_cpuinfo(struct seq_file *m)
-{
-	unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
-
-	seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name);
-
-	seq_printf(m, "upgrade cpu\t: ");
-	if (equip_reg & PREP_IBM_EQUIPMENT_CPU) {
-		seq_printf(m, "not ");
-	}
-	seq_printf(m, "present\n");
-
-	/* print info about the SCSI fuse */
-	seq_printf(m, "scsi fuse\t: ");
-	if (equip_reg & PREP_IBM_EQUIPMENT_SCSIFUSE)
-		seq_printf(m, "ok");
-	else
-		seq_printf(m, "bad");
-	seq_printf(m, "\n");
-
-	/* print info about SIMMs */
-	if (have_residual_data) {
-		int i;
-		seq_printf(m, "simms\t\t: ");
-		for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
-			if (res->Memories[i].SIMMSize != 0)
-				seq_printf(m, "%d:%ldMiB ", i,
-					(res->Memories[i].SIMMSize > 1024) ?
-					res->Memories[i].SIMMSize>>20 :
-					res->Memories[i].SIMMSize);
-		}
-		seq_printf(m, "\n");
-	}
-}
-
-static int
-prep_gen_cpuinfo(struct seq_file *m)
-{
-	prep_ibm_cpuinfo(m);
-	return 0;
-}
-
-static int
-prep_sandalfoot_cpuinfo(struct seq_file *m)
-{
-	unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
-
-	prep_ibm_cpuinfo(m);
-
-	/* report amount and type of L2 cache present */
-	seq_printf(m, "L2 cache\t: ");
-	if (equip_reg & PREP_IBM_EQUIPMENT_L2) {
-		seq_printf(m, "not present");
-	} else {
-		if (equip_reg & PREP_IBM_EQUIPMENT_L2_256)
-			seq_printf(m, "256KiB");
-		else
-			seq_printf(m, "unknown size");
-
-		if (equip_reg & PREP_IBM_EQUIPMENT_L2_COPYBACK)
-			seq_printf(m, ", copy-back");
-		else
-			seq_printf(m, ", write-through");
-	}
-	seq_printf(m, "\n");
-
-	return 0;
-}
-
-static int
-prep_thinkpad_cpuinfo(struct seq_file *m)
-{
-	unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
-	char *cpubus_speed, *pci_speed;
-
-	prep_ibm_cpuinfo(m);
-
-	/* report amount and type of L2 cache present */
-	seq_printf(m, "l2 cache\t: ");
-	if ((equip_reg & 0x1) == 0) {
-		switch ((equip_reg & 0xc) >> 2) {
-			case 0x0:
-				seq_printf(m, "128KiB look-aside 2-way write-through\n");
-				break;
-			case 0x1:
-				seq_printf(m, "512KiB look-aside direct-mapped write-back\n");
-				break;
-			case 0x2:
-				seq_printf(m, "256KiB look-aside 2-way write-through\n");
-				break;
-			case 0x3:
-				seq_printf(m, "256KiB look-aside direct-mapped write-back\n");
-				break;
-		}
-	} else {
-		seq_printf(m, "not present\n");
-	}
-
-	/* report bus speeds because we can */
-	if ((equip_reg & 0x80) == 0) {
-		switch ((equip_reg & 0x30) >> 4) {
-			case 0x1:
-				cpubus_speed = "50";
-				pci_speed = "25";
-				break;
-			case 0x3:
-				cpubus_speed = "66";
-				pci_speed = "33";
-				break;
-			default:
-				cpubus_speed = "unknown";
-				pci_speed = "unknown";
-				break;
-		}
-	} else {
-		switch ((equip_reg & 0x30) >> 4) {
-			case 0x1:
-				cpubus_speed = "25";
-				pci_speed = "25";
-				break;
-			case 0x2:
-				cpubus_speed = "60";
-				pci_speed = "30";
-				break;
-			case 0x3:
-				cpubus_speed = "33";
-				pci_speed = "33";
-				break;
-			default:
-				cpubus_speed = "unknown";
-				pci_speed = "unknown";
-				break;
-		}
-	}
-	seq_printf(m, "60x bus\t\t: %sMHz\n", cpubus_speed);
-	seq_printf(m, "pci bus\t\t: %sMHz\n", pci_speed);
-
-	return 0;
-}
-
-static int
-prep_carolina_cpuinfo(struct seq_file *m)
-{
-	unsigned int equip_reg = inb(PREP_IBM_EQUIPMENT);
-
-	prep_ibm_cpuinfo(m);
-
-	/* report amount and type of L2 cache present */
-	seq_printf(m, "l2 cache\t: ");
-	if ((equip_reg & 0x1) == 0) {
-		unsigned int l2_reg = inb(PREP_IBM_L2INFO);
-
-		/* L2 size */
-		if ((l2_reg & 0x60) == 0)
-			seq_printf(m, "256KiB");
-		else if ((l2_reg & 0x60) == 0x20)
-			seq_printf(m, "512KiB");
-		else
-			seq_printf(m, "unknown size");
-
-		/* L2 type */
-		if ((l2_reg & 0x3) == 0)
-			seq_printf(m, ", async");
-		else if ((l2_reg & 0x3) == 1)
-			seq_printf(m, ", sync");
-		else
-			seq_printf(m, ", unknown type");
-
-		seq_printf(m, "\n");
-	} else {
-		seq_printf(m, "not present\n");
-	}
-
-	return 0;
-}
-
-static int
-prep_tiger1_cpuinfo(struct seq_file *m)
-{
-	unsigned int l2_reg = inb(PREP_IBM_L2INFO);
-
-	prep_ibm_cpuinfo(m);
-
-	/* report amount and type of L2 cache present */
-	seq_printf(m, "l2 cache\t: ");
-	if ((l2_reg & 0xf) == 0xf) {
-		seq_printf(m, "not present\n");
-	} else {
-		if (l2_reg & 0x8)
-			seq_printf(m, "async, ");
-		else
-			seq_printf(m, "sync burst, ");
-	
-		if (l2_reg & 0x4)
-			seq_printf(m, "parity, ");
-		else
-			seq_printf(m, "no parity, ");
-	
-		switch (l2_reg & 0x3) {
-			case 0x0:
-				seq_printf(m, "256KiB\n");
-				break;
-			case 0x1:
-				seq_printf(m, "512KiB\n");
-				break;
-			case 0x2:
-				seq_printf(m, "1MiB\n");
-				break;
-			default:
-				seq_printf(m, "unknown size\n");
-				break;
-		}
-	}
-
-	return 0;
-}
-
-
-/* Used by all Motorola PReP */
-static int
-prep_mot_cpuinfo(struct seq_file *m)
-{
-	unsigned int cachew = *((unsigned char *)CACHECRBA);
-
-	seq_printf(m, "machine\t\t: PReP %s\n", Motherboard_map_name);
-
-	/* report amount and type of L2 cache present */
-	seq_printf(m, "l2 cache\t: ");
-	switch (cachew & L2CACHE_MASK) {
-		case L2CACHE_512KB:
-			seq_printf(m, "512KiB");
-			break;
-		case L2CACHE_256KB:
-			seq_printf(m, "256KiB");
-			break;
-		case L2CACHE_1MB:
-			seq_printf(m, "1MiB");
-			break;
-		case L2CACHE_NONE:
-			seq_printf(m, "none\n");
-			goto no_l2;
-			break;
-		default:
-			seq_printf(m, "%x\n", cachew);
-	}
-
-	seq_printf(m, ", parity %s",
-			(cachew & L2CACHE_PARITY)? "enabled" : "disabled");
-
-	seq_printf(m, " SRAM:");
-
-	switch ( ((cachew & 0xf0) >> 4) & ~(0x3) ) {
-		case 1: seq_printf(m, "synchronous, parity, flow-through\n");
-				break;
-		case 2: seq_printf(m, "asynchronous, no parity\n");
-				break;
-		case 3: seq_printf(m, "asynchronous, parity\n");
-				break;
-		default:seq_printf(m, "synchronous, pipelined, no parity\n");
-				break;
-	}
-
-no_l2:
-	/* print info about SIMMs */
-	if (have_residual_data) {
-		int i;
-		seq_printf(m, "simms\t\t: ");
-		for (i = 0; (res->ActualNumMemories) && (i < MAX_MEMS); i++) {
-			if (res->Memories[i].SIMMSize != 0)
-				seq_printf(m, "%d:%ldM ", i,
-					(res->Memories[i].SIMMSize > 1024) ?
-					res->Memories[i].SIMMSize>>20 :
-					res->Memories[i].SIMMSize);
-		}
-		seq_printf(m, "\n");
-	}
-
-	return 0;
-}
-
-static void
-prep_restart(char *cmd)
-{
-#define PREP_SP92	0x92	/* Special Port 92 */
-	local_irq_disable(); /* no interrupts */
-
-	/* set exception prefix high - to the prom */
-	_nmask_and_or_msr(0, MSR_IP);
-
-	/* make sure bit 0 (reset) is a 0 */
-	outb( inb(PREP_SP92) & ~1L , PREP_SP92);
-	/* signal a reset to system control port A - soft reset */
-	outb( inb(PREP_SP92) | 1 , PREP_SP92);
-
-	while ( 1 ) ;
-	/* not reached */
-#undef PREP_SP92
-}
-
-static void
-prep_halt(void)
-{
-	local_irq_disable(); /* no interrupts */
-
-	/* set exception prefix high - to the prom */
-	_nmask_and_or_msr(0, MSR_IP);
-
-	while ( 1 ) ;
-	/* not reached */
-}
-
-/* Carrera is the power manager in the Thinkpads. Unfortunately not much is
- * known about it, so we can't power down.
- */
-static void
-prep_carrera_poweroff(void)
-{
-	prep_halt();
-}
-
-/*
- * On most IBM PReP's, power management is handled by a Signetics 87c750
- * behind the Utah component on the ISA bus. To access the 750 you must write
- * a series of nibbles to port 0x82a (decoded by the Utah). This is described
- * somewhat in the IBM Carolina Technical Specification.
- * -Hollis
- */
-static void
-utah_sig87c750_setbit(unsigned int bytenum, unsigned int bitnum, int value)
-{
-	/*
-	 * byte1: 0 0 0 1 0  d  a5 a4
-	 * byte2: 0 0 0 1 a3 a2 a1 a0
-	 *
-	 * d = the bit's value, enabled or disabled
-	 * (a5 a4 a3) = the byte number, minus 20
-	 * (a2 a1 a0) = the bit number
-	 *
-	 * example: set the 5th bit of byte 21 (21.5)
-	 *     a5 a4 a3 = 001 (byte 1)
-	 *     a2 a1 a0 = 101 (bit 5)
-	 *
-	 *     byte1 = 0001 0100 (0x14)
-	 *     byte2 = 0001 1101 (0x1d)
-	 */
-	unsigned char byte1=0x10, byte2=0x10;
-
-	/* the 750's '20.0' is accessed as '0.0' through Utah (which adds 20) */
-	bytenum -= 20;
-
-	byte1 |= (!!value) << 2;		/* set d */
-	byte1 |= (bytenum >> 1) & 0x3;	/* set a5, a4 */
-
-	byte2 |= (bytenum & 0x1) << 3;	/* set a3 */
-	byte2 |= bitnum & 0x7;			/* set a2, a1, a0 */
-
-	outb(byte1, PREP_IBM_PM1);	/* first nibble */
-	mb();
-	udelay(100);				/* important: let controller recover */
-
-	outb(byte2, PREP_IBM_PM1);	/* second nibble */
-	mb();
-	udelay(100);				/* important: let controller recover */
-}
-
-static void
-prep_sig750_poweroff(void)
-{
-	/* tweak the power manager found in most IBM PRePs (except Thinkpads) */
-
-	local_irq_disable();
-	/* set exception prefix high - to the prom */
-	_nmask_and_or_msr(0, MSR_IP);
-
-	utah_sig87c750_setbit(21, 5, 1); /* set bit 21.5, "PMEXEC_OFF" */
-
-	while (1) ;
-	/* not reached */
-}
-
-static int
-prep_show_percpuinfo(struct seq_file *m, int i)
-{
-	/* PREP's without residual data will give incorrect values here */
-	seq_printf(m, "clock\t\t: ");
-	if (have_residual_data)
-		seq_printf(m, "%ldMHz\n",
-			   (res->VitalProductData.ProcessorHz > 1024) ?
-			   res->VitalProductData.ProcessorHz / 1000000 :
-			   res->VitalProductData.ProcessorHz);
-	else
-		seq_printf(m, "???\n");
-
-	return 0;
-}
-
-/*
- * Fill out screen_info according to the residual data. This allows us to use
- * at least vesafb.
- */
-static void __init
-prep_init_vesa(void)
-{
-#if     (defined(CONFIG_FB_VGA16) || defined(CONFIG_FB_VGA16_MODULE) || \
-	 defined(CONFIG_FB_VESA))
-	PPC_DEVICE *vgadev = NULL;
-
-	if (have_residual_data)
-		vgadev = residual_find_device(~0, NULL, DisplayController,
-							SVGAController, -1, 0);
-
-	if (vgadev != NULL) {
-		PnP_TAG_PACKET *pkt;
-
-		pkt = PnP_find_large_vendor_packet(
-				(unsigned char *)&res->DevicePnPHeap[vgadev->AllocatedOffset],
-				0x04, 0); /* 0x04 = Display Tag */
-		if (pkt != NULL) {
-			unsigned char *ptr = (unsigned char *)pkt;
-
-			if (ptr[4]) {
-				/* graphics mode */
-				screen_info.orig_video_isVGA = VIDEO_TYPE_VLFB;
-
-				screen_info.lfb_depth = ptr[4] * 8;
-
-				screen_info.lfb_width = swab16(*(short *)(ptr+6));
-				screen_info.lfb_height = swab16(*(short *)(ptr+8));
-				screen_info.lfb_linelength = swab16(*(short *)(ptr+10));
-
-				screen_info.lfb_base = swab32(*(long *)(ptr+12));
-				screen_info.lfb_size = swab32(*(long *)(ptr+20)) / 65536;
-			}
-		}
-	}
-#endif
-}
-
-/*
- * Set DBAT 2 to access 0x80000000 so early progress messages will work
- */
-static __inline__ void
-prep_set_bat(void)
-{
-	/* wait for all outstanding memory access to complete */
-	mb();
-
-	/* setup DBATs */
-	mtspr(SPRN_DBAT2U, 0x80001ffe);
-	mtspr(SPRN_DBAT2L, 0x8000002a);
-
-	/* wait for updates */
-	mb();
-}
-
-/*
- * IBM 3-digit status LED
- */
-static unsigned int ibm_statusled_base;
-
-static void
-ibm_statusled_progress(char *s, unsigned short hex);
-
-static int
-ibm_statusled_panic(struct notifier_block *dummy1, unsigned long dummy2,
-		    void * dummy3)
-{
-	ibm_statusled_progress(NULL, 0x505); /* SOS */
-	return NOTIFY_DONE;
-}
-
-static struct notifier_block ibm_statusled_block = {
-	ibm_statusled_panic,
-	NULL,
-	INT_MAX /* try to do it first */
-};
-
-static void
-ibm_statusled_progress(char *s, unsigned short hex)
-{
-	static int notifier_installed;
-	/*
-	 * Progress uses 4 digits and we have only 3.  So, we map 0xffff to
-	 * 0xfff for display switch off.  Out of range values are mapped to
-	 * 0xeff, as I'm told 0xf00 and above are reserved for hardware codes.
-	 * Install the panic notifier when the display is first switched off.
-	 */
-	if (hex == 0xffff) {
-		hex = 0xfff;
-		if (!notifier_installed) {
-			++notifier_installed;
-			atomic_notifier_chain_register(&panic_notifier_list,
-						&ibm_statusled_block);
-		}
-	}
-	else
-		if (hex > 0xfff)
-			hex = 0xeff;
-
-	mb();
-	outw(hex, ibm_statusled_base);
-}
-
-static void __init
-ibm_statusled_init(void)
-{
-	/*
-	 * The IBM 3-digit LED display is specified in the residual data
-	 * as an operator panel device, type "System Status LED".  Find
-	 * that device and determine its address.  We validate all the
-	 * other parameters on the off-chance another, similar device
-	 * exists.
-	 */
-	if (have_residual_data) {
-		PPC_DEVICE *led;
-		PnP_TAG_PACKET *pkt;
-
-		led = residual_find_device(~0, NULL, SystemPeripheral,
-					   OperatorPanel, SystemStatusLED, 0);
-		if (!led)
-			return;
-
-		pkt = PnP_find_packet((unsigned char *)
-		       &res->DevicePnPHeap[led->AllocatedOffset], S8_Packet, 0);
-		if (!pkt)
-			return;
-
-		if (pkt->S8_Pack.IOInfo != ISAAddr16bit)
-			return;
-		if (*(unsigned short *)pkt->S8_Pack.RangeMin !=
-		    *(unsigned short *)pkt->S8_Pack.RangeMax)
-			return;
-		if (pkt->S8_Pack.IOAlign != 2)
-			return;
-		if (pkt->S8_Pack.IONum != 2)
-			return;
-
-		ibm_statusled_base = ld_le16((unsigned short *)
-					     (pkt->S8_Pack.RangeMin));
-		ppc_md.progress = ibm_statusled_progress;
-	}
-}
-
-static void __init
-prep_setup_arch(void)
-{
-	unsigned char reg;
-	int is_ide=0;
-
-	/* init to some ~sane value until calibrate_delay() runs */
-	loops_per_jiffy = 50000000;
-
-	/* Lookup PCI host bridges */
-	prep_find_bridges();
-
-	/* Set up floppy in PS/2 mode */
-	outb(0x09, SIO_CONFIG_RA);
-	reg = inb(SIO_CONFIG_RD);
-	reg = (reg & 0x3F) | 0x40;
-	outb(reg, SIO_CONFIG_RD);
-	outb(reg, SIO_CONFIG_RD);	/* Have to write twice to change! */
-
-	switch ( _prep_type )
-	{
-	case _PREP_IBM:
-		reg = inb(PREP_IBM_PLANAR);
-		printk(KERN_INFO "IBM planar ID: %02x", reg);
-		switch (reg) {
-			case PREP_IBM_SANDALFOOT:
-				prep_gen_enable_l2();
-				setup_ibm_pci = prep_sandalfoot_setup_pci;
-				ppc_md.power_off = prep_sig750_poweroff;
-				ppc_md.show_cpuinfo = prep_sandalfoot_cpuinfo;
-				break;
-			case PREP_IBM_THINKPAD:
-				prep_gen_enable_l2();
-				setup_ibm_pci = prep_thinkpad_setup_pci;
-				ppc_md.power_off = prep_carrera_poweroff;
-				ppc_md.show_cpuinfo = prep_thinkpad_cpuinfo;
-				break;
-			default:
-				if (have_residual_data) {
-					prep_gen_enable_l2();
-					setup_ibm_pci = prep_residual_setup_pci;
-					ppc_md.power_off = prep_halt;
-					ppc_md.show_cpuinfo = prep_gen_cpuinfo;
-					break;
-				}
-				else
-					printk(" - unknown! Assuming Carolina");
-					/* fall through */
-			case PREP_IBM_CAROLINA_IDE_0:
-			case PREP_IBM_CAROLINA_IDE_1:
-			case PREP_IBM_CAROLINA_IDE_2:
-			case PREP_IBM_CAROLINA_IDE_3:
-				is_ide = 1;
-			case PREP_IBM_CAROLINA_SCSI_0:
-			case PREP_IBM_CAROLINA_SCSI_1:
-			case PREP_IBM_CAROLINA_SCSI_2:
-			case PREP_IBM_CAROLINA_SCSI_3:
-				prep_carolina_enable_l2();
-				setup_ibm_pci = prep_carolina_setup_pci;
-				ppc_md.power_off = prep_sig750_poweroff;
-				ppc_md.show_cpuinfo = prep_carolina_cpuinfo;
-				break;
-			case PREP_IBM_TIGER1_133:
-			case PREP_IBM_TIGER1_166:
-			case PREP_IBM_TIGER1_180:
-			case PREP_IBM_TIGER1_xxx:
-			case PREP_IBM_TIGER1_333:
-				prep_carolina_enable_l2();
-				setup_ibm_pci = prep_tiger1_setup_pci;
-				ppc_md.power_off = prep_sig750_poweroff;
-				ppc_md.show_cpuinfo = prep_tiger1_cpuinfo;
-				break;
-		}
-		printk("\n");
-
-		/* default root device */
-		if (is_ide)
-			ROOT_DEV = MKDEV(IDE0_MAJOR, 3);
-		else
-			ROOT_DEV = MKDEV(SCSI_DISK0_MAJOR, 3);
-
-		break;
-	case _PREP_Motorola:
-		prep_gen_enable_l2();
-		ppc_md.power_off = prep_halt;
-		ppc_md.show_cpuinfo = prep_mot_cpuinfo;
-
-#ifdef CONFIG_BLK_DEV_INITRD
-		if (initrd_start)
-			ROOT_DEV = Root_RAM0;
-		else
-#endif
-#ifdef CONFIG_ROOT_NFS
-			ROOT_DEV = Root_NFS;
-#else
-			ROOT_DEV = Root_SDA2;
-#endif
-		break;
-	}
-
-	/* Read in NVRAM data */
-	init_prep_nvram();
-
-	/* if no bootargs, look in NVRAM */
-	if ( cmd_line[0] == '\0' ) {
-		char *bootargs;
-		 bootargs = prep_nvram_get_var("bootargs");
-		 if (bootargs != NULL) {
-			 strcpy(cmd_line, bootargs);
-			 /* again.. */
-			 strcpy(boot_command_line, cmd_line);
-		}
-	}
-
-	prep_init_vesa();
-
-	switch (_prep_type) {
-	case _PREP_Motorola:
-		raven_init();
-		break;
-	case _PREP_IBM:
-		ibm_prep_init();
-		break;
-	}
-
-#ifdef CONFIG_VGA_CONSOLE
-	/* vgacon.c needs to know where we mapped IO memory in io_block_mapping() */
-	vgacon_remap_base = 0xf0000000;
-	conswitchp = &vga_con;
-#endif
-}
-
-/*
- * First, see if we can get this information from the residual data.
- * This is important on some IBM PReP systems.  If we cannot, we let the
- * TODC code handle doing this.
- */
-static void __init
-prep_calibrate_decr(void)
-{
-	if (have_residual_data) {
-		unsigned long freq, divisor = 4;
-
-		if ( res->VitalProductData.ProcessorBusHz ) {
-			freq = res->VitalProductData.ProcessorBusHz;
-			printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
-					(freq/divisor)/1000000,
-					(freq/divisor)%1000000);
-			tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
-			tb_ticks_per_jiffy = freq / HZ / divisor;
-		}
-	}
-	else
-		todc_calibrate_decr();
-}
-
-static void __init
-prep_init_IRQ(void)
-{
-	unsigned int pci_viddid, pci_did;
-
-	if (OpenPIC_Addr != NULL) {
-		openpic_init(NUM_8259_INTERRUPTS);
-		/* We have a cascade on OpenPIC IRQ 0, Linux IRQ 16 */
-		openpic_hookup_cascade(NUM_8259_INTERRUPTS, "82c59 cascade",
-				       i8259_irq);
-	}
-
-	if (have_residual_data) {
-		i8259_init(residual_isapic_addr(), 0);
-		return;
-	}
-
-	/* If we have a Raven PCI bridge or a Hawk PCI bridge / Memory
-	 * controller, we poll (as they have a different int-ack address). */
-	early_read_config_dword(NULL, 0, 0, PCI_VENDOR_ID, &pci_viddid);
-	pci_did = (pci_viddid & 0xffff0000) >> 16;
-	if (((pci_viddid & 0xffff) == PCI_VENDOR_ID_MOTOROLA)
-			&& ((pci_did == PCI_DEVICE_ID_MOTOROLA_RAVEN)
-				|| (pci_did == PCI_DEVICE_ID_MOTOROLA_HAWK)))
-		i8259_init(0, 0);
-	else
-		/* PCI interrupt ack address given in section 6.1.8 of the
-		 * PReP specification. */
-		i8259_init(MPC10X_MAPA_PCI_INTACK_ADDR, 0);
-}
-
-#ifdef CONFIG_SMP
-/* PReP (MTX) support */
-static int __init
-smp_prep_probe(void)
-{
-	extern int mot_multi;
-
-	if (mot_multi) {
-		openpic_request_IPIs();
-		smp_hw_index[1] = 1;
-		return 2;
-	}
-
-	return 1;
-}
-
-static void __init
-smp_prep_kick_cpu(int nr)
-{
-	*(unsigned long *)KERNELBASE = nr;
-	asm volatile("dcbf 0,%0"::"r"(KERNELBASE):"memory");
-	printk("CPU1 released, waiting\n");
-}
-
-static void __init
-smp_prep_setup_cpu(int cpu_nr)
-{
-	if (OpenPIC_Addr)
-		do_openpic_setup_cpu();
-}
-
-static struct smp_ops_t prep_smp_ops = {
-	smp_openpic_message_pass,
-	smp_prep_probe,
-	smp_prep_kick_cpu,
-	smp_prep_setup_cpu,
-	.give_timebase = smp_generic_give_timebase,
-	.take_timebase = smp_generic_take_timebase,
-};
-#endif /* CONFIG_SMP */
-
-/*
- * Setup the bat mappings we're going to load that cover
- * the io areas.  RAM was mapped by mapin_ram().
- * -- Cort
- */
-static void __init
-prep_map_io(void)
-{
-	io_block_mapping(0x80000000, PREP_ISA_IO_BASE, 0x10000000, _PAGE_IO);
-	io_block_mapping(0xf0000000, PREP_ISA_MEM_BASE, 0x08000000, _PAGE_IO);
-}
-
-static int __init
-prep_request_io(void)
-{
-#ifdef CONFIG_NVRAM
-	request_region(PREP_NVRAM_AS0, 0x8, "nvram");
-#endif
-	request_region(0x00,0x20,"dma1");
-	request_region(0x40,0x20,"timer");
-	request_region(0x80,0x10,"dma page reg");
-	request_region(0xc0,0x20,"dma2");
-
-	return 0;
-}
-
-device_initcall(prep_request_io);
-
-void __init
-prep_init(unsigned long r3, unsigned long r4, unsigned long r5,
-		unsigned long r6, unsigned long r7)
-{
-#ifdef CONFIG_PREP_RESIDUAL
-	/* make a copy of residual data */
-	if ( r3 ) {
-		memcpy((void *)res,(void *)(r3+KERNELBASE),
-			 sizeof(RESIDUAL));
-	}
-#endif
-
-	isa_io_base = PREP_ISA_IO_BASE;
-	isa_mem_base = PREP_ISA_MEM_BASE;
-	pci_dram_offset = PREP_PCI_DRAM_OFFSET;
-	ISA_DMA_THRESHOLD = 0x00ffffff;
-	DMA_MODE_READ = 0x44;
-	DMA_MODE_WRITE = 0x48;
-	ppc_do_canonicalize_irqs = 1;
-
-	/* figure out what kind of prep workstation we are */
-	if (have_residual_data) {
-		if ( !strncmp(res->VitalProductData.PrintableModel,"IBM",3) )
-			_prep_type = _PREP_IBM;
-		else
-			_prep_type = _PREP_Motorola;
-	}
-	else {
-		/* assume motorola if no residual (netboot?) */
-		_prep_type = _PREP_Motorola;
-	}
-
-#ifdef CONFIG_PREP_RESIDUAL
-	/* Switch off all residual data processing if the user requests it */
-	if (strstr(cmd_line, "noresidual") != NULL)
-			res = NULL;
-#endif
-
-	/* Initialise progress early to get maximum benefit */
-	prep_set_bat();
-	ibm_statusled_init();
-
-	ppc_md.setup_arch     = prep_setup_arch;
-	ppc_md.show_percpuinfo = prep_show_percpuinfo;
-	ppc_md.show_cpuinfo   = NULL; /* set in prep_setup_arch() */
-	ppc_md.init_IRQ       = prep_init_IRQ;
-	/* this gets changed later on if we have an OpenPIC -- Cort */
-	ppc_md.get_irq        = i8259_irq;
-
-	ppc_md.phys_mem_access_prot = pci_phys_mem_access_prot;
-
-	ppc_md.restart        = prep_restart;
-	ppc_md.power_off      = NULL; /* set in prep_setup_arch() */
-	ppc_md.halt           = prep_halt;
-
-	ppc_md.nvram_read_val = prep_nvram_read_val;
-	ppc_md.nvram_write_val = prep_nvram_write_val;
-
-	ppc_md.time_init      = todc_time_init;
-	if (_prep_type == _PREP_IBM) {
-		ppc_md.rtc_read_val = todc_mc146818_read_val;
-		ppc_md.rtc_write_val = todc_mc146818_write_val;
-		TODC_INIT(TODC_TYPE_MC146818, RTC_PORT(0), NULL, RTC_PORT(1),
-				8);
-	} else {
-		TODC_INIT(TODC_TYPE_MK48T59, PREP_NVRAM_AS0, PREP_NVRAM_AS1,
-				PREP_NVRAM_DATA, 8);
-	}
-
-	ppc_md.calibrate_decr = prep_calibrate_decr;
-	ppc_md.set_rtc_time   = todc_set_rtc_time;
-	ppc_md.get_rtc_time   = todc_get_rtc_time;
-
-	ppc_md.setup_io_mappings = prep_map_io;
-
-#ifdef CONFIG_SMP
-	smp_ops			 = &prep_smp_ops;
-#endif /* CONFIG_SMP */
-}
diff --git a/arch/ppc/platforms/prpmc750.c b/arch/ppc/platforms/prpmc750.c
deleted file mode 100644
index 93bd593cf95..00000000000
--- a/arch/ppc/platforms/prpmc750.c
+++ /dev/null
@@ -1,360 +0,0 @@
-/*
- * Board setup routines for Motorola PrPMC750
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/slab.h>
-#include <linux/serial_reg.h>
-
-#include <asm/byteorder.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/machdep.h>
-#include <asm/pci-bridge.h>
-#include <asm/uaccess.h>
-#include <asm/time.h>
-#include <asm/open_pic.h>
-#include <asm/bootinfo.h>
-#include <asm/hawk.h>
-
-#include "prpmc750.h"
-
-extern unsigned long loops_per_jiffy;
-
-extern void gen550_progress(char *, unsigned short);
-
-static u_char prpmc750_openpic_initsenses[] __initdata =
-{
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_HOSTINT0 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_UART */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_DEBUGINT */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_HAWK_WDT */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_UNUSED */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_ABORT */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_HOSTINT1 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_HOSTINT2 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_HOSTINT3 */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_PMC_INTA */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_PMC_INTB */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_PMC_INTC */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_PMC_INTD */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_UNUSED */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_UNUSED */
-    (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC750_INT_UNUSED */
-};
-
-/*
- * Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
- * Combined irq tables.  Only Base has IDSEL 14, only Carrier has 21 and 22.
- */
-static inline int
-prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *      PCI IDSEL/INTPIN->INTLINE
-	 *      A       B       C       D
-	 */
-	{
-		{12,	0,	0,	0},  /* IDSEL 14 - Ethernet, base */
-		{0,	0,	0,	0},  /* IDSEL 15 - unused */
-		{10,	11,	12,	9},  /* IDSEL 16 - PMC A1, PMC1 */
-		{10,	11,	12,	9},  /* IDSEL 17 - PrPMC-A-B, PMC2-B */
-		{11,	12,	9,	10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
-		{0,	0,	0,	0},  /* IDSEL 19 - unused */
-		{9,	10,	11,	12}, /* IDSEL 20 - P2P Bridge */
-		{11,	12,	9,	10}, /* IDSEL 21 - PMC A2, carrier */
-		{12,	9,	10,	11}, /* IDSEL 22 - PMC A2-B, carrier */
-	};
-	const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-};
-
-static void __init prpmc750_pcibios_fixup(void)
-{
-	struct pci_dev *dev;
-	unsigned short wtmp;
-
-	/*
-	 * Kludge to clean up after PPC6BUG which doesn't
-	 * configure the CL5446 VGA card.  Also the
-	 * resource subsystem doesn't fixup the
-	 * PCI mem resources on the CL5446.
-	 */
-	if ((dev = pci_get_device(PCI_VENDOR_ID_CIRRUS,
-				   PCI_DEVICE_ID_CIRRUS_5446, 0))) {
-		dev->resource[0].start += PRPMC750_PCI_PHY_MEM_OFFSET;
-		dev->resource[0].end += PRPMC750_PCI_PHY_MEM_OFFSET;
-		pci_read_config_word(dev, PCI_COMMAND, &wtmp);
-		pci_write_config_word(dev, PCI_COMMAND, wtmp | 3);
-		/* Enable Color mode in MISC reg */
-		outb(0x03, 0x3c2);
-		/* Select DRAM config reg */
-		outb(0x0f, 0x3c4);
-		/* Set proper DRAM config */
-		outb(0xdf, 0x3c5);
-		pci_dev_put(dev);
-	}
-}
-
-void __init prpmc750_find_bridges(void)
-{
-	struct pci_controller *hose;
-
-	hose = pcibios_alloc_controller();
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-	hose->io_base_virt = (void *)PRPMC750_ISA_IO_BASE;
-	hose->pci_mem_offset = PRPMC750_PCI_PHY_MEM_OFFSET;
-
-	pci_init_resource(&hose->io_resource,
-			  PRPMC750_PCI_IO_START,
-			  PRPMC750_PCI_IO_END,
-			  IORESOURCE_IO, "PCI host bridge");
-
-	pci_init_resource(&hose->mem_resources[0],
-			  PRPMC750_PROC_PCI_MEM_START,
-			  PRPMC750_PROC_PCI_MEM_END,
-			  IORESOURCE_MEM, "PCI host bridge");
-
-	hose->io_space.start = PRPMC750_PCI_IO_START;
-	hose->io_space.end = PRPMC750_PCI_IO_END;
-	hose->mem_space.start = PRPMC750_PCI_MEM_START;
-	hose->mem_space.end = PRPMC750_PCI_MEM_END - HAWK_MPIC_SIZE;
-
-	if (hawk_init(hose, PRPMC750_HAWK_PPC_REG_BASE,
-		      PRPMC750_PROC_PCI_MEM_START,
-		      PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE,
-		      PRPMC750_PROC_PCI_IO_START, PRPMC750_PROC_PCI_IO_END,
-		      PRPMC750_PROC_PCI_MEM_END - HAWK_MPIC_SIZE + 1)
-	    != 0) {
-		printk(KERN_CRIT "Could not initialize host bridge\n");
-	}
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pcibios_fixup = prpmc750_pcibios_fixup;
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = prpmc_map_irq;
-}
-static int prpmc750_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "machine\t\t: PrPMC750\n");
-
-	return 0;
-}
-
-static void __init prpmc750_setup_arch(void)
-{
-	/* init to some ~sane value until calibrate_delay() runs */
-	loops_per_jiffy = 50000000 / HZ;
-
-	/* Lookup PCI host bridges */
-	prpmc750_find_bridges();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	OpenPIC_InitSenses = prpmc750_openpic_initsenses;
-	OpenPIC_NumInitSenses = sizeof(prpmc750_openpic_initsenses);
-
-	printk(KERN_INFO "Port by MontaVista Software, Inc. "
-			"(source@mvista.com)\n");
-}
-
-/*
- * Compute the PrPMC750's bus speed using the baud clock as a
- * reference.
- */
-static unsigned long __init prpmc750_get_bus_speed(void)
-{
-	unsigned long tbl_start, tbl_end;
-	unsigned long current_state, old_state, bus_speed;
-	unsigned char lcr, dll, dlm;
-	int baud_divisor, count;
-
-	/* Read the UART's baud clock divisor */
-	lcr = readb(PRPMC750_SERIAL_0_LCR);
-	writeb(lcr | UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
-	dll = readb(PRPMC750_SERIAL_0_DLL);
-	dlm = readb(PRPMC750_SERIAL_0_DLM);
-	writeb(lcr & ~UART_LCR_DLAB, PRPMC750_SERIAL_0_LCR);
-	baud_divisor = (dlm << 8) | dll;
-
-	/*
-	 * Use the baud clock divisor and base baud clock
-	 * to determine the baud rate and use that as
-	 * the number of baud clock edges we use for
-	 * the time base sample.  Make it half the baud
-	 * rate.
-	 */
-	count = PRPMC750_BASE_BAUD / (baud_divisor * 16);
-
-	/* Find the first edge of the baud clock */
-	old_state = readb(PRPMC750_STATUS_REG) & PRPMC750_BAUDOUT_MASK;
-	do {
-		current_state = readb(PRPMC750_STATUS_REG) &
-		    PRPMC750_BAUDOUT_MASK;
-	} while (old_state == current_state);
-
-	old_state = current_state;
-
-	/* Get the starting time base value */
-	tbl_start = get_tbl();
-
-	/*
-	 * Loop until we have found a number of edges equal
-	 * to half the count (half the baud rate)
-	 */
-	do {
-		do {
-			current_state = readb(PRPMC750_STATUS_REG) &
-			    PRPMC750_BAUDOUT_MASK;
-		} while (old_state == current_state);
-		old_state = current_state;
-	} while (--count);
-
-	/* Get the ending time base value */
-	tbl_end = get_tbl();
-
-	/* Compute bus speed */
-	bus_speed = (tbl_end - tbl_start) * 128;
-
-	return bus_speed;
-}
-
-static void __init prpmc750_calibrate_decr(void)
-{
-	unsigned long freq;
-	int divisor = 4;
-
-	freq = prpmc750_get_bus_speed();
-
-	tb_ticks_per_jiffy = freq / (HZ * divisor);
-	tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
-}
-
-static void prpmc750_restart(char *cmd)
-{
-	local_irq_disable();
-	writeb(PRPMC750_MODRST_MASK, PRPMC750_MODRST_REG);
-	while (1) ;
-}
-
-static void prpmc750_halt(void)
-{
-	local_irq_disable();
-	while (1) ;
-}
-
-static void prpmc750_power_off(void)
-{
-	prpmc750_halt();
-}
-
-static void __init prpmc750_init_IRQ(void)
-{
-	openpic_init(0);
-}
-
-/*
- * Set BAT 3 to map 0xf0000000 to end of physical memory space.
- */
-static __inline__ void prpmc750_set_bat(void)
-{
-	mb();
-	mtspr(SPRN_DBAT1U, 0xf0001ffe);
-	mtspr(SPRN_DBAT1L, 0xf000002a);
-	mb();
-}
-
-/*
- * We need to read the Falcon/Hawk memory controller
- * to properly determine this value
- */
-static unsigned long __init prpmc750_find_end_of_memory(void)
-{
-	/* Read the memory size from the Hawk SMC */
-	return hawk_get_mem_size(PRPMC750_HAWK_SMC_BASE);
-}
-
-static void __init prpmc750_map_io(void)
-{
-	io_block_mapping(PRPMC750_ISA_IO_BASE, PRPMC750_ISA_IO_BASE,
-			 0x10000000, _PAGE_IO);
-#if 0
-	io_block_mapping(0xf0000000, 0xc0000000, 0x08000000, _PAGE_IO);
-#endif
-	io_block_mapping(0xf8000000, 0xf8000000, 0x08000000, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	/* Cover the Hawk registers with a BAT */
-	prpmc750_set_bat();
-
-	isa_io_base = PRPMC750_ISA_IO_BASE;
-	isa_mem_base = PRPMC750_ISA_MEM_BASE;
-	pci_dram_offset = PRPMC750_PCI_DRAM_OFFSET;
-
-	ppc_md.setup_arch = prpmc750_setup_arch;
-	ppc_md.show_cpuinfo = prpmc750_show_cpuinfo;
-	ppc_md.init_IRQ = prpmc750_init_IRQ;
-	ppc_md.get_irq = openpic_get_irq;
-
-	ppc_md.find_end_of_memory = prpmc750_find_end_of_memory;
-	ppc_md.setup_io_mappings = prpmc750_map_io;
-
-	ppc_md.restart = prpmc750_restart;
-	ppc_md.power_off = prpmc750_power_off;
-	ppc_md.halt = prpmc750_halt;
-
-	/* PrPMC750 has no timekeeper part */
-	ppc_md.time_init = NULL;
-	ppc_md.get_rtc_time = NULL;
-	ppc_md.set_rtc_time = NULL;
-	ppc_md.calibrate_decr = prpmc750_calibrate_decr;
-
-#ifdef  CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.progress = gen550_progress;
-#endif				/* CONFIG_SERIAL_TEXT_DEBUG */
-}
diff --git a/arch/ppc/platforms/prpmc750.h b/arch/ppc/platforms/prpmc750.h
deleted file mode 100644
index c4dcff09d7c..00000000000
--- a/arch/ppc/platforms/prpmc750.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * arch/ppc/platforms/prpmc750.h
- *
- * Definitions for Motorola PrPMC750 board support
- *
- * Author: Matt Porter <mporter@mvista.com>
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_PRPMC750_H__
-#define __ASM_PRPMC750_H__
-
-/*
- * Due to limitations imposed by legacy hardware (primarily IDE controllers),
- * the PrPMC750 carrier board operates using a PReP address map.
- *
- * From Processor (physical) -> PCI:
- *   PCI Mem Space: 0xc0000000 - 0xfe000000 -> 0x00000000 - 0x3e000000 (768 MB)
- *   PCI I/O Space: 0x80000000 - 0x90000000 -> 0x00000000 - 0x10000000 (256 MB)
- *	Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
- *
- * From PCI -> Processor (physical):
- *   System Memory: 0x80000000 -> 0x00000000
- */
-
-#define PRPMC750_ISA_IO_BASE		PREP_ISA_IO_BASE
-#define PRPMC750_ISA_MEM_BASE		PREP_ISA_MEM_BASE
-
-/* PCI Memory space mapping info */
-#define PRPMC750_PCI_MEM_SIZE		0x30000000U
-#define PRPMC750_PROC_PCI_MEM_START	PRPMC750_ISA_MEM_BASE
-#define PRPMC750_PROC_PCI_MEM_END	(PRPMC750_PROC_PCI_MEM_START +	\
-					 PRPMC750_PCI_MEM_SIZE - 1)
-#define PRPMC750_PCI_MEM_START		0x00000000U
-#define PRPMC750_PCI_MEM_END		(PRPMC750_PCI_MEM_START +	\
-					 PRPMC750_PCI_MEM_SIZE - 1)
-
-/* PCI I/O space mapping info */
-#define PRPMC750_PCI_IO_SIZE		0x10000000U
-#define PRPMC750_PROC_PCI_IO_START	PRPMC750_ISA_IO_BASE
-#define PRPMC750_PROC_PCI_IO_END	(PRPMC750_PROC_PCI_IO_START +	\
-					 PRPMC750_PCI_IO_SIZE - 1)
-#define PRPMC750_PCI_IO_START		0x00000000U
-#define PRPMC750_PCI_IO_END		(PRPMC750_PCI_IO_START + 	\
-					 PRPMC750_PCI_IO_SIZE - 1)
-
-/* System memory mapping info */
-#define PRPMC750_PCI_DRAM_OFFSET	PREP_PCI_DRAM_OFFSET
-#define PRPMC750_PCI_PHY_MEM_OFFSET	(PRPMC750_ISA_MEM_BASE-PRPMC750_PCI_MEM_START)
-
-/* Register address definitions */
-#define PRPMC750_HAWK_SMC_BASE		0xfef80000U
-#define PRPMC750_HAWK_PPC_REG_BASE	0xfeff0000U
-
-#define PRPMC750_BASE_BAUD		1843200
-#define PRPMC750_SERIAL_0		0xfef88000
-#define PRPMC750_SERIAL_0_DLL		(PRPMC750_SERIAL_0 + (UART_DLL << 4))
-#define PRPMC750_SERIAL_0_DLM		(PRPMC750_SERIAL_0 + (UART_DLM << 4))
-#define PRPMC750_SERIAL_0_LCR		(PRPMC750_SERIAL_0 + (UART_LCR << 4))
-
-#define PRPMC750_STATUS_REG		0xfef88080
-#define PRPMC750_BAUDOUT_MASK		0x02
-#define PRPMC750_MONARCH_MASK		0x01
-
-#define PRPMC750_MODRST_REG		0xfef880a0
-#define PRPMC750_MODRST_MASK		0x01
-
-#define PRPMC750_PIRQ_REG		0xfef880b0
-#define PRPMC750_SEL1_MASK		0x02
-#define PRPMC750_SEL0_MASK		0x01
-
-#define PRPMC750_TBEN_REG		0xfef880c0
-#define PRPMC750_TBEN_MASK		0x01
-
-/* UART Defines. */
-#define RS_TABLE_SIZE  4
-
-/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
-#define BASE_BAUD  (PRPMC750_BASE_BAUD / 16)
-
-#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
-
-#define SERIAL_PORT_DFNS \
-        { 0, BASE_BAUD, PRPMC750_SERIAL_0, 1, STD_COM_FLAGS, \
-		iomem_base: (unsigned char *)PRPMC750_SERIAL_0, \
-		iomem_reg_shift: 4, \
-		io_type: SERIAL_IO_MEM } /* ttyS0 */
-
-#endif				/* __ASM_PRPMC750_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/prpmc800.c b/arch/ppc/platforms/prpmc800.c
deleted file mode 100644
index 5bcda7f92cd..00000000000
--- a/arch/ppc/platforms/prpmc800.c
+++ /dev/null
@@ -1,472 +0,0 @@
-/*
- * Author: Dale Farnsworth <dale.farnsworth@mvista.com>
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/harrier_defs.h>
-
-#include <asm/byteorder.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/machdep.h>
-#include <asm/time.h>
-#include <asm/pci-bridge.h>
-#include <asm/open_pic.h>
-#include <asm/bootinfo.h>
-#include <asm/harrier.h>
-
-#include "prpmc800.h"
-
-#define HARRIER_REVI_REG	(PRPMC800_HARRIER_XCSR_BASE+HARRIER_REVI_OFF)
-#define HARRIER_UCTL_REG	(PRPMC800_HARRIER_XCSR_BASE+HARRIER_UCTL_OFF)
-#define HARRIER_MISC_CSR_REG   (PRPMC800_HARRIER_XCSR_BASE+HARRIER_MISC_CSR_OFF)
-#define HARRIER_IFEVP_REG    (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEVP_OFF)
-#define HARRIER_IFEDE_REG    (PRPMC800_HARRIER_MPIC_BASE+HARRIER_MPIC_IFEDE_OFF)
-#define HARRIER_FEEN_REG	(PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEEN_OFF)
-#define HARRIER_FEMA_REG	(PRPMC800_HARRIER_XCSR_BASE+HARRIER_FEMA_OFF)
-
-#define HARRIER_VENI_REG	(PRPMC800_HARRIER_XCSR_BASE + HARRIER_VENI_OFF)
-#define HARRIER_MISC_CSR	(PRPMC800_HARRIER_XCSR_BASE + \
-				 HARRIER_MISC_CSR_OFF)
-
-#define MONARCH	(monarch != 0)
-#define NON_MONARCH (monarch == 0)
-
-extern int mpic_init(void);
-extern unsigned long loops_per_jiffy;
-extern void gen550_progress(char *, unsigned short);
-
-static int monarch = 0;
-static int found_self = 0;
-static int self = 0;
-
-static u_char prpmc800_openpic_initsenses[] __initdata =
-{
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_HOSTINT0 */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_UNUSED */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_DEBUGINT */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_HARRIER_WDT */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_UNUSED */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_UNUSED */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_HOSTINT1 */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_HOSTINT2 */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_HOSTINT3 */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_PMC_INTA */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_PMC_INTB */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_PMC_INTC */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_PMC_INTD */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_UNUSED */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_UNUSED */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_UNUSED */
-   (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* PRPMC800_INT_HARRIER_INT (UARTS, ABORT, DMA) */
-};
-
-/*
- * Motorola PrPMC750/PrPMC800 in PrPMCBASE or PrPMC-Carrier
- * Combined irq tables.  Only Base has IDSEL 14, only Carrier has 21 and 22.
- */
-static inline int
-prpmc_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *      PCI IDSEL/INTPIN->INTLINE
-	 *      A       B       C       D
-	 */
-	{
-		{12,	0,	0,	0},  /* IDSEL 14 - Ethernet, base */
-		{0,	0,	0,	0},  /* IDSEL 15 - unused */
-		{10,	11,	12,	9},  /* IDSEL 16 - PMC A1, PMC1 */
-		{10,	11,	12,	9},  /* IDSEL 17 - PrPMC-A-B, PMC2-B */
-		{11,	12,	9,	10}, /* IDSEL 18 - PMC A1-B, PMC1-B */
-		{0,	0,	0,	0},  /* IDSEL 19 - unused */
-		{9,	10,	11,	12}, /* IDSEL 20 - P2P Bridge */
-		{11,	12,	9,	10}, /* IDSEL 21 - PMC A2, carrier */
-		{12,	9,	10,	11}, /* IDSEL 22 - PMC A2-B, carrier */
-	};
-	const long min_idsel = 14, max_idsel = 22, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-};
-
-static int
-prpmc_read_config_dword(struct pci_controller *hose, u8 bus, u8 devfn,
-			int offset, u32 * val)
-{
-	/* paranoia */
-	if ((hose == NULL) ||
-	    (hose->cfg_addr == NULL) || (hose->cfg_data == NULL))
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	out_be32(hose->cfg_addr, ((offset & 0xfc) << 24) | (devfn << 16)
-		 | ((bus - hose->bus_offset) << 8) | 0x80);
-	*val = in_le32((u32 *) (hose->cfg_data + (offset & 3)));
-
-	return PCIBIOS_SUCCESSFUL;
-}
-
-#define HARRIER_PCI_VEND_DEV_ID	(PCI_VENDOR_ID_MOTOROLA | \
-				 (PCI_DEVICE_ID_MOTOROLA_HARRIER << 16))
-static int prpmc_self(u8 bus, u8 devfn)
-{
-	/*
-	 * Harriers always view themselves as being on bus 0. If we're not
-	 * looking at bus 0, we're not going to find ourselves.
-	 */
-	if (bus != 0)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	else {
-		int result;
-		int val;
-		struct pci_controller *hose;
-
-		hose = pci_bus_to_hose(bus);
-
-		/* See if target device is a Harrier */
-		result = prpmc_read_config_dword(hose, bus, devfn,
-						 PCI_VENDOR_ID, &val);
-		if ((result != PCIBIOS_SUCCESSFUL) ||
-		    (val != HARRIER_PCI_VEND_DEV_ID))
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		/*
-		 * LBA bit is set if target Harrier == initiating Harrier
-		 * (i.e. if we are reading our own PCI header).
-		 */
-		result = prpmc_read_config_dword(hose, bus, devfn,
-						 HARRIER_LBA_OFF, &val);
-		if ((result != PCIBIOS_SUCCESSFUL) ||
-		    ((val & HARRIER_LBA_MSK) != HARRIER_LBA_MSK))
-			return PCIBIOS_DEVICE_NOT_FOUND;
-
-		/* It's us, save our location for later */
-		self = devfn;
-		found_self = 1;
-		return PCIBIOS_SUCCESSFUL;
-	}
-}
-
-static int prpmc_exclude_device(u8 bus, u8 devfn)
-{
-	/*
-	 * Monarch is allowed to access all PCI devices. Non-monarch is
-	 * only allowed to access its own Harrier.
-	 */
-
-	if (MONARCH)
-		return PCIBIOS_SUCCESSFUL;
-	if (found_self)
-		if ((bus == 0) && (devfn == self))
-			return PCIBIOS_SUCCESSFUL;
-		else
-			return PCIBIOS_DEVICE_NOT_FOUND;
-	else
-		return prpmc_self(bus, devfn);
-}
-
-void __init prpmc800_find_bridges(void)
-{
-	struct pci_controller *hose;
-	int host_bridge;
-
-	hose = pcibios_alloc_controller();
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	ppc_md.pci_exclude_device = prpmc_exclude_device;
-	ppc_md.pcibios_fixup = NULL;
-	ppc_md.pcibios_fixup_bus = NULL;
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = prpmc_map_irq;
-
-	setup_indirect_pci(hose,
-			   PRPMC800_PCI_CONFIG_ADDR, PRPMC800_PCI_CONFIG_DATA);
-
-	/* Get host bridge vendor/dev id */
-
-	host_bridge = in_be32((uint *) (HARRIER_VENI_REG));
-
-	if (host_bridge != HARRIER_VEND_DEV_ID) {
-		printk(KERN_CRIT "Host bridge 0x%x not supported\n",
-				host_bridge);
-		return;
-	}
-
-	monarch = in_be32((uint *) HARRIER_MISC_CSR) & HARRIER_SYSCON;
-
-	printk(KERN_INFO "Running as %s.\n",
-			MONARCH ? "Monarch" : "Non-Monarch");
-
-	hose->io_space.start = PRPMC800_PCI_IO_START;
-	hose->io_space.end = PRPMC800_PCI_IO_END;
-	hose->io_base_virt = (void *)PRPMC800_ISA_IO_BASE;
-	hose->pci_mem_offset = PRPMC800_PCI_PHY_MEM_OFFSET;
-
-	pci_init_resource(&hose->io_resource,
-			  PRPMC800_PCI_IO_START, PRPMC800_PCI_IO_END,
-			  IORESOURCE_IO, "PCI host bridge");
-
-	if (MONARCH) {
-		hose->mem_space.start = PRPMC800_PCI_MEM_START;
-		hose->mem_space.end = PRPMC800_PCI_MEM_END;
-
-		pci_init_resource(&hose->mem_resources[0],
-				  PRPMC800_PCI_MEM_START,
-				  PRPMC800_PCI_MEM_END,
-				  IORESOURCE_MEM, "PCI host bridge");
-
-		if (harrier_init(hose,
-				 PRPMC800_HARRIER_XCSR_BASE,
-				 PRPMC800_PROC_PCI_MEM_START,
-				 PRPMC800_PROC_PCI_MEM_END,
-				 PRPMC800_PROC_PCI_IO_START,
-				 PRPMC800_PROC_PCI_IO_END,
-				 PRPMC800_HARRIER_MPIC_BASE) != 0)
-			printk(KERN_CRIT "Could not initialize HARRIER "
-					 "bridge\n");
-
-		harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE);
-		harrier_wait_eready(PRPMC800_HARRIER_XCSR_BASE);
-		hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	} else {
-		pci_init_resource(&hose->mem_resources[0],
-				  PRPMC800_NM_PCI_MEM_START,
-				  PRPMC800_NM_PCI_MEM_END,
-				  IORESOURCE_MEM, "PCI host bridge");
-
-		hose->mem_space.start = PRPMC800_NM_PCI_MEM_START;
-		hose->mem_space.end = PRPMC800_NM_PCI_MEM_END;
-
-		if (harrier_init(hose,
-				 PRPMC800_HARRIER_XCSR_BASE,
-				 PRPMC800_NM_PROC_PCI_MEM_START,
-				 PRPMC800_NM_PROC_PCI_MEM_END,
-				 PRPMC800_PROC_PCI_IO_START,
-				 PRPMC800_PROC_PCI_IO_END,
-				 PRPMC800_HARRIER_MPIC_BASE) != 0)
-			printk(KERN_CRIT "Could not initialize HARRIER "
-					 "bridge\n");
-
-		harrier_setup_nonmonarch(PRPMC800_HARRIER_XCSR_BASE,
-					 HARRIER_ITSZ_1MB);
-		harrier_release_eready(PRPMC800_HARRIER_XCSR_BASE);
-	}
-}
-
-static int prpmc800_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "machine\t\t: PrPMC800\n");
-
-	return 0;
-}
-
-static void __init prpmc800_setup_arch(void)
-{
-	/* init to some ~sane value until calibrate_delay() runs */
-	loops_per_jiffy = 50000000 / HZ;
-
-	/* Lookup PCI host bridges */
-	prpmc800_find_bridges();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA2;
-#endif
-
-	printk(KERN_INFO "Port by MontaVista Software, Inc. "
-			 "(source@mvista.com)\n");
-}
-
-/*
- * Compute the PrPMC800's tbl frequency using the baud clock as a reference.
- */
-static void __init prpmc800_calibrate_decr(void)
-{
-	unsigned long tbl_start, tbl_end;
-	unsigned long current_state, old_state, tb_ticks_per_second;
-	unsigned int count;
-	unsigned int harrier_revision;
-
-	harrier_revision = readb(HARRIER_REVI_REG);
-	if (harrier_revision < 2) {
-		/* XTAL64 was broken in harrier revision 1 */
-		printk(KERN_INFO "time_init: Harrier revision %d, assuming "
-				 "100 Mhz bus\n", harrier_revision);
-		tb_ticks_per_second = 100000000 / 4;
-		tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
-		tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
-		return;
-	}
-
-	/*
-	 * The XTAL64 bit oscillates at the 1/64 the base baud clock
-	 * Set count to XTAL64 cycles per second.  Since we'll count
-	 * half-cycles, we'll reach the count in half a second.
-	 */
-	count = PRPMC800_BASE_BAUD / 64;
-
-	/* Find the first edge of the baud clock */
-	old_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
-	do {
-		current_state = readb(HARRIER_UCTL_REG) & HARRIER_XTAL64_MASK;
-	} while (old_state == current_state);
-
-	old_state = current_state;
-
-	/* Get the starting time base value */
-	tbl_start = get_tbl();
-
-	/*
-	 * Loop until we have found a number of edges (half-cycles)
-	 * equal to the count (half a second)
-	 */
-	do {
-		do {
-			current_state = readb(HARRIER_UCTL_REG) &
-			    HARRIER_XTAL64_MASK;
-		} while (old_state == current_state);
-		old_state = current_state;
-	} while (--count);
-
-	/* Get the ending time base value */
-	tbl_end = get_tbl();
-
-	/* We only counted for half a second, so double to get ticks/second */
-	tb_ticks_per_second = (tbl_end - tbl_start) * 2;
-	tb_ticks_per_jiffy = tb_ticks_per_second / HZ;
-	tb_to_us = mulhwu_scale_factor(tb_ticks_per_second, 1000000);
-}
-
-static void prpmc800_restart(char *cmd)
-{
-	ulong temp;
-
-	local_irq_disable();
-	temp = in_be32((uint *) HARRIER_MISC_CSR_REG);
-	temp |= HARRIER_RSTOUT;
-	out_be32((uint *) HARRIER_MISC_CSR_REG, temp);
-	while (1) ;
-}
-
-static void prpmc800_halt(void)
-{
-	local_irq_disable();
-	while (1) ;
-}
-
-static void prpmc800_power_off(void)
-{
-	prpmc800_halt();
-}
-
-static void __init prpmc800_init_IRQ(void)
-{
-	OpenPIC_InitSenses = prpmc800_openpic_initsenses;
-	OpenPIC_NumInitSenses = sizeof(prpmc800_openpic_initsenses);
-
-	/* Setup external interrupt sources. */
-	openpic_set_sources(0, 16, OpenPIC_Addr + 0x10000);
-	/* Setup internal UART interrupt source. */
-	openpic_set_sources(16, 1, OpenPIC_Addr + 0x10200);
-
-	/* Do the MPIC initialization based on the above settings. */
-	openpic_init(0);
-
-	/* enable functional exceptions for uarts and abort */
-	out_8((u8 *) HARRIER_FEEN_REG, (HARRIER_FE_UA0 | HARRIER_FE_UA1));
-	out_8((u8 *) HARRIER_FEMA_REG, ~(HARRIER_FE_UA0 | HARRIER_FE_UA1));
-}
-
-/*
- * Set BAT 3 to map 0xf0000000 to end of physical memory space.
- */
-static __inline__ void prpmc800_set_bat(void)
-{
-	mb();
-	mtspr(SPRN_DBAT1U, 0xf0001ffe);
-	mtspr(SPRN_DBAT1L, 0xf000002a);
-	mb();
-}
-
-/*
- * We need to read the Harrier memory controller
- * to properly determine this value
- */
-static unsigned long __init prpmc800_find_end_of_memory(void)
-{
-	/* Read the memory size from the Harrier XCSR */
-	return harrier_get_mem_size(PRPMC800_HARRIER_XCSR_BASE);
-}
-
-static void __init prpmc800_map_io(void)
-{
-	io_block_mapping(0x80000000, 0x80000000, 0x10000000, _PAGE_IO);
-	io_block_mapping(0xf0000000, 0xf0000000, 0x10000000, _PAGE_IO);
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	prpmc800_set_bat();
-
-	isa_io_base = PRPMC800_ISA_IO_BASE;
-	isa_mem_base = PRPMC800_ISA_MEM_BASE;
-	pci_dram_offset = PRPMC800_PCI_DRAM_OFFSET;
-
-	ppc_md.setup_arch = prpmc800_setup_arch;
-	ppc_md.show_cpuinfo = prpmc800_show_cpuinfo;
-	ppc_md.init_IRQ = prpmc800_init_IRQ;
-	ppc_md.get_irq = openpic_get_irq;
-
-	ppc_md.find_end_of_memory = prpmc800_find_end_of_memory;
-	ppc_md.setup_io_mappings = prpmc800_map_io;
-
-	ppc_md.restart = prpmc800_restart;
-	ppc_md.power_off = prpmc800_power_off;
-	ppc_md.halt = prpmc800_halt;
-
-	/* PrPMC800 has no timekeeper part */
-	ppc_md.time_init = NULL;
-	ppc_md.get_rtc_time = NULL;
-	ppc_md.set_rtc_time = NULL;
-	ppc_md.calibrate_decr = prpmc800_calibrate_decr;
-#ifdef  CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.progress = gen550_progress;
-#else				/* !CONFIG_SERIAL_TEXT_DEBUG */
-	ppc_md.progress = NULL;
-#endif				/* CONFIG_SERIAL_TEXT_DEBUG */
-}
diff --git a/arch/ppc/platforms/prpmc800.h b/arch/ppc/platforms/prpmc800.h
deleted file mode 100644
index 26f604e05cf..00000000000
--- a/arch/ppc/platforms/prpmc800.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * arch/ppc/platforms/prpmc800.h
- *
- * Definitions for Motorola PrPMC800 board support
- *
- * Author: Dale Farnsworth <dale.farnsworth@mvista.com>
- *
- * 2001-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
- /*
-  * From Processor to PCI:
-  *   PCI Mem Space: 0x80000000 - 0xa0000000 -> 0x80000000 - 0xa0000000 (512 MB)
-  *   PCI I/O Space: 0xfe400000 - 0xfeef0000 -> 0x00000000 - 0x00b00000 (11 MB)
-  *      Note: Must skip 0xfe000000-0xfe400000 for CONFIG_HIGHMEM/PKMAP area
-  *
-  * From PCI to Processor:
-  *   System Memory: 0x00000000 -> 0x00000000
-  */
-
-#ifndef __ASMPPC_PRPMC800_H
-#define __ASMPPC_PRPMC800_H
-
-#define PRPMC800_PCI_CONFIG_ADDR		0xfe000cf8
-#define PRPMC800_PCI_CONFIG_DATA		0xfe000cfc
-
-#define PRPMC800_PROC_PCI_IO_START		0xfe400000U
-#define PRPMC800_PROC_PCI_IO_END		0xfeefffffU
-#define PRPMC800_PCI_IO_START			0x00000000U
-#define PRPMC800_PCI_IO_END			0x00afffffU
-
-#define PRPMC800_PROC_PCI_MEM_START		0x80000000U
-#define PRPMC800_PROC_PCI_MEM_END		0x9fffffffU
-#define PRPMC800_PCI_MEM_START			0x80000000U
-#define PRPMC800_PCI_MEM_END			0x9fffffffU
-
-#define PRPMC800_NM_PROC_PCI_MEM_START		0x40000000U
-#define PRPMC800_NM_PROC_PCI_MEM_END		0xdfffffffU
-#define PRPMC800_NM_PCI_MEM_START		0x40000000U
-#define PRPMC800_NM_PCI_MEM_END			0xdfffffffU
-
-#define PRPMC800_PCI_DRAM_OFFSET		0x00000000U
-#define PRPMC800_PCI_PHY_MEM_OFFSET		0x00000000U
-
-#define PRPMC800_ISA_IO_BASE			PRPMC800_PROC_PCI_IO_START
-#define PRPMC800_ISA_MEM_BASE			0x00000000U
-
-#define PRPMC800_HARRIER_XCSR_BASE		HARRIER_DEFAULT_XCSR_BASE
-#define PRPMC800_HARRIER_MPIC_BASE		0xff000000
-
-#define PRPMC800_SERIAL_1			0xfeff00c0
-
-#define PRPMC800_BASE_BAUD			1843200
-
-/*
- * interrupt vector number and priority for harrier internal interrupt
- * sources
- */
-#define PRPMC800_INT_IRQ			16
-#define PRPMC800_INT_PRI			15
-
-/* UART Defines. */
-#define RS_TABLE_SIZE  4
-
-/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
-#define BASE_BAUD (PRPMC800_BASE_BAUD / 16)
-
-#define STD_COM_FLAGS ASYNC_BOOT_AUTOCONF
-
-/* UARTS are at IRQ 16 */
-#define STD_SERIAL_PORT_DFNS \
-        { 0, BASE_BAUD, PRPMC800_SERIAL_1, 16, STD_COM_FLAGS, /* ttyS0 */\
-		iomem_base: (unsigned char *)PRPMC800_SERIAL_1,		\
-		iomem_reg_shift: 0,					\
-		io_type: SERIAL_IO_MEM },
-
-#define SERIAL_PORT_DFNS \
-        STD_SERIAL_PORT_DFNS
-
-#endif				/* __ASMPPC_PRPMC800_H */
diff --git a/arch/ppc/platforms/radstone_ppc7d.c b/arch/ppc/platforms/radstone_ppc7d.c
deleted file mode 100644
index f1dee1e8780..00000000000
--- a/arch/ppc/platforms/radstone_ppc7d.c
+++ /dev/null
@@ -1,1492 +0,0 @@
-/*
- * Board setup routines for the Radstone PPC7D boards.
- *
- * Author: James Chapman <jchapman@katalix.com>
- *
- * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
- * Based on code done by - Mark A. Greer <mgreer@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-/* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs,
- * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse,
- * 4 serial ports, 2 high speed serial ports (MPSCs) and optional
- * SCSI / VGA.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/serial.h>
-#include <linux/tty.h>		/* for linux/serial_core.h */
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-#include <linux/mv643xx.h>
-#include <linux/netdevice.h>
-#include <linux/platform_device.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/smp.h>
-#include <asm/vga.h>
-#include <asm/open_pic.h>
-#include <asm/i8259.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/mpc10x.h>
-#include <asm/pci-bridge.h>
-#include <asm/mv64x60.h>
-
-#include "radstone_ppc7d.h"
-
-#undef DEBUG
-
-#define PPC7D_RST_PIN			17 	/* GPP17 */
-
-extern u32 mv64360_irq_base;
-extern spinlock_t rtc_lock;
-
-static struct mv64x60_handle bh;
-static int ppc7d_has_alma;
-
-extern void gen550_progress(char *, unsigned short);
-extern void gen550_init(int, struct uart_port *);
-
-/* FIXME - move to h file */
-extern int ds1337_do_command(int id, int cmd, void *arg);
-#define DS1337_GET_DATE         0
-#define DS1337_SET_DATE         1
-
-/* residual data */
-unsigned char __res[sizeof(bd_t)];
-
-/*****************************************************************************
- * Serial port code
- *****************************************************************************/
-
-#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
-static void __init ppc7d_early_serial_map(void)
-{
-#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
-	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
-#elif defined(CONFIG_SERIAL_8250)
-	struct uart_port serial_req;
-
-	/* Setup serial port access */
-	memset(&serial_req, 0, sizeof(serial_req));
-	serial_req.uartclk = UART_CLK;
-	serial_req.irq = 4;
-	serial_req.flags = STD_COM_FLAGS;
-	serial_req.iotype = UPIO_MEM;
-	serial_req.membase = (u_char *) PPC7D_SERIAL_0;
-
-	gen550_init(0, &serial_req);
-	if (early_serial_setup(&serial_req) != 0)
-		printk(KERN_ERR "Early serial init of port 0 failed\n");
-
-	/* Assume early_serial_setup() doesn't modify serial_req */
-	serial_req.line = 1;
-	serial_req.irq = 3;
-	serial_req.membase = (u_char *) PPC7D_SERIAL_1;
-
-	gen550_init(1, &serial_req);
-	if (early_serial_setup(&serial_req) != 0)
-		printk(KERN_ERR "Early serial init of port 1 failed\n");
-#else
-#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
-#endif
-}
-#endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
-
-/*****************************************************************************
- * Low-level board support code
- *****************************************************************************/
-
-static unsigned long __init ppc7d_find_end_of_memory(void)
-{
-	bd_t *bp = (bd_t *) __res;
-
-	if (bp->bi_memsize)
-		return bp->bi_memsize;
-
-	return (256 * 1024 * 1024);
-}
-
-static void __init ppc7d_map_io(void)
-{
-	/* remove temporary mapping */
-	mtspr(SPRN_DBAT3U, 0x00000000);
-	mtspr(SPRN_DBAT3L, 0x00000000);
-
-	io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO);
-	io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
-}
-
-static void ppc7d_restart(char *cmd)
-{
-	u32 data;
-
-	/* Disable GPP17 interrupt */
-	data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
-	data &= ~(1 << PPC7D_RST_PIN);
-	mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
-
-	/* Configure MPP17 as GPP */
-	data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
-	data &= ~(0x0000000f << 4);
-	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
-
-	/* Enable pin GPP17 for output */
-	data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
-	data |= (1 << PPC7D_RST_PIN);
-	mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
-
-	/* Toggle GPP9 pin to reset the board */
-	mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN);
-	mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN);
-
-	for (;;) ;		/* Spin until reset happens */
-	/* NOTREACHED */
-}
-
-static void ppc7d_power_off(void)
-{
-	u32 data;
-
-	local_irq_disable();
-
-	/* Ensure that internal MV643XX watchdog is disabled.
-	 * The Disco watchdog uses MPP17 on this hardware.
-	 */
-	data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
-	data &= ~(0x0000000f << 4);
-	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
-
-	data = mv64x60_read(&bh, MV64x60_WDT_WDC);
-	if (data & 0x80000000) {
-		mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24);
-		mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24);
-	}
-
-	for (;;) ;		/* No way to shut power off with software */
-	/* NOTREACHED */
-}
-
-static void ppc7d_halt(void)
-{
-	ppc7d_power_off();
-	/* NOTREACHED */
-}
-
-static unsigned long ppc7d_led_no_pulse;
-
-static int __init ppc7d_led_pulse_disable(char *str)
-{
-	ppc7d_led_no_pulse = 1;
-	return 1;
-}
-
-/* This kernel option disables the heartbeat pulsing of a board LED */
-__setup("ledoff", ppc7d_led_pulse_disable);
-
-static void ppc7d_heartbeat(void)
-{
-	u32 data32;
-	u8 data8;
-	static int max706_wdog = 0;
-
-	/* Unfortunately we can't access the LED control registers
-	 * during early init because they're on the CPLD which is the
-	 * other side of a PCI bridge which goes unreachable during
-	 * PCI scan. So write the LEDs only if the MV64360 watchdog is
-	 * enabled (i.e. userspace apps are running so kernel is up)..
-	 */
-	data32 = mv64x60_read(&bh, MV64x60_WDT_WDC);
-	if (data32 & 0x80000000) {
-		/* Enable MAX706 watchdog if not done already */
-		if (!max706_wdog) {
-			outb(3, PPC7D_CPLD_RESET);
-			max706_wdog = 1;
-		}
-
-		/* Hit the MAX706 watchdog */
-		outb(0, PPC7D_CPLD_WATCHDOG_TRIG);
-
-		/* Pulse LED DS219 if not disabled */
-		if (!ppc7d_led_no_pulse) {
-			static int led_on = 0;
-
-			data8 = inb(PPC7D_CPLD_LEDS);
-			if (led_on)
-				data8 &= ~PPC7D_CPLD_LEDS_DS219_MASK;
-			else
-				data8 |= PPC7D_CPLD_LEDS_DS219_MASK;
-
-			outb(data8, PPC7D_CPLD_LEDS);
-			led_on = !led_on;
-		}
-	}
-	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
-}
-
-static int ppc7d_show_cpuinfo(struct seq_file *m)
-{
-	u8 val;
-	u8 val1, val2;
-	static int flash_sizes[4] = { 64, 32, 0, 16 };
-	static int flash_banks[4] = { 4, 3, 2, 1 };
-	static int sdram_bank_sizes[4] = { 128, 256, 512, 1 };
-	int sdram_num_banks = 2;
-	static char *pci_modes[] = { "PCI33", "PCI66",
-		"Unknown", "Unknown",
-		"PCIX33", "PCIX66",
-		"PCIX100", "PCIX133"
-	};
-
-	seq_printf(m, "vendor\t\t: Radstone Technology\n");
-	seq_printf(m, "machine\t\t: PPC7D\n");
-
-	val = inb(PPC7D_CPLD_BOARD_REVISION);
-	val1 = (val & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
-	val2 = (val & PPC7D_CPLD_BOARD_REVISION_LETTER_MASK);
-	seq_printf(m, "revision\t: %hd%c%c\n",
-		   val1,
-		   (val2 <= 0x18) ? 'A' + val2 : 'Y',
-		   (val2 > 0x18) ? 'A' + (val2 - 0x19) : ' ');
-
-	val = inb(PPC7D_CPLD_MOTHERBOARD_TYPE);
-	val1 = val & PPC7D_CPLD_MB_TYPE_PLL_MASK;
-	val2 = val & (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK |
-		      PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK);
-	seq_printf(m, "bus speed\t: %dMHz\n",
-		   (val1 == PPC7D_CPLD_MB_TYPE_PLL_133) ? 133 :
-		   (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 :
-		   (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0);
-
-	val = inb(PPC7D_CPLD_MEM_CONFIG);
-	if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--;
-
-	val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND);
-	val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6;
-	seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c",
-		   sdram_num_banks,
-		   sdram_bank_sizes[val1],
-		   (sdram_bank_sizes[val1] < 128) ? 'G' : 'M',
-		   sdram_num_banks * sdram_bank_sizes[val1],
-		   (sdram_bank_sizes[val1] < 128) ? 'G' : 'M');
-	if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) {
-		seq_printf(m, " [ECC %sabled]",
-			   (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" :
-			   "dis");
-	}
-	seq_printf(m, "\n");
-
-	val1 = (val & PPC7D_CPLD_FLASH_DEV_SIZE_MASK);
-	val2 = (val & PPC7D_CPLD_FLASH_BANK_NUM_MASK) >> 2;
-	seq_printf(m, "FLASH\t\t: %d banks of %dM, total %dM\n",
-		   flash_banks[val2], flash_sizes[val1],
-		   flash_banks[val2] * flash_sizes[val1]);
-
-	val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL);
-	val1 = inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
-	seq_printf(m, "  write links\t: %s%s%s%s\n",
-		   (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "WRITE " : "",
-		   (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "BOOT " : "",
-		   (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "USER " : "",
-		   (val & (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
-			   PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
-			   PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK)) ==
-		   0 ? "NONE" : "");
-	seq_printf(m, "  write sector h/w enables: %s%s%s%s%s\n",
-		   (val & PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK) ? "RECOVERY " :
-		   "",
-		   (val & PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK) ? "BOOT " : "",
-		   (val & PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK) ? "USER " : "",
-		   (val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ? "NVRAM " :
-		   "",
-		   (((val &
-		      (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK |
-		       PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK |
-		       PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK)) == 0)
-		    && ((val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ==
-			0)) ? "NONE" : "");
-	val1 =
-	    inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT) &
-	    (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK |
-	     PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK);
-	seq_printf(m, "  software sector enables: %s%s%s\n",
-		   (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK) ? "SYSBOOT "
-		   : "",
-		   (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK) ? "USER " : "",
-		   (val1 == 0) ? "NONE " : "");
-
-	seq_printf(m, "Boot options\t: %s%s%s%s\n",
-		   (val & PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK) ?
-		   "ALTERNATE " : "",
-		   (val & PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK) ? "VME " :
-		   "",
-		   (val & PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK) ? "RECOVERY "
-		   : "",
-		   ((val &
-		     (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK |
-		      PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK |
-		      PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK)) ==
-		    0) ? "NONE" : "");
-
-	val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1);
-	seq_printf(m, "Fitted modules\t: %s%s%s%s\n",
-		   (val & PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK) ? "" : "PMC1 ",
-		   (val & PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK) ? "" : "PMC2 ",
-		   (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) ? "AFIX " : "",
-		   ((val & (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
-			    PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK |
-			    PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK)) ==
-		    (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
-		     PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK)) ? "NONE" : "");
-
-	if (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) {
-		static const char *ids[] = {
-			"unknown",
-			"1553 (Dual Channel)",
-			"1553 (Single Channel)",
-			"8-bit SCSI + VGA",
-			"16-bit SCSI + VGA",
-			"1553 (Single Channel with sideband)",
-			"1553 (Dual Channel with sideband)",
-			NULL
-		};
-		u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03);
-		seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id,
-			   id < 7 ? ids[id] : "unknown");
-	}
-
-	val = inb(PPC7D_CPLD_PCI_CONFIG);
-	val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4;
-	val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK);
-	seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n",
-		   pci_modes[val1], pci_modes[val2]);
-
-	val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
-	seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n",
-		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v",
-		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v");
-	seq_printf(m, "PMC power source: %s\n",
-		   (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" :
-		   "internal");
-
-	val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4);
-	val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
-	seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n",
-		   (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "",
-		   (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "",
-		   (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "",
-		   (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "",
-		   (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "",
-		   (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "",
-		   (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " :
-		   "");
-
-	val = inb(PPC7D_CPLD_ID_LINK);
-	val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK |
-		      PPC7D_CPLD_ID_LINK_E7_MASK |
-		      PPC7D_CPLD_ID_LINK_E12_MASK |
-		      PPC7D_CPLD_ID_LINK_E13_MASK);
-
-	val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) &
-	    (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
-	     PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
-	     PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK);
-
-	seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n",
-		   (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "",
-		   (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "",
-		   (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "",
-		   (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "",
-		   (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "",
-		   (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "",
-		   (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "",
-		   ((val == 0) && (val1 == 0)) ? "NONE" : "");
-
-	val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK);
-	seq_printf(m, "Front panel reset switch: %sabled\n",
-		   (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en");
-
-	return 0;
-}
-
-static void __init ppc7d_calibrate_decr(void)
-{
-	ulong freq;
-
-	freq = 100000000 / 4;
-
-	pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n",
-		 freq / 1000000, freq % 1000000);
-
-	tb_ticks_per_jiffy = freq / HZ;
-	tb_to_us = mulhwu_scale_factor(freq, 1000000);
-}
-
-/*****************************************************************************
- * Interrupt stuff
- *****************************************************************************/
-
-static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id)
-{
-	u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
-	if (temp & (1 << 28)) {
-		i8259_irq();
-		mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28)));
-		return IRQ_HANDLED;
-	}
-
-	return IRQ_NONE;
-}
-
-/*
- * Each interrupt cause is assigned an IRQ number.
- * Southbridge has 16*2 (two 8259's) interrupts.
- * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
- * If multiple interrupts are pending, get_irq() returns the
- * lowest pending irq number first.
- *
- *
- * IRQ #   Source                              Trig   Active
- * =============================================================
- *
- * Southbridge
- * -----------
- * IRQ #   Source                              Trig
- * =============================================================
- * 0       ISA High Resolution Counter         Edge
- * 1       Keyboard                            Edge
- * 2       Cascade From (IRQ 8-15)             Edge
- * 3       Com 2 (Uart 2)                      Edge
- * 4       Com 1 (Uart 1)                      Edge
- * 5       PCI Int D/AFIX IRQZ ID4 (2,7)       Level
- * 6       GPIO                                Level
- * 7       LPT                                 Edge
- * 8       RTC Alarm                           Edge
- * 9       PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
- * 10      PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
- * 11      USB2                                Level
- * 12      Mouse                               Edge
- * 13      Reserved internally by Ali M1535+
- * 14      PCI Int C/VME/AFIX IRQY ID3 (2,6)   Level
- * 15      COM 5/6                             Level
- *
- * 16..112 Discovery-II...
- *
- * MPP28   Southbridge                         Edge   High
- *
- *
- * Interrupts are cascaded through to the Discovery-II.
- *
- *  PCI ---
- *         \
- * CPLD --> ALI1535 -------> DISCOVERY-II
- *        INTF           MPP28
- */
-static void __init ppc7d_init_irq(void)
-{
-	int irq;
-
-	pr_debug("%s\n", __func__);
-	i8259_init(0, 0);
-	mv64360_init_irq();
-
-	/* IRQs 5,6,9,10,11,14,15 are level sensitive */
-	irq_desc[5].status |= IRQ_LEVEL;
-	irq_desc[6].status |= IRQ_LEVEL;
-	irq_desc[9].status |= IRQ_LEVEL;
-	irq_desc[10].status |= IRQ_LEVEL;
-	irq_desc[11].status |= IRQ_LEVEL;
-	irq_desc[14].status |= IRQ_LEVEL;
-	irq_desc[15].status |= IRQ_LEVEL;
-
-	/* GPP28 is edge triggered */
-	irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL;
-}
-
-static u32 ppc7d_irq_canonicalize(u32 irq)
-{
-	if ((irq >= 16) && (irq < (16 + 96)))
-		irq -= 16;
-
-	return irq;
-}
-
-static int ppc7d_get_irq(void)
-{
-	int irq;
-
-	irq = mv64360_get_irq();
-	if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
-		irq = i8259_irq();
-	return irq;
-}
-
-/*
- * 9       PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
- * 10      PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
- * 14      PCI Int C/VME/AFIX IRQY ID3 (2,6)   Level
- * 5       PCI Int D/AFIX IRQZ ID4 (2,7)       Level
- */
-static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel,
-				unsigned char pin)
-{
-	static const char pci_irq_table[][4] =
-	    /*
-	     *      PCI IDSEL/INTPIN->INTLINE
-	     *         A   B   C   D
-	     */
-	{
-		{10, 14, 5, 9},	/* IDSEL 10 - PMC2 / AFIX IRQW */
-		{9, 10, 14, 5},	/* IDSEL 11 - PMC1 / AFIX IRQX */
-		{5, 9, 10, 14},	/* IDSEL 12 - AFIX IRQY */
-		{14, 5, 9, 10},	/* IDSEL 13 - AFIX IRQZ */
-	};
-	const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4;
-
-	pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __func__,
-		 dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin);
-
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-void __init ppc7d_intr_setup(void)
-{
-	u32 data;
-
-	/*
-	 * Define GPP 28 interrupt polarity as active high
-	 * input signal and level triggered
-	 */
-	data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL);
-	data &= ~(1 << 28);
-	mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data);
-	data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
-	data &= ~(1 << 28);
-	mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
-
-	/* Config GPP intr ctlr to respond to level trigger */
-	data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL);
-	data |= (1 << 10);
-	mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data);
-
-	/* XXXX Erranum FEr PCI-#8 */
-	data = mv64x60_read(&bh, MV64x60_PCI0_CMD);
-	data &= ~((1 << 5) | (1 << 9));
-	mv64x60_write(&bh, MV64x60_PCI0_CMD, data);
-	data = mv64x60_read(&bh, MV64x60_PCI1_CMD);
-	data &= ~((1 << 5) | (1 << 9));
-	mv64x60_write(&bh, MV64x60_PCI1_CMD, data);
-
-	/*
-	 * Dismiss and then enable interrupt on GPP interrupt cause
-	 * for CPU #0
-	 */
-	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28));
-	data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
-	data |= (1 << 28);
-	mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
-
-	/*
-	 * Dismiss and then enable interrupt on CPU #0 high cause reg
-	 * BIT27 summarizes GPP interrupts 23-31
-	 */
-	mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27));
-	data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI);
-	data |= (1 << 27);
-	mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data);
-}
-
-/*****************************************************************************
- * Platform device data fixup routines.
- *****************************************************************************/
-
-#if defined(CONFIG_SERIAL_MPSC)
-static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev)
-{
-	struct mpsc_pdata *pdata;
-
-	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
-
-	pdata->max_idle = 40;
-	pdata->default_baud = PPC7D_DEFAULT_BAUD;
-	pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC;
-	pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ;
-
-	return;
-}
-#endif
-
-#if defined(CONFIG_MV643XX_ETH)
-static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev)
-{
-	struct mv643xx_eth_platform_data *eth_pd;
-	static u16 phy_addr[] = {
-		PPC7D_ETH0_PHY_ADDR,
-		PPC7D_ETH1_PHY_ADDR,
-		PPC7D_ETH2_PHY_ADDR,
-	};
-	int i;
-
-	eth_pd = pdev->dev.platform_data;
-	eth_pd->force_phy_addr = 1;
-	eth_pd->phy_addr = phy_addr[pdev->id];
-	eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE;
-	eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE;
-
-	/* Adjust IRQ by mv64360_irq_base */
-	for (i = 0; i < pdev->num_resources; i++) {
-		struct resource *r = &pdev->resource[i];
-
-		if (r->flags & IORESOURCE_IRQ) {
-			r->start += mv64360_irq_base;
-			r->end += mv64360_irq_base;
-			pr_debug("%s, uses IRQ %d\n", pdev->name,
-				 (int)r->start);
-		}
-	}
-
-}
-#endif
-
-#if defined(CONFIG_I2C_MV64XXX)
-static void __init
-ppc7d_fixup_i2c_pdata(struct platform_device *pdev)
-{
-	struct mv64xxx_i2c_pdata *pdata;
-	int i;
-
-	pdata = pdev->dev.platform_data;
-	if (pdata == NULL) {
-		pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
-		if (pdata == NULL)
-			return;
-
-		pdev->dev.platform_data = pdata;
-	}
-
-	/* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
-	pdata->freq_m = 8;
-	pdata->freq_n = 3;
-	pdata->timeout = 500;
-	pdata->retries = 3;
-
-	/* Adjust IRQ by mv64360_irq_base */
-	for (i = 0; i < pdev->num_resources; i++) {
-		struct resource *r = &pdev->resource[i];
-
-		if (r->flags & IORESOURCE_IRQ) {
-			r->start += mv64360_irq_base;
-			r->end += mv64360_irq_base;
-			pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start);
-		}
-	}
-}
-#endif
-
-static int ppc7d_platform_notify(struct device *dev)
-{
-	static struct {
-		char *bus_id;
-		void ((*rtn) (struct platform_device * pdev));
-	} dev_map[] = {
-#if defined(CONFIG_SERIAL_MPSC)
-		{ MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata },
-		{ MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata },
-#endif
-#if defined(CONFIG_MV643XX_ETH)
-		{ MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata },
-		{ MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata },
-#endif
-#if defined(CONFIG_I2C_MV64XXX)
-		{ MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata },
-#endif
-	};
-	struct platform_device *pdev;
-	int i;
-
-	if (dev && dev->bus_id)
-		for (i = 0; i < ARRAY_SIZE(dev_map); i++)
-			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
-				     BUS_ID_SIZE)) {
-
-				pdev = container_of(dev,
-						    struct platform_device,
-						    dev);
-				dev_map[i].rtn(pdev);
-			}
-
-	return 0;
-}
-
-/*****************************************************************************
- * PCI device fixups.
- * These aren't really fixups per se. They are used to init devices as they
- * are found during PCI scan.
- *
- * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI
- * scan in order to find other devices on its secondary side.
- *****************************************************************************/
-
-static void __init ppc7d_fixup_hb8(struct pci_dev *dev)
-{
-	u16 val16;
-
-	if (dev->bus->number == 0) {
-		pr_debug("PCI: HB8 init\n");
-
-		pci_write_config_byte(dev, 0x1c,
-				      ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000)
-				       >> 8) | 0x01);
-		pci_write_config_byte(dev, 0x1d,
-				      (((PPC7D_PCI0_IO_START_PCI_ADDR +
-					 PPC7D_PCI0_IO_SIZE -
-					 1) & 0xf000) >> 8) | 0x01);
-		pci_write_config_word(dev, 0x30,
-				      PPC7D_PCI0_IO_START_PCI_ADDR >> 16);
-		pci_write_config_word(dev, 0x32,
-				      ((PPC7D_PCI0_IO_START_PCI_ADDR +
-					PPC7D_PCI0_IO_SIZE -
-					1) >> 16) & 0xffff);
-
-		pci_write_config_word(dev, 0x20,
-				      PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16);
-		pci_write_config_word(dev, 0x22,
-				      ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR +
-					PPC7D_PCI0_MEM0_SIZE -
-					1) >> 16) & 0xffff);
-		pci_write_config_word(dev, 0x24, 0);
-		pci_write_config_word(dev, 0x26, 0);
-		pci_write_config_dword(dev, 0x28, 0);
-		pci_write_config_dword(dev, 0x2c, 0);
-
-		pci_read_config_word(dev, 0x3e, &val16);
-		val16 |= ((1 << 5) | (1 << 1));	/* signal master aborts and
-						 * SERR to primary
-						 */
-		val16 &= ~(1 << 2);		/* ISA disable, so all ISA
-						 * ports forwarded to secondary
-						 */
-		pci_write_config_word(dev, 0x3e, val16);
-	}
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8);
-
-/* This should perhaps be a separate driver as we're actually initializing
- * the chip for this board here. It's hardly a fixup...
- */
-static void __init ppc7d_fixup_ali1535(struct pci_dev *dev)
-{
-	pr_debug("PCI: ALI1535 init\n");
-
-	if (dev->bus->number == 1) {
-		/* Configure the ISA Port Settings */
-		pci_write_config_byte(dev, 0x43, 0x00);
-
-		/* Disable PCI Interrupt polling mode */
-		pci_write_config_byte(dev, 0x45, 0x00);
-
-		/* Multifunction pin select INTFJ -> INTF */
-		pci_write_config_byte(dev, 0x78, 0x00);
-
-		/* Set PCI INT -> IRQ Routing control in for external
-		 * pins south bridge.
-		 */
-		pci_write_config_byte(dev, 0x48, 0x31);	/* [7-4] INT B -> IRQ10
-							 * [3-0] INT A -> IRQ9
-							 */
-		pci_write_config_byte(dev, 0x49, 0x5D);	/* [7-4] INT D -> IRQ5
-							 * [3-0] INT C -> IRQ14
-							 */
-
-		/* PPC7D setup */
-		/* NEC USB device on IRQ 11 (INTE) - INTF disabled */
-		pci_write_config_byte(dev, 0x4A, 0x09);
-
-		/* GPIO on IRQ 6 */
-		pci_write_config_byte(dev, 0x76, 0x07);
-
-		/* SIRQ I (COMS 5/6) use IRQ line 15.
-		 * Positive (not subtractive) address decode.
-		 */
-		pci_write_config_byte(dev, 0x44, 0x0f);
-
-		/* SIRQ II disabled */
-		pci_write_config_byte(dev, 0x75, 0x0);
-
-		/* On board USB and RTC disabled */
-		pci_write_config_word(dev, 0x52, (1 << 14));
-		pci_write_config_byte(dev, 0x74, 0x00);
-
-		/* On board IDE disabled */
-		pci_write_config_byte(dev, 0x58, 0x00);
-
-		/* Decode 32-bit addresses */
-		pci_write_config_byte(dev, 0x5b, 0);
-
-		/* Disable docking IO */
-		pci_write_config_word(dev, 0x5c, 0x0000);
-
-		/* Disable modem, enable sound */
-		pci_write_config_byte(dev, 0x77, (1 << 6));
-
-		/* Disable hot-docking mode */
-		pci_write_config_byte(dev, 0x7d, 0x00);
-	}
-}
-
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535);
-
-static int ppc7d_pci_exclude_device(u8 bus, u8 devfn)
-{
-	/* Early versions of this board were fitted with IBM ALMA
-	 * PCI-VME bridge chips. The PCI config space of these devices
-	 * was not set up correctly and causes PCI scan problems.
-	 */
-	if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma)
-		return PCIBIOS_DEVICE_NOT_FOUND;
-
-	return mv64x60_pci_exclude_device(bus, devfn);
-}
-
-/* This hook is called when each PCI bus is probed.
- */
-static void ppc7d_pci_fixup_bus(struct pci_bus *bus)
-{
-	pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n",
-		 bus->number,
-		 bus->resource[0] ? bus->resource[0]->start : 0,
-		 bus->resource[0] ? bus->resource[0]->end : 0,
-		 bus->resource[1] ? bus->resource[1]->start : 0,
-		 bus->resource[1] ? bus->resource[1]->end : 0,
-		 bus->resource[2] ? bus->resource[2]->start : 0,
-		 bus->resource[2] ? bus->resource[2]->end : 0,
-		 bus->resource[3] ? bus->resource[3]->start : 0,
-		 bus->resource[3] ? bus->resource[3]->end : 0);
-
-	if ((bus->number == 1) && (bus->resource[2] != NULL)) {
-		/* Hide PCI window 2 of Bus 1 which is used only to
-		 * map legacy ISA memory space.
-		 */
-		bus->resource[2]->start = 0;
-		bus->resource[2]->end = 0;
-		bus->resource[2]->flags = 0;
-	}
-}
-
-/*****************************************************************************
- * Board device setup code
- *****************************************************************************/
-
-void __init ppc7d_setup_peripherals(void)
-{
-	u32 val32;
-
-	/* Set up windows for boot CS */
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
-				 PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE,
-				 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
-
-	/* Boot firmware configures the following DevCS addresses.
-	 * DevCS0 - board control/status
-	 * DevCS1 - test registers
-	 * DevCS2 - AFIX port/address registers (for identifying)
-	 * DevCS3 - FLASH
-	 *
-	 * We don't use DevCS0, DevCS1.
-	 */
-	val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE);
-	val32 |= ((1 << 4) | (1 << 5));
-	mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32);
-	mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0);
-	mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0);
-	mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0);
-	mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
-				 PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
-				 PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
-
-	mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
-				 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
-				 0);
-	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
-
-	/* Set up Enet->SRAM window */
-	mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
-				 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
-				 0x2);
-	bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
-
-	/* Give enet r/w access to memory region */
-	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0);
-	val32 |= (0x3 << (4 << 1));
-	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32);
-	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1);
-	val32 |= (0x3 << (4 << 1));
-	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32);
-	val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2);
-	val32 |= (0x3 << (4 << 1));
-	mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32);
-
-	val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL);
-	val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24));
-	mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32);
-
-	/* Enumerate pci bus.
-	 *
-	 * We scan PCI#0 first (the bus with the HB8 and other
-	 * on-board peripherals). We must configure the 64360 before
-	 * each scan, according to the bus number assignments.  Busses
-	 * are assigned incrementally, starting at 0.  PCI#0 is
-	 * usually assigned bus#0, the secondary side of the HB8 gets
-	 * bus#1 and PCI#1 (second PMC site) gets bus#2.  However, if
-	 * any PMC card has a PCI bridge, these bus assignments will
-	 * change.
-	 */
-
-	/* Turn off PCI retries */
-	val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
-	val32 |= (1 << 17);
-	mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
-
-	/* Scan PCI#0 */
-	mv64x60_set_bus(&bh, 0, 0);
-	bh.hose_a->first_busno = 0;
-	bh.hose_a->last_busno = 0xff;
-	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
-	printk(KERN_INFO "PCI#0: first=%d last=%d\n",
-	       bh.hose_a->first_busno, bh.hose_a->last_busno);
-
-	/* Scan PCI#1 */
-	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
-	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
-	bh.hose_b->last_busno = 0xff;
-	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
-		bh.hose_b->first_busno);
-	printk(KERN_INFO "PCI#1: first=%d last=%d\n",
-	       bh.hose_b->first_busno, bh.hose_b->last_busno);
-
-	/* Turn on PCI retries */
-	val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
-	val32 &= ~(1 << 17);
-	mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
-
-	/* Setup interrupts */
-	ppc7d_intr_setup();
-}
-
-static void __init ppc7d_setup_bridge(void)
-{
-	struct mv64x60_setup_info si;
-	int i;
-	u32 temp;
-
-	mv64360_irq_base = 16;	/* first 16 intrs are 2 x 8259's */
-
-	memset(&si, 0, sizeof(si));
-
-	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
-
-	si.pci_0.enable_bus = 1;
-	si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR;
-	si.pci_0.pci_io.pci_base_hi = 0;
-	si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR;
-	si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE;
-	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR;
-	si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR;
-	si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
-	si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE;
-	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR;
-	si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR;
-	si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR;
-	si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE;
-	si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_0.pci_cmd_bits = 0;
-	si.pci_0.latency_timer = 0x80;
-
-	si.pci_1.enable_bus = 1;
-	si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR;
-	si.pci_1.pci_io.pci_base_hi = 0;
-	si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR;
-	si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE;
-	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR;
-	si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR;
-	si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
-	si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE;
-	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR;
-	si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR;
-	si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR;
-	si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE;
-	si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
-	si.pci_1.pci_cmd_bits = 0;
-	si.pci_1.latency_timer = 0x80;
-
-	/* Don't clear the SRAM window since we use it for debug */
-	si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN);
-
-	printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n",
-	       si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size);
-	printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n",
-	       si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size);
-
-	for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-		si.cpu_prot_options[i] = 0;
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
-
-		si.pci_0.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-
-		si.pci_1.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_NONE |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
-#else
-		si.cpu_prot_options[i] = 0;
-		/* All PPC7D hardware uses B0 or newer MV64360 silicon which
-		 * does not have snoop bugs.
-		 */
-		si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
-		si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
-		si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
-
-		si.pci_0.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
-
-		si.pci_1.acc_cntl_options[i] =
-		    MV64360_PCI_ACC_CNTL_SNOOP_WB |
-		    MV64360_PCI_ACC_CNTL_SWAP_NONE |
-		    MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
-		    MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
-#endif
-	}
-
-	/* Lookup PCI host bridges */
-	if (mv64x60_init(&bh, &si))
-		printk(KERN_ERR "MV64360 initialization failed.\n");
-
-	pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base);
-
-	/* Enable WB Cache coherency on SRAM */
-	temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG);
-	pr_debug("SRAM_CONFIG: %x\n", temp);
-#if defined(CONFIG_NOT_COHERENT_CACHE)
-	mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2);
-#else
-	mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2);
-#endif
-	/* If system operates with internal bus arbiter (CPU master
-	 * control bit8) clear AACK Delay bit [25] in CPU
-	 * configuration register.
-	 */
-	temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL);
-	if (temp & (1 << 8)) {
-		temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
-		mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25)));
-	}
-
-	/* Data and address parity is enabled */
-	temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
-	mv64x60_write(&bh, MV64x60_CPU_CONFIG,
-		      (temp | (1 << 26) | (1 << 19)));
-
-	pci_dram_offset = 0;	/* sys mem at same addr on PCI & cpu bus */
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = ppc7d_map_irq;
-	ppc_md.pci_exclude_device = ppc7d_pci_exclude_device;
-
-	mv64x60_set_bus(&bh, 0, 0);
-	bh.hose_a->first_busno = 0;
-	bh.hose_a->last_busno = 0xff;
-	bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
-	bh.hose_a->mem_space.end =
-	    PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE;
-
-	/* These will be set later, as a result of PCI0 scan */
-	bh.hose_b->first_busno = 0;
-	bh.hose_b->last_busno = 0xff;
-	bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
-	bh.hose_b->mem_space.end =
-	    PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE;
-
-	pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n",
-		 mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50),
-		 mv64x60_read(&bh, 0xf0));
-}
-
-static void __init ppc7d_setup_arch(void)
-{
-	int port;
-
-	loops_per_jiffy = 100000000 / HZ;
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef	CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_HDA1;
-#endif
-
-	if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) ||
-	    (cur_cpu_spec->cpu_features & CPU_FTR_L3CR))
-		/* 745x is different.  We only want to pass along enable. */
-		_set_L2CR(L2CR_L2E);
-	else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR)
-		/* All modules have 1MB of L2.  We also assume that an
-		 * L2 divisor of 3 will work.
-		 */
-		_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
-			  | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
-
-	if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)
-		/* No L3 cache */
-		_set_L3CR(0);
-
-#ifdef CONFIG_DUMMY_CONSOLE
-	conswitchp = &dummy_con;
-#endif
-
-	/* Lookup PCI host bridges */
-	if (ppc_md.progress)
-		ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0);
-
-	ppc7d_setup_bridge();
-	ppc7d_setup_peripherals();
-
-	/* Disable ethernet. It might have been setup by the bootrom */
-	for (port = 0; port < 3; port++)
-		mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port),
-			      0x0000ff00);
-
-	/* Clear queue pointers to ensure they are all initialized,
-	 * otherwise since queues 1-7 are unused, they have random
-	 * pointers which look strange in register dumps. Don't bother
-	 * with queue 0 since it will be initialized later.
-	 */
-	for (port = 0; port < 3; port++) {
-		mv64x60_write(&bh,
-			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port),
-			      0x00000000);
-		mv64x60_write(&bh,
-			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port),
-			      0x00000000);
-		mv64x60_write(&bh,
-			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port),
-			      0x00000000);
-		mv64x60_write(&bh,
-			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port),
-			      0x00000000);
-		mv64x60_write(&bh,
-			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port),
-			      0x00000000);
-		mv64x60_write(&bh,
-			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port),
-			      0x00000000);
-		mv64x60_write(&bh,
-			      MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port),
-			      0x00000000);
-	}
-
-	printk(KERN_INFO "Radstone Technology PPC7D\n");
-	if (ppc_md.progress)
-		ppc_md.progress("ppc7d_setup_arch: exit", 0);
-
-}
-
-/* Real Time Clock support.
- * PPC7D has a DS1337 accessed by I2C.
- */
-static ulong ppc7d_get_rtc_time(void)
-{
-        struct rtc_time tm;
-        int result;
-
-        spin_lock(&rtc_lock);
-        result = ds1337_do_command(0, DS1337_GET_DATE, &tm);
-        spin_unlock(&rtc_lock);
-
-        if (result == 0)
-                result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
-
-        return result;
-}
-
-static int ppc7d_set_rtc_time(unsigned long nowtime)
-{
-        struct rtc_time tm;
-        int result;
-
-        spin_lock(&rtc_lock);
-        to_tm(nowtime, &tm);
-        result = ds1337_do_command(0, DS1337_SET_DATE, &tm);
-        spin_unlock(&rtc_lock);
-
-        return result;
-}
-
-/* This kernel command line parameter can be used to have the target
- * wait for a JTAG debugger to attach. Of course, a JTAG debugger
- * with hardware breakpoint support can have the target stop at any
- * location during init, but this is a convenience feature that makes
- * it easier in the common case of loading the code using the ppcboot
- * bootloader..
- */
-static unsigned long ppc7d_wait_debugger;
-
-static int __init ppc7d_waitdbg(char *str)
-{
-	ppc7d_wait_debugger = 1;
-	return 1;
-}
-
-__setup("waitdbg", ppc7d_waitdbg);
-
-/* Second phase board init, called after other (architecture common)
- * low-level services have been initialized.
- */
-static void ppc7d_init2(void)
-{
-	unsigned long flags;
-	u32 data;
-	u8 data8;
-
-	pr_debug("%s: enter\n", __func__);
-
-	/* Wait for debugger? */
-	if (ppc7d_wait_debugger) {
-		printk("Waiting for debugger...\n");
-
-		while (readl(&ppc7d_wait_debugger)) ;
-	}
-
-	/* Hook up i8259 interrupt which is connected to GPP28 */
-	request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr,
-		    IRQF_DISABLED, "I8259 (GPP28) interrupt", (void *)0);
-
-	/* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */
-	spin_lock_irqsave(&mv64x60_lock, flags);
-	data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
-	data &= ~(0x0000000f << 0);
-	data |= (0x00000004 << 0);
-	data &= ~(0x0000000f << 4);
-	data |= (0x00000004 << 4);
-	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
-	spin_unlock_irqrestore(&mv64x60_lock, flags);
-
-	/* All LEDs off */
-	data8 = inb(PPC7D_CPLD_LEDS);
-	data8 &= ~0x08;
-	data8 |= 0x07;
-	outb(data8, PPC7D_CPLD_LEDS);
-
-        /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */
-        ppc_md.set_rtc_time = ppc7d_set_rtc_time;
-        ppc_md.get_rtc_time = ppc7d_get_rtc_time;
-
-	pr_debug("%s: exit\n", __func__);
-}
-
-/* Called from machine_init(), early, before any of the __init functions
- * have run. We must init software-configurable pins before other functions
- * such as interrupt controllers are initialised.
- */
-void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-			  unsigned long r6, unsigned long r7)
-{
-	u8 val8;
-	u8 rev_num;
-
-	/* Map 0xe0000000-0xffffffff early because we need access to SRAM
-	 * and the ISA memory space (for serial port) here. This mapping
-	 * is redone properly in ppc7d_map_io() later.
-	 */
-	mtspr(SPRN_DBAT3U, 0xe0003fff);
-	mtspr(SPRN_DBAT3L, 0xe000002a);
-
-	/*
-	 * Zero SRAM. Note that this generates parity errors on
-	 * internal data path in SRAM if it's first time accessing it
-	 * after reset.
-	 *
-	 * We do this ASAP to avoid parity errors when reading
-	 * uninitialized SRAM.
-	 */
-	memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE);
-
-	pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n",
-		 r3, r4, r5, r6, r7);
-
-	parse_bootinfo(find_bootinfo());
-
-	/* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
-	 * are non-zero, then we should use the board info from the bd_t
-	 * structure and the cmdline pointed to by r6 instead of the
-	 * information from birecs, if any.  Otherwise, use the information
-	 * from birecs as discovered by the preceding call to
-	 * parse_bootinfo().  This rule should work with both PPCBoot, which
-	 * uses a bd_t board info structure, and the kernel boot wrapper,
-	 * which uses birecs.
-	 */
-	if (r3 && r6) {
-		bd_t *bp = (bd_t *) __res;
-
-		/* copy board info structure */
-		memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));
-		/* copy command line */
-		*(char *)(r7 + KERNELBASE) = 0;
-		strcpy(cmd_line, (char *)(r6 + KERNELBASE));
-
-		printk(KERN_INFO "Board info data:-\n");
-		printk(KERN_INFO "  Internal freq: %lu MHz, bus freq: %lu MHz\n",
-		       bp->bi_intfreq, bp->bi_busfreq);
-		printk(KERN_INFO "  Memory: %lx, size %lx\n", bp->bi_memstart,
-		       bp->bi_memsize);
-		printk(KERN_INFO "  Console baudrate: %lu\n", bp->bi_baudrate);
-		printk(KERN_INFO "  Ethernet address: "
-		       "%02x:%02x:%02x:%02x:%02x:%02x\n",
-		       bp->bi_enetaddr[0], bp->bi_enetaddr[1],
-		       bp->bi_enetaddr[2], bp->bi_enetaddr[3],
-		       bp->bi_enetaddr[4], bp->bi_enetaddr[5]);
-	}
-#ifdef CONFIG_BLK_DEV_INITRD
-	/* take care of initrd if we have one */
-	if (r4) {
-		initrd_start = r4 + KERNELBASE;
-		initrd_end = r5 + KERNELBASE;
-		printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end);
-	}
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-	/* Map in board regs, etc. */
-	isa_io_base = 0xe8000000;
-	isa_mem_base = 0xe8000000;
-	pci_dram_offset = 0x00000000;
-	ISA_DMA_THRESHOLD = 0x00ffffff;
-	DMA_MODE_READ = 0x44;
-	DMA_MODE_WRITE = 0x48;
-
-	ppc_md.setup_arch = ppc7d_setup_arch;
-	ppc_md.init = ppc7d_init2;
-	ppc_md.show_cpuinfo = ppc7d_show_cpuinfo;
-	/* XXX this is broken... */
-	ppc_md.irq_canonicalize = ppc7d_irq_canonicalize;
-	ppc_md.init_IRQ = ppc7d_init_irq;
-	ppc_md.get_irq = ppc7d_get_irq;
-
-	ppc_md.restart = ppc7d_restart;
-	ppc_md.power_off = ppc7d_power_off;
-	ppc_md.halt = ppc7d_halt;
-
-	ppc_md.find_end_of_memory = ppc7d_find_end_of_memory;
-	ppc_md.setup_io_mappings = ppc7d_map_io;
-
-	ppc_md.time_init = NULL;
-	ppc_md.set_rtc_time = NULL;
-	ppc_md.get_rtc_time = NULL;
-	ppc_md.calibrate_decr = ppc7d_calibrate_decr;
-	ppc_md.nvram_read_val = NULL;
-	ppc_md.nvram_write_val = NULL;
-
-	ppc_md.heartbeat = ppc7d_heartbeat;
-	ppc_md.heartbeat_reset = HZ;
-	ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
-
-	ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;
-
-#if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
-    defined(CONFIG_I2C_MV64XXX)
-	platform_notify = ppc7d_platform_notify;
-#endif
-
-#ifdef CONFIG_SERIAL_MPSC
-	/* On PPC7D, we must configure MPSC support via CPLD control
-	 * registers.
-	 */
-	outb(PPC7D_CPLD_RTS_COM4_SCLK |
-	     PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS);
-	outb(PPC7D_CPLD_COMS_COM3_TCLKEN |
-	     PPC7D_CPLD_COMS_COM3_TXEN |
-	     PPC7D_CPLD_COMS_COM4_TCLKEN |
-	     PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS);
-#endif /* CONFIG_SERIAL_MPSC */
-
-#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
-	ppc7d_early_serial_map();
-#ifdef  CONFIG_SERIAL_TEXT_DEBUG
-#if defined(CONFIG_SERIAL_MPSC_CONSOLE)
-	ppc_md.progress = mv64x60_mpsc_progress;
-#elif defined(CONFIG_SERIAL_8250)
-	ppc_md.progress = gen550_progress;
-#else
-#error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
-#endif /* CONFIG_SERIAL_8250 */
-#endif /* CONFIG_SERIAL_TEXT_DEBUG */
-#endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
-
-	/* Enable write access to user flash.  This is necessary for
-	 * flash probe.
-	 */
-	val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
-	writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED &
-		       PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK),
-	       (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
-
-	/* Determine if this board has IBM ALMA VME devices */
-	val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION);
-	rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
-	if (rev_num <= 1)
-		ppc7d_has_alma = 1;
-
-#ifdef DEBUG
-	console_printk[0] = 8;
-#endif
-}
diff --git a/arch/ppc/platforms/radstone_ppc7d.h b/arch/ppc/platforms/radstone_ppc7d.h
deleted file mode 100644
index 2bb093a0c03..00000000000
--- a/arch/ppc/platforms/radstone_ppc7d.h
+++ /dev/null
@@ -1,433 +0,0 @@
-/*
- * Board definitions for the Radstone PPC7D boards.
- *
- * Author: James Chapman <jchapman@katalix.com>
- *
- * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
- * Based on code done by - Mark A. Greer <mgreer@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-/*
- * The MV64360 has 2 PCI buses each with 1 window from the CPU bus to
- * PCI I/O space and 4 windows from the CPU bus to PCI MEM space.
- * We'll only use one PCI MEM window on each PCI bus.
- *
- * This is the CPU physical memory map (windows must be at least 1MB
- * and start on a boundary that is a multiple of the window size):
- *
- *    0xff800000-0xffffffff      - Boot window
- *    0xff000000-0xff000fff	 - AFIX registers (DevCS2)
- *    0xfef00000-0xfef0ffff      - Internal MV64x60 registers
- *    0xfef40000-0xfef7ffff      - Internal SRAM
- *    0xfef00000-0xfef0ffff      - MV64360 Registers
- *    0x70000000-0x7fffffff      - soldered flash (DevCS3)
- *    0xe8000000-0xe9ffffff      - PCI I/O
- *    0x80000000-0xbfffffff      - PCI MEM
- */
-
-#ifndef __PPC_PLATFORMS_PPC7D_H
-#define __PPC_PLATFORMS_PPC7D_H
-
-#include <asm/ppcboot.h>
-
-/*****************************************************************************
- * CPU Physical Memory Map setup.
- *****************************************************************************/
-
-#define PPC7D_BOOT_WINDOW_BASE			0xff800000
-#define PPC7D_AFIX_REG_BASE			0xff000000
-#define PPC7D_INTERNAL_SRAM_BASE		0xfef40000
-#define PPC7D_FLASH_BASE			0x70000000
-
-#define PPC7D_BOOT_WINDOW_SIZE_ACTUAL		0x00800000 /* 8MB */
-#define PPC7D_FLASH_SIZE_ACTUAL			0x10000000 /* 256MB */
-
-#define PPC7D_BOOT_WINDOW_SIZE		max(MV64360_WINDOW_SIZE_MIN,	\
-		PPC7D_BOOT_WINDOW_SIZE_ACTUAL)
-#define PPC7D_FLASH_SIZE		max(MV64360_WINDOW_SIZE_MIN,	\
-		PPC7D_FLASH_SIZE_ACTUAL)
-#define PPC7D_AFIX_REG_SIZE		max(MV64360_WINDOW_SIZE_MIN, 0xff)
-
-
-#define PPC7D_PCI0_MEM0_START_PROC_ADDR        0x80000000UL
-#define PPC7D_PCI0_MEM0_START_PCI_HI_ADDR      0x00000000UL
-#define PPC7D_PCI0_MEM0_START_PCI_LO_ADDR      0x80000000UL
-#define PPC7D_PCI0_MEM0_SIZE                   0x20000000UL
-#define PPC7D_PCI0_MEM1_START_PROC_ADDR        0xe8010000UL
-#define PPC7D_PCI0_MEM1_START_PCI_HI_ADDR      0x00000000UL
-#define PPC7D_PCI0_MEM1_START_PCI_LO_ADDR      0x00000000UL
-#define PPC7D_PCI0_MEM1_SIZE                   0x000f0000UL
-#define PPC7D_PCI0_IO_START_PROC_ADDR          0xe8000000UL
-#define PPC7D_PCI0_IO_START_PCI_ADDR           0x00000000UL
-#define PPC7D_PCI0_IO_SIZE                     0x00010000UL
-
-#define PPC7D_PCI1_MEM0_START_PROC_ADDR        0xa0000000UL
-#define PPC7D_PCI1_MEM0_START_PCI_HI_ADDR      0x00000000UL
-#define PPC7D_PCI1_MEM0_START_PCI_LO_ADDR      0xa0000000UL
-#define PPC7D_PCI1_MEM0_SIZE                   0x20000000UL
-#define PPC7D_PCI1_MEM1_START_PROC_ADDR        0xe9800000UL
-#define PPC7D_PCI1_MEM1_START_PCI_HI_ADDR      0x00000000UL
-#define PPC7D_PCI1_MEM1_START_PCI_LO_ADDR      0x00000000UL
-#define PPC7D_PCI1_MEM1_SIZE                   0x00800000UL
-#define PPC7D_PCI1_IO_START_PROC_ADDR          0xe9000000UL
-#define PPC7D_PCI1_IO_START_PCI_ADDR           0x00000000UL
-#define PPC7D_PCI1_IO_SIZE                     0x00010000UL
-
-#define	PPC7D_DEFAULT_BAUD			9600
-#define	PPC7D_MPSC_CLK_SRC			8	  /* TCLK */
-#define	PPC7D_MPSC_CLK_FREQ			133333333 /* 133.3333... MHz */
-
-#define	PPC7D_ETH0_PHY_ADDR			8
-#define	PPC7D_ETH1_PHY_ADDR			9
-#define	PPC7D_ETH2_PHY_ADDR			0
-
-#define PPC7D_ETH_TX_QUEUE_SIZE			400
-#define PPC7D_ETH_RX_QUEUE_SIZE			400
-
-#define	PPC7D_ETH_PORT_CONFIG_VALUE			\
-	MV64340_ETH_UNICAST_NORMAL_MODE			|	\
-	MV64340_ETH_DEFAULT_RX_QUEUE_0			|	\
-	MV64340_ETH_DEFAULT_RX_ARP_QUEUE_0		|	\
-	MV64340_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP		|	\
-	MV64340_ETH_RECEIVE_BC_IF_IP			|	\
-	MV64340_ETH_RECEIVE_BC_IF_ARP			|	\
-	MV64340_ETH_CAPTURE_TCP_FRAMES_DIS		|	\
-	MV64340_ETH_CAPTURE_UDP_FRAMES_DIS		|	\
-	MV64340_ETH_DEFAULT_RX_TCP_QUEUE_0		|	\
-	MV64340_ETH_DEFAULT_RX_UDP_QUEUE_0		|	\
-	MV64340_ETH_DEFAULT_RX_BPDU_QUEUE_0
-
-#define	PPC7D_ETH_PORT_CONFIG_EXTEND_VALUE		\
-	MV64340_ETH_SPAN_BPDU_PACKETS_AS_NORMAL		|	\
-	MV64340_ETH_PARTITION_DISABLE
-
-#define	GT_ETH_IPG_INT_RX(value)			\
-	((value & 0x3fff) << 8)
-
-#define	PPC7D_ETH_PORT_SDMA_CONFIG_VALUE		\
-	MV64340_ETH_RX_BURST_SIZE_4_64BIT		|	\
-	GT_ETH_IPG_INT_RX(0)			|	\
-	MV64340_ETH_TX_BURST_SIZE_4_64BIT
-
-#define	PPC7D_ETH_PORT_SERIAL_CONTROL_VALUE		\
-	MV64340_ETH_ENABLE_AUTO_NEG_FOR_DUPLX		|	\
-	MV64340_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL	|	\
-	MV64340_ETH_ADV_SYMMETRIC_FLOW_CTRL		|	\
-	MV64340_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX	|	\
-	MV64340_ETH_FORCE_BP_MODE_NO_JAM		|	\
-	(1 << 9)					|	\
-	MV64340_ETH_DO_NOT_FORCE_LINK_FAIL		|	\
-	MV64340_ETH_RETRANSMIT_16_ATTEMPTS		|	\
-	MV64340_ETH_ENABLE_AUTO_NEG_SPEED_GMII		|	\
-	MV64340_ETH_DTE_ADV_0				|	\
-	MV64340_ETH_DISABLE_AUTO_NEG_BYPASS		|	\
-	MV64340_ETH_AUTO_NEG_NO_CHANGE			|	\
-	MV64340_ETH_MAX_RX_PACKET_9700BYTE		|	\
-	MV64340_ETH_CLR_EXT_LOOPBACK			|	\
-	MV64340_ETH_SET_FULL_DUPLEX_MODE		|	\
-	MV64340_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
-
-/*****************************************************************************
- * Serial defines.
- *****************************************************************************/
-
-#define PPC7D_SERIAL_0		0xe80003f8
-#define PPC7D_SERIAL_1		0xe80002f8
-
-#define RS_TABLE_SIZE  2
-
-/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
-#define UART_CLK			1843200
-#define BASE_BAUD			( UART_CLK / 16 )
-
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF)
-#endif
-
-#define STD_SERIAL_PORT_DFNS \
-        { 0, BASE_BAUD, PPC7D_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
-		iomem_base: (u8 *)PPC7D_SERIAL_0,			  \
-		io_type: SERIAL_IO_MEM, },				  \
-        { 0, BASE_BAUD, PPC7D_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
-		iomem_base: (u8 *)PPC7D_SERIAL_1,			  \
-		io_type: SERIAL_IO_MEM },
-
-#define SERIAL_PORT_DFNS \
-        STD_SERIAL_PORT_DFNS
-
-/*****************************************************************************
- * CPLD defines.
- *
- * Register map:-
- *
- * 0000 to 000F 	South Bridge DMA 1 Control
- * 0020 and 0021 	South Bridge Interrupt 1 Control
- * 0040 to 0043 	South Bridge Counter Control
- * 0060 		Keyboard
- * 0061 		South Bridge NMI Status and Control
- * 0064 		Keyboard
- * 0071 and 0072 	RTC R/W
- * 0078 to 007B 	South Bridge BIOS Timer
- * 0080 to 0090 	South Bridge DMA Pages
- * 00A0 and 00A1 	South Bridge Interrupt 2 Control
- * 00C0 to 00DE 	South Bridge DMA 2 Control
- * 02E8 to 02EF 	COM6 R/W
- * 02F8 to 02FF 	South Bridge COM2 R/W
- * 03E8 to 03EF 	COM5 R/W
- * 03F8 to 03FF 	South Bridge COM1 R/W
- * 040A 		South Bridge DMA Scatter/Gather RO
- * 040B 		DMA 1 Extended Mode WO
- * 0410 to 043F 	South Bridge DMA Scatter/Gather
- * 0481 to 048B 	South Bridge DMA High Pages
- * 04D0 and 04D1 	South Bridge Edge/Level Control
- * 04D6 		DMA 2 Extended Mode WO
- * 0804 		Memory Configuration RO
- * 0806 		Memory Configuration Extend RO
- * 0808 		SCSI Activity LED R/W
- * 080C 		Equipment Present 1 RO
- * 080E 		Equipment Present 2 RO
- * 0810 		Equipment Present 3 RO
- * 0812 		Equipment Present 4 RO
- * 0818 		Key Lock RO
- * 0820 		LEDS R/W
- * 0824 		COMs R/W
- * 0826 		RTS R/W
- * 0828 		Reset R/W
- * 082C 		Watchdog Trig R/W
- * 082E 		Interrupt R/W
- * 0830 		Interrupt Status RO
- * 0832 		PCI configuration RO
- * 0854 		Board Revision RO
- * 0858 		Extended ID RO
- * 0864 		ID Link RO
- * 0866 		Motherboard Type RO
- * 0868 		FLASH Write control RO
- * 086A 		Software FLASH write protect R/W
- * 086E 		FLASH Control R/W
- *****************************************************************************/
-
-#define PPC7D_CPLD_MEM_CONFIG			0x0804
-#define PPC7D_CPLD_MEM_CONFIG_EXTEND		0x0806
-#define PPC7D_CPLD_SCSI_ACTIVITY_LED		0x0808
-#define PPC7D_CPLD_EQUIPMENT_PRESENT_1		0x080C
-#define PPC7D_CPLD_EQUIPMENT_PRESENT_2		0x080E
-#define PPC7D_CPLD_EQUIPMENT_PRESENT_3		0x0810
-#define PPC7D_CPLD_EQUIPMENT_PRESENT_4		0x0812
-#define PPC7D_CPLD_KEY_LOCK			0x0818
-#define PPC7D_CPLD_LEDS				0x0820
-#define PPC7D_CPLD_COMS				0x0824
-#define PPC7D_CPLD_RTS				0x0826
-#define PPC7D_CPLD_RESET			0x0828
-#define PPC7D_CPLD_WATCHDOG_TRIG		0x082C
-#define PPC7D_CPLD_INTR				0x082E
-#define PPC7D_CPLD_INTR_STATUS			0x0830
-#define PPC7D_CPLD_PCI_CONFIG			0x0832
-#define PPC7D_CPLD_BOARD_REVISION		0x0854
-#define PPC7D_CPLD_EXTENDED_ID			0x0858
-#define PPC7D_CPLD_ID_LINK			0x0864
-#define PPC7D_CPLD_MOTHERBOARD_TYPE		0x0866
-#define PPC7D_CPLD_FLASH_WRITE_CNTL		0x0868
-#define PPC7D_CPLD_SW_FLASH_WRITE_PROTECT	0x086A
-#define PPC7D_CPLD_FLASH_CNTL			0x086E
-
-/* MEMORY_CONFIG_EXTEND */
-#define PPC7D_CPLD_SDRAM_BANK_NUM_MASK		0x02
-#define PPC7D_CPLD_SDRAM_BANK_SIZE_MASK		0xc0
-#define PPC7D_CPLD_SDRAM_BANK_SIZE_128M		0
-#define PPC7D_CPLD_SDRAM_BANK_SIZE_256M		0x40
-#define PPC7D_CPLD_SDRAM_BANK_SIZE_512M		0x80
-#define PPC7D_CPLD_SDRAM_BANK_SIZE_1G		0xc0
-#define PPC7D_CPLD_FLASH_DEV_SIZE_MASK		0x03
-#define PPC7D_CPLD_FLASH_BANK_NUM_MASK		0x0c
-#define PPC7D_CPLD_FLASH_DEV_SIZE_64M		0
-#define PPC7D_CPLD_FLASH_DEV_SIZE_32M		1
-#define PPC7D_CPLD_FLASH_DEV_SIZE_16M		3
-#define PPC7D_CPLD_FLASH_BANK_NUM_4		0x00
-#define PPC7D_CPLD_FLASH_BANK_NUM_3		0x04
-#define PPC7D_CPLD_FLASH_BANK_NUM_2		0x08
-#define PPC7D_CPLD_FLASH_BANK_NUM_1		0x0c
-
-/* SCSI_LED */
-#define PPC7D_CPLD_SCSI_ACTIVITY_LED_OFF	0
-#define PPC7D_CPLD_SCSI_ACTIVITY_LED_ON		1
-
-/* EQUIPMENT_PRESENT_1 */
-#define PPC7D_CPLD_EQPT_PRES_1_FITTED		0
-#define PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK	(0x80 >> 2)
-#define PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK	(0x80 >> 3)
-#define PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK	(0x80 >> 4)
-
-/* EQUIPMENT_PRESENT_2 */
-#define PPC7D_CPLD_EQPT_PRES_2_FITTED		!0
-#define PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK	(0x80 >> 0)
-#define PPC7D_CPLD_EQPT_PRES_2_COM36_MASK	(0x80 >> 2)
-#define PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK	(0x80 >> 3)
-#define PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK	(0x80 >> 4)
-
-/* EQUIPMENT_PRESENT_3 */
-#define PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK	(0x80 >> 3)
-#define PPC7D_CPLD_EQPT_PRES_3_PMC2_5V		(0 >> 3)
-#define PPC7D_CPLD_EQPT_PRES_3_PMC2_3V		(0x80 >> 3)
-#define PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK	(0x80 >> 4)
-#define PPC7D_CPLD_EQPT_PRES_3_PMC1_5V		(0 >> 4)
-#define PPC7D_CPLD_EQPT_PRES_3_PMC1_3V		(0x80 >> 4)
-#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK	(0x80 >> 5)
-#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_INTER	(0 >> 5)
-#define PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_VME	(0x80 >> 5)
-
-/* EQUIPMENT_PRESENT_4 */
-#define PPC7D_CPLD_EQPT_PRES_4_LPT_MASK		(0x80 >> 2)
-#define PPC7D_CPLD_EQPT_PRES_4_LPT_FITTED	(0x80 >> 2)
-#define PPC7D_CPLD_EQPT_PRES_4_PS2_USB2_MASK	(0xc0 >> 6)
-#define PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED	(0x40 >> 6)
-#define PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED	(0x80 >> 6)
-
-/* CPLD_LEDS */
-#define PPC7D_CPLD_LEDS_ON			(!0)
-#define PPC7D_CPLD_LEDS_OFF			(0)
-#define PPC7D_CPLD_LEDS_NVRAM_PAGE_MASK		(0xc0 >> 2)
-#define PPC7D_CPLD_LEDS_DS201_MASK		(0x80 >> 4)
-#define PPC7D_CPLD_LEDS_DS219_MASK		(0x80 >> 5)
-#define PPC7D_CPLD_LEDS_DS220_MASK		(0x80 >> 6)
-#define PPC7D_CPLD_LEDS_DS221_MASK		(0x80 >> 7)
-
-/* CPLD_COMS */
-#define PPC7D_CPLD_COMS_COM3_TCLKEN		(0x80 >> 0)
-#define PPC7D_CPLD_COMS_COM3_RTCLKEN		(0x80 >> 1)
-#define PPC7D_CPLD_COMS_COM3_MODE_MASK		(0x80 >> 2)
-#define PPC7D_CPLD_COMS_COM3_MODE_RS232		(0)
-#define PPC7D_CPLD_COMS_COM3_MODE_RS422		(0x80 >> 2)
-#define PPC7D_CPLD_COMS_COM3_TXEN		(0x80 >> 3)
-#define PPC7D_CPLD_COMS_COM4_TCLKEN		(0x80 >> 4)
-#define PPC7D_CPLD_COMS_COM4_RTCLKEN		(0x80 >> 5)
-#define PPC7D_CPLD_COMS_COM4_MODE_MASK		(0x80 >> 6)
-#define PPC7D_CPLD_COMS_COM4_MODE_RS232		(0)
-#define PPC7D_CPLD_COMS_COM4_MODE_RS422		(0x80 >> 6)
-#define PPC7D_CPLD_COMS_COM4_TXEN		(0x80 >> 7)
-
-/* CPLD_RTS */
-#define PPC7D_CPLD_RTS_COM36_LOOPBACK		(0x80 >> 0)
-#define PPC7D_CPLD_RTS_COM4_SCLK		(0x80 >> 1)
-#define PPC7D_CPLD_RTS_COM3_TXFUNC_MASK		(0xc0 >> 2)
-#define PPC7D_CPLD_RTS_COM3_TXFUNC_DISABLED	(0 >> 2)
-#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED	(0x80 >> 2)
-#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3	(0xc0 >> 2)
-#define PPC7D_CPLD_RTS_COM3_TXFUNC_ENABLED_RTG3S (0xc0 >> 2)
-#define PPC7D_CPLD_RTS_COM56_MODE_MASK		(0x80 >> 4)
-#define PPC7D_CPLD_RTS_COM56_MODE_RS232		(0)
-#define PPC7D_CPLD_RTS_COM56_MODE_RS422		(0x80 >> 4)
-#define PPC7D_CPLD_RTS_COM56_ENABLE_MASK	(0x80 >> 5)
-#define PPC7D_CPLD_RTS_COM56_DISABLED		(0)
-#define PPC7D_CPLD_RTS_COM56_ENABLED		(0x80 >> 5)
-#define PPC7D_CPLD_RTS_COM4_TXFUNC_MASK		(0xc0 >> 6)
-#define PPC7D_CPLD_RTS_COM4_TXFUNC_DISABLED	(0 >> 6)
-#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED	(0x80 >> 6)
-#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3	(0x40 >> 6)
-#define PPC7D_CPLD_RTS_COM4_TXFUNC_ENABLED_RTG3S (0x40 >> 6)
-
-/* WATCHDOG_TRIG */
-#define PPC7D_CPLD_WDOG_CAUSE_MASK		(0x80 >> 0)
-#define PPC7D_CPLD_WDOG_CAUSE_NORMAL_RESET	(0 >> 0)
-#define PPC7D_CPLD_WDOG_CAUSE_WATCHDOG		(0x80 >> 0)
-#define PPC7D_CPLD_WDOG_ENABLE_MASK		(0x80 >> 6)
-#define PPC7D_CPLD_WDOG_ENABLE_OFF		(0 >> 6)
-#define PPC7D_CPLD_WDOG_ENABLE_ON		(0x80 >> 6)
-#define PPC7D_CPLD_WDOG_RESETSW_MASK		(0x80 >> 7)
-#define PPC7D_CPLD_WDOG_RESETSW_OFF		(0 >> 7)
-#define PPC7D_CPLD_WDOG_RESETSW_ON		(0x80 >> 7)
-
-/* Interrupt mask and status bits */
-#define PPC7D_CPLD_INTR_TEMP_MASK		(0x80 >> 0)
-#define PPC7D_CPLD_INTR_HB8_MASK		(0x80 >> 1)
-#define PPC7D_CPLD_INTR_PHY1_MASK		(0x80 >> 2)
-#define PPC7D_CPLD_INTR_PHY0_MASK		(0x80 >> 3)
-#define PPC7D_CPLD_INTR_ISANMI_MASK		(0x80 >> 5)
-#define PPC7D_CPLD_INTR_CRITTEMP_MASK		(0x80 >> 6)
-
-/* CPLD_INTR */
-#define PPC7D_CPLD_INTR_ENABLE_OFF		(0)
-#define PPC7D_CPLD_INTR_ENABLE_ON		(!0)
-
-/* CPLD_INTR_STATUS */
-#define PPC7D_CPLD_INTR_STATUS_OFF		(0)
-#define PPC7D_CPLD_INTR_STATUS_ON		(!0)
-
-/* CPLD_PCI_CONFIG */
-#define PPC7D_CPLD_PCI_CONFIG_PCI0_MASK		0x70
-#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI33	0x00
-#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCI66	0x10
-#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX33	0x40
-#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX66	0x50
-#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX100      0x60
-#define PPC7D_CPLD_PCI_CONFIG_PCI0_PCIX133	0x70
-#define PPC7D_CPLD_PCI_CONFIG_PCI1_MASK		0x07
-#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI33	0x00
-#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCI66	0x01
-#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX33	0x04
-#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX66	0x05
-#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX100	0x06
-#define PPC7D_CPLD_PCI_CONFIG_PCI1_PCIX133	0x07
-
-/* CPLD_BOARD_REVISION */
-#define PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK	0xe0
-#define PPC7D_CPLD_BOARD_REVISION_LETTER_MASK	0x1f
-
-/* CPLD_EXTENDED_ID */
-#define PPC7D_CPLD_EXTENDED_ID_PPC7D		0x18
-
-/* CPLD_ID_LINK */
-#define PPC7D_CPLD_ID_LINK_VME64_GAP_MASK	(0x80 >> 2)
-#define PPC7D_CPLD_ID_LINK_VME64_GA4_MASK	(0x80 >> 3)
-#define PPC7D_CPLD_ID_LINK_E13_MASK		(0x80 >> 4)
-#define PPC7D_CPLD_ID_LINK_E12_MASK		(0x80 >> 5)
-#define PPC7D_CPLD_ID_LINK_E7_MASK		(0x80 >> 6)
-#define PPC7D_CPLD_ID_LINK_E6_MASK		(0x80 >> 7)
-
-/* CPLD_MOTHERBOARD_TYPE */
-#define PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK	(0x80 >> 0)
-#define PPC7D_CPLD_MB_TYPE_ECC_ENABLED		(0x80 >> 0)
-#define PPC7D_CPLD_MB_TYPE_ECC_DISABLED		(0 >> 0)
-#define PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK	(0x80 >> 3)
-#define PPC7D_CPLD_MB_TYPE_PLL_MASK		0x0c
-#define PPC7D_CPLD_MB_TYPE_PLL_133		0x00
-#define PPC7D_CPLD_MB_TYPE_PLL_100		0x08
-#define PPC7D_CPLD_MB_TYPE_PLL_64		0x04
-#define PPC7D_CPLD_MB_TYPE_HW_ID_MASK		0x03
-
-/* CPLD_FLASH_WRITE_CNTL */
-#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK	(0x80 >> 0)
-#define PPD7D_CPLD_FLASH_CNTL_WR_LINK_FITTED	(0x80 >> 0)
-#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK	(0x80 >> 2)
-#define PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_FITTED	(0x80 >> 2)
-#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK	(0x80 >> 3)
-#define PPD7D_CPLD_FLASH_CNTL_USER_LINK_FITTED	(0x80 >> 3)
-#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK	(0x80 >> 5)
-#define PPD7D_CPLD_FLASH_CNTL_RECO_WR_ENABLED	(0x80 >> 5)
-#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK	(0x80 >> 6)
-#define PPD7D_CPLD_FLASH_CNTL_BOOT_WR_ENABLED	(0x80 >> 6)
-#define PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK	(0x80 >> 7)
-#define PPD7D_CPLD_FLASH_CNTL_USER_WR_ENABLED	(0x80 >> 7)
-
-/* CPLD_SW_FLASH_WRITE_PROTECT */
-#define PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED	(!0)
-#define PPC7D_CPLD_SW_FLASH_WRPROT_DISABLED	(0)
-#define PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK	(0x80 >> 6)
-#define PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK	(0x80 >> 7)
-
-/* CPLD_FLASH_WRITE_CNTL */
-#define PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK	(0x80 >> 0)
-#define PPC7D_CPLD_FLASH_CNTL_NVRAM_DISABLED	(0 >> 0)
-#define PPC7D_CPLD_FLASH_CNTL_NVRAM_ENABLED	(0x80 >> 0)
-#define PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK	(0x80 >> 1)
-#define PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK	(0x80 >> 2)
-#define PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK	(0x80 >> 3)
-
-
-#endif /* __PPC_PLATFORMS_PPC7D_H */
diff --git a/arch/ppc/platforms/residual.c b/arch/ppc/platforms/residual.c
deleted file mode 100644
index d687b0f8763..00000000000
--- a/arch/ppc/platforms/residual.c
+++ /dev/null
@@ -1,1034 +0,0 @@
-/*
- * Code to deal with the PReP residual data.
- *
- * Written by: Cort Dougan (cort@cs.nmt.edu)
- * Improved _greatly_ and rewritten by Gabriel Paubert (paubert@iram.es)
- *
- *  This file is based on the following documentation:
- *
- *	IBM Power Personal Systems Architecture
- *	Residual Data
- * 	Document Number: PPS-AR-FW0001
- *
- *  This file is subject to the terms and conditions of the GNU General Public
- *  License.  See the file COPYING in the main directory of this archive
- *  for more details.
- *
- */
-
-#include <linux/string.h>
-#include <asm/residual.h>
-#include <asm/pnp.h>
-#include <asm/byteorder.h>
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <linux/stddef.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/slab.h>
-#include <linux/user.h>
-#include <linux/a.out.h>
-#include <linux/tty.h>
-#include <linux/major.h>
-#include <linux/interrupt.h>
-#include <linux/reboot.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/pci.h>
-#include <linux/proc_fs.h>
-
-#include <asm/sections.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/pgtable.h>
-#include <asm/ide.h>
-
-
-unsigned char __res[sizeof(RESIDUAL)] = {0,};
-RESIDUAL *res = (RESIDUAL *)&__res;
-
-char * PnP_BASE_TYPES[] __initdata = {
-  "Reserved",
-  "MassStorageDevice",
-  "NetworkInterfaceController",
-  "DisplayController",
-  "MultimediaController",
-  "MemoryController",
-  "BridgeController",
-  "CommunicationsDevice",
-  "SystemPeripheral",
-  "InputDevice",
-  "ServiceProcessor"
-  };
-
-/* Device Sub Type Codes */
-
-unsigned char * PnP_SUB_TYPES[] __initdata = {
-  "\001\000SCSIController",
-  "\001\001IDEController",
-  "\001\002FloppyController",
-  "\001\003IPIController",
-  "\001\200OtherMassStorageController",
-  "\002\000EthernetController",
-  "\002\001TokenRingController",
-  "\002\002FDDIController",
-  "\002\0x80OtherNetworkController",
-  "\003\000VGAController",
-  "\003\001SVGAController",
-  "\003\002XGAController",
-  "\003\200OtherDisplayController",
-  "\004\000VideoController",
-  "\004\001AudioController",
-  "\004\200OtherMultimediaController",
-  "\005\000RAM",
-  "\005\001FLASH",
-  "\005\200OtherMemoryDevice",
-  "\006\000HostProcessorBridge",
-  "\006\001ISABridge",
-  "\006\002EISABridge",
-  "\006\003MicroChannelBridge",
-  "\006\004PCIBridge",
-  "\006\005PCMCIABridge",
-  "\006\006VMEBridge",
-  "\006\200OtherBridgeDevice",
-  "\007\000RS232Device",
-  "\007\001ATCompatibleParallelPort",
-  "\007\200OtherCommunicationsDevice",
-  "\010\000ProgrammableInterruptController",
-  "\010\001DMAController",
-  "\010\002SystemTimer",
-  "\010\003RealTimeClock",
-  "\010\004L2Cache",
-  "\010\005NVRAM",
-  "\010\006PowerManagement",
-  "\010\007CMOS",
-  "\010\010OperatorPanel",
-  "\010\011ServiceProcessorClass1",
-  "\010\012ServiceProcessorClass2",
-  "\010\013ServiceProcessorClass3",
-  "\010\014GraphicAssist",
-  "\010\017SystemPlanar",
-  "\010\200OtherSystemPeripheral",
-  "\011\000KeyboardController",
-  "\011\001Digitizer",
-  "\011\002MouseController",
-  "\011\003TabletController",
-  "\011\0x80OtherInputController",
-  "\012\000GeneralMemoryController",
-  NULL
-};
-
-/* Device Interface Type Codes */
-
-unsigned char * PnP_INTERFACES[] __initdata = {
-  "\000\000\000General",
-  "\001\000\000GeneralSCSI",
-  "\001\001\000GeneralIDE",
-  "\001\001\001ATACompatible",
-
-  "\001\002\000GeneralFloppy",
-  "\001\002\001Compatible765",
-  "\001\002\002NS398_Floppy",         /* NS Super I/O wired to use index
-                                         register at port 398 and data
-                                         register at port 399               */
-  "\001\002\003NS26E_Floppy",         /* Ports 26E and 26F                  */
-  "\001\002\004NS15C_Floppy",         /* Ports 15C and 15D                  */
-  "\001\002\005NS2E_Floppy",          /* Ports 2E and 2F                    */
-  "\001\002\006CHRP_Floppy",          /* CHRP Floppy in PR*P system         */
-
-  "\001\003\000GeneralIPI",
-
-  "\002\000\000GeneralEther",
-  "\002\001\000GeneralToken",
-  "\002\002\000GeneralFDDI",
-
-  "\003\000\000GeneralVGA",
-  "\003\001\000GeneralSVGA",
-  "\003\002\000GeneralXGA",
-
-  "\004\000\000GeneralVideo",
-  "\004\001\000GeneralAudio",
-  "\004\001\001CS4232Audio",            /* CS 4232 Plug 'n Play Configured    */
-
-  "\005\000\000GeneralRAM",
-  /* This one is obviously wrong ! */
-  "\005\000\000PCIMemoryController",    /* PCI Config Method                  */
-  "\005\000\001RS6KMemoryController",   /* RS6K Config Method                 */
-  "\005\001\000GeneralFLASH",
-
-  "\006\000\000GeneralHostBridge",
-  "\006\001\000GeneralISABridge",
-  "\006\002\000GeneralEISABridge",
-  "\006\003\000GeneralMCABridge",
-  /* GeneralPCIBridge = 0, */
-  "\006\004\000PCIBridgeDirect",
-  "\006\004\001PCIBridgeIndirect",
-  "\006\004\002PCIBridgeRS6K",
-  "\006\005\000GeneralPCMCIABridge",
-  "\006\006\000GeneralVMEBridge",
-
-  "\007\000\000GeneralRS232",
-  "\007\000\001COMx",
-  "\007\000\002Compatible16450",
-  "\007\000\003Compatible16550",
-  "\007\000\004NS398SerPort",         /* NS Super I/O wired to use index
-                                         register at port 398 and data
-                                         register at port 399               */
-  "\007\000\005NS26ESerPort",         /* Ports 26E and 26F                  */
-  "\007\000\006NS15CSerPort",         /* Ports 15C and 15D                  */
-  "\007\000\007NS2ESerPort",          /* Ports 2E and 2F                    */
-
-  "\007\001\000GeneralParPort",
-  "\007\001\001LPTx",
-  "\007\001\002NS398ParPort",         /* NS Super I/O wired to use index
-                                         register at port 398 and data
-                                         register at port 399               */
-  "\007\001\003NS26EParPort",         /* Ports 26E and 26F                  */
-  "\007\001\004NS15CParPort",         /* Ports 15C and 15D                  */
-  "\007\001\005NS2EParPort",          /* Ports 2E and 2F                    */
-
-  "\010\000\000GeneralPIC",
-  "\010\000\001ISA_PIC",
-  "\010\000\002EISA_PIC",
-  "\010\000\003MPIC",
-  "\010\000\004RS6K_PIC",
-
-  "\010\001\000GeneralDMA",
-  "\010\001\001ISA_DMA",
-  "\010\001\002EISA_DMA",
-
-  "\010\002\000GeneralTimer",
-  "\010\002\001ISA_Timer",
-  "\010\002\002EISA_Timer",
-  "\010\003\000GeneralRTC",
-  "\010\003\001ISA_RTC",
-
-  "\010\004\001StoreThruOnly",
-  "\010\004\002StoreInEnabled",
-  "\010\004\003RS6KL2Cache",
-
-  "\010\005\000IndirectNVRAM",        /* Indirectly addressed               */
-  "\010\005\001DirectNVRAM",          /* Memory Mapped                      */
-  "\010\005\002IndirectNVRAM24",      /* Indirectly addressed - 24 bit      */
-
-  "\010\006\000GeneralPowerManagement",
-  "\010\006\001EPOWPowerManagement",
-  "\010\006\002PowerControl",         // d1378
-
-  "\010\007\000GeneralCMOS",
-
-  "\010\010\000GeneralOPPanel",
-  "\010\010\001HarddiskLight",
-  "\010\010\002CDROMLight",
-  "\010\010\003PowerLight",
-  "\010\010\004KeyLock",
-  "\010\010\005ANDisplay",            /* AlphaNumeric Display               */
-  "\010\010\006SystemStatusLED",      /* 3 digit 7 segment LED              */
-  "\010\010\007CHRP_SystemStatusLED", /* CHRP LEDs in PR*P system           */
-
-  "\010\011\000GeneralServiceProcessor",
-  "\010\012\000GeneralServiceProcessor",
-  "\010\013\000GeneralServiceProcessor",
-
-  "\010\014\001TransferData",
-  "\010\014\002IGMC32",
-  "\010\014\003IGMC64",
-
-  "\010\017\000GeneralSystemPlanar",   /* 10/5/95                            */
-  NULL
-  };
-
-static const unsigned char __init *PnP_SUB_TYPE_STR(unsigned char BaseType,
-					     unsigned char SubType) {
-	unsigned char ** s=PnP_SUB_TYPES;
-	while (*s && !((*s)[0]==BaseType
-		       && (*s)[1]==SubType)) s++;
-	if (*s) return *s+2;
-	else return("Unknown !");
-};
-
-static const unsigned char __init *PnP_INTERFACE_STR(unsigned char BaseType,
-					      unsigned char SubType,
-					      unsigned char Interface) {
-	unsigned char ** s=PnP_INTERFACES;
-	while (*s && !((*s)[0]==BaseType
-		       && (*s)[1]==SubType
-		       && (*s)[2]==Interface)) s++;
-	if (*s) return *s+3;
-	else return NULL;
-};
-
-static void __init printsmallvendor(PnP_TAG_PACKET *pkt, int size) {
-	int i, c;
-	char decomp[4];
-#define p pkt->S14_Pack.S14_Data.S14_PPCPack
-	switch(p.Type) {
-	case 1:
-	  /* Decompress first 3 chars */
-	  c = *(unsigned short *)p.PPCData;
-	  decomp[0]='A'-1+((c>>10)&0x1F);
-	  decomp[1]='A'-1+((c>>5)&0x1F);
-	  decomp[2]='A'-1+(c&0x1F);
-	  decomp[3]=0;
-	  printk("    Chip identification: %s%4.4X\n",
-		 decomp, ld_le16((unsigned short *)(p.PPCData+2)));
-	  break;
-	default:
-	  printk("    Small vendor item type 0x%2.2x, data (hex): ",
-		 p.Type);
-	  for(i=0; i<size-2; i++) printk("%2.2x ", p.PPCData[i]);
-	  printk("\n");
-	  break;
-	}
-#undef p
-}
-
-static void __init printsmallpacket(PnP_TAG_PACKET * pkt, int size) {
-	static const unsigned char * intlevel[] = {"high", "low"};
-	static const unsigned char * intsense[] = {"edge", "level"};
-
-	switch (tag_small_item_name(pkt->S1_Pack.Tag)) {
-	case PnPVersion:
-	  printk("    PnPversion 0x%x.%x\n",
-		 pkt->S1_Pack.Version[0], /* How to interpret version ? */
-		 pkt->S1_Pack.Version[1]);
-	  break;
-//	case Logicaldevice:
-	  break;
-//	case CompatibleDevice:
-	  break;
-	case IRQFormat:
-#define p pkt->S4_Pack
-	  printk("    IRQ Mask 0x%4.4x, %s %s sensitive\n",
-		 ld_le16((unsigned short *)p.IRQMask),
-		 intlevel[(size>3) ? !(p.IRQInfo&0x05) : 0],
-		 intsense[(size>3) ? !(p.IRQInfo&0x03) : 0]);
-#undef p
-	  break;
-	case DMAFormat:
-#define p pkt->S5_Pack
-	  printk("    DMA channel mask 0x%2.2x, info 0x%2.2x\n",
-		 p.DMAMask, p.DMAInfo);
-#undef p
-	  break;
-	case StartDepFunc:
-	  printk("Start dependent function:\n");
-	  break;
-	case EndDepFunc:
-	  printk("End dependent function\n");
-	  break;
-	case IOPort:
-#define p pkt->S8_Pack
-	  printk("    Variable (%d decoded bits) I/O port\n"
-		 "      from 0x%4.4x to 0x%4.4x, alignment %d, %d ports\n",
-		 p.IOInfo&ISAAddr16bit?16:10,
-		 ld_le16((unsigned short *)p.RangeMin),
- 		 ld_le16((unsigned short *)p.RangeMax),
-		 p.IOAlign, p.IONum);
-#undef p
-	  break;
-	case FixedIOPort:
-#define p pkt->S9_Pack
-	  printk("    Fixed (10 decoded bits) I/O port from %3.3x to %3.3x\n",
-		 (p.Range[1]<<8)|p.Range[0],
-		 ((p.Range[1]<<8)|p.Range[0])+p.IONum-1);
-#undef p
-	  break;
-	case Res1:
-	case Res2:
-	case Res3:
-	  printk("    Undefined packet type %d!\n",
-		 tag_small_item_name(pkt->S1_Pack.Tag));
-	  break;
-	case SmallVendorItem:
-	  printsmallvendor(pkt,size);
-	  break;
-	default:
-	  printk("    Type 0x2.2x%d, size=%d\n",
-		 pkt->S1_Pack.Tag, size);
-	  break;
-	}
-}
-
-static void __init printlargevendor(PnP_TAG_PACKET * pkt, int size) {
-	static const unsigned char * addrtype[] = {"I/O", "Memory", "System"};
-	static const unsigned char * inttype[] = {"8259", "MPIC", "RS6k BUID %d"};
-	static const unsigned char * convtype[] = {"Bus Memory", "Bus I/O", "DMA"};
-	static const unsigned char * transtype[] = {"direct", "mapped", "direct-store segment"};
-	static const unsigned char * L2type[] = {"WriteThru", "CopyBack"};
-	static const unsigned char * L2assoc[] = {"DirectMapped", "2-way set"};
-
-	int i;
-	char tmpstr[30], *t;
-#define p pkt->L4_Pack.L4_Data.L4_PPCPack
-	switch(p.Type) {
-	case 2:
-	  printk("    %d K %s %s L2 cache, %d/%d bytes line/sector size\n",
-		 ld_le32((unsigned int *)p.PPCData),
-		 L2type[p.PPCData[10]-1],
-		 L2assoc[p.PPCData[4]-1],
-		 ld_le16((unsigned short *)p.PPCData+3),
-		 ld_le16((unsigned short *)p.PPCData+4));
-	  break;
-	case 3:
-	  printk("    PCI Bridge parameters\n"
-		 "      ConfigBaseAddress %0x\n"
-		 "      ConfigBaseData %0x\n"
-		 "      Bus number %d\n",
-		 ld_le32((unsigned int *)p.PPCData),
-		 ld_le32((unsigned int *)(p.PPCData+8)),
-		 p.PPCData[16]);
-	  for(i=20; i<size-4; i+=12) {
-	  	int j, first;
-	  	if(p.PPCData[i]) printk("      PCI Slot %d", p.PPCData[i]);
-		else printk ("      Integrated PCI device");
-		for(j=0, first=1, t=tmpstr; j<4; j++) {
-			int line=ld_le16((unsigned short *)(p.PPCData+i+4)+j);
-			if(line!=0xffff){
-			        if(first) first=0; else *t++='/';
-				*t++='A'+j;
-			}
-		}
-		*t='\0';
-		printk(" DevFunc 0x%x interrupt line(s) %s routed to",
-		       p.PPCData[i+1],tmpstr);
-		sprintf(tmpstr,
-			inttype[p.PPCData[i+2]-1],
-			p.PPCData[i+3]);
-		printk(" %s line(s) ",
-		       tmpstr);
-		for(j=0, first=1, t=tmpstr; j<4; j++) {
-			int line=ld_le16((unsigned short *)(p.PPCData+i+4)+j);
-			if(line!=0xffff){
-				if(first) first=0; else *t++='/';
-				t+=sprintf(t,"%d(%c)",
-					   line&0x7fff,
-					   line&0x8000?'E':'L');
-			}
-		}
-		printk("%s\n",tmpstr);
-	  }
-	  break;
-	case 5:
-	  printk("    Bridge address translation, %s decoding:\n"
-		 "      Processor  Bus        Size       Conversion Translation\n"
-		 "      0x%8.8x 0x%8.8x 0x%8.8x %s %s\n",
-		 p.PPCData[0]&1 ? "positive" : "subtractive",
-		 ld_le32((unsigned int *)p.PPCData+1),
-		 ld_le32((unsigned int *)p.PPCData+3),
-		 ld_le32((unsigned int *)p.PPCData+5),
-		 convtype[p.PPCData[2]-1],
-		 transtype[p.PPCData[1]-1]);
-	  break;
-	case 6:
-	  printk("    Bus speed %d Hz, %d slot(s)\n",
-		 ld_le32((unsigned int *)p.PPCData),
-		 p.PPCData[4]);
-	  break;
-	case 7:
-	  printk("    SCSI buses: %d, id(s):", p.PPCData[0]);
-	  for(i=1; i<=p.PPCData[0]; i++)
-	    printk(" %d%c", p.PPCData[i], i==p.PPCData[0] ? '\n' : ',');
-	  break;
-	case 9:
-	  printk("    %s address (%d bits), at 0x%x size 0x%x bytes\n",
-		 addrtype[p.PPCData[0]-1],
-		 p.PPCData[1],
-		 ld_le32((unsigned int *)(p.PPCData+4)),
-		 ld_le32((unsigned int *)(p.PPCData+12)));
-	  break;
-	case 10:
-	  sprintf(tmpstr,
-		  inttype[p.PPCData[0]-1],
-		  p.PPCData[1]);
-
-	  printk("    ISA interrupts routed to %s\n"
-		 "      lines",
-		 tmpstr);
-	  for(i=0; i<16; i++) {
-	  	int line=ld_le16((unsigned short *)p.PPCData+i+1);
-		if (line!=0xffff) printk(" %d(IRQ%d)", line, i);
-	  }
-	  printk("\n");
-	  break;
-	default:
-	  printk("    Large vendor item type 0x%2.2x\n      Data (hex):",
-		 p.Type);
-	  for(i=0; i<size-4; i++) printk(" %2.2x", p.PPCData[i]);
-	  printk("\n");
-#undef p
-	}
-}
-
-static void __init printlargepacket(PnP_TAG_PACKET * pkt, int size) {
-	switch (tag_large_item_name(pkt->S1_Pack.Tag)) {
-	case LargeVendorItem:
-	  printlargevendor(pkt, size);
-	  break;
-	default:
-	  printk("    Type 0x2.2x%d, size=%d\n",
-		 pkt->S1_Pack.Tag, size);
-	  break;
-	}
-}
-
-static void __init printpackets(PnP_TAG_PACKET * pkt, const char * cat)
-{
-	if (pkt->S1_Pack.Tag== END_TAG) {
-		printk("  No packets describing %s resources.\n", cat);
-		return;
-	}
-	printk(  "  Packets describing %s resources:\n",cat);
-	do {
-		int size;
-		if (tag_type(pkt->S1_Pack.Tag)) {
-		  	size= 3 +
-			  pkt->L1_Pack.Count0 +
-			  pkt->L1_Pack.Count1*256;
-			printlargepacket(pkt, size);
-		} else {
-			size=tag_small_count(pkt->S1_Pack.Tag)+1;
-			printsmallpacket(pkt, size);
-		}
-		pkt = (PnP_TAG_PACKET *)((unsigned char *) pkt + size);
-	} while (pkt->S1_Pack.Tag != END_TAG);
-}
-
-void __init print_residual_device_info(void)
-{
-	int i;
-	PPC_DEVICE *dev;
-#define did dev->DeviceId
-
-	/* make sure we have residual data first */
-	if (!have_residual_data)
-		return;
-
-	printk("Residual: %ld devices\n", res->ActualNumDevices);
-	for ( i = 0;
-	      i < res->ActualNumDevices ;
-	      i++)
-	{
-	  	char decomp[4], sn[20];
-		const char * s;
-		dev = &res->Devices[i];
-		s = PnP_INTERFACE_STR(did.BaseType, did.SubType,
-				      did.Interface);
-		if(!s) {
-			sprintf(sn, "interface %d", did.Interface);
-			s=sn;
-		}
-		if ( did.BusId & PCIDEVICE )
-		  printk("PCI Device, Bus %d, DevFunc 0x%x:",
-			 dev->BusAccess.PCIAccess.BusNumber,
-			 dev->BusAccess.PCIAccess.DevFuncNumber);
-	       	if ( did.BusId & PNPISADEVICE ) printk("PNPISA Device:");
-		if ( did.BusId & ISADEVICE )
-		  printk("ISA Device, Slot %d, LogicalDev %d:",
-			 dev->BusAccess.ISAAccess.SlotNumber,
-			 dev->BusAccess.ISAAccess.LogicalDevNumber);
-		if ( did.BusId & EISADEVICE ) printk("EISA Device:");
-		if ( did.BusId & PROCESSORDEVICE )
-		  printk("ProcBus Device, Bus %d, BUID %d: ",
-			 dev->BusAccess.ProcBusAccess.BusNumber,
-			 dev->BusAccess.ProcBusAccess.BUID);
-		if ( did.BusId & PCMCIADEVICE ) printk("PCMCIA ");
-		if ( did.BusId & VMEDEVICE ) printk("VME ");
-		if ( did.BusId & MCADEVICE ) printk("MCA ");
-		if ( did.BusId & MXDEVICE ) printk("MX ");
-		/* Decompress first 3 chars */
-		decomp[0]='A'-1+((did.DevId>>26)&0x1F);
-		decomp[1]='A'-1+((did.DevId>>21)&0x1F);
-		decomp[2]='A'-1+((did.DevId>>16)&0x1F);
-		decomp[3]=0;
-		printk(" %s%4.4lX, %s, %s, %s\n",
-		       decomp, did.DevId&0xffff,
-		       PnP_BASE_TYPES[did.BaseType],
-		       PnP_SUB_TYPE_STR(did.BaseType,did.SubType),
-		       s);
-		if ( dev->AllocatedOffset )
-			printpackets( (union _PnP_TAG_PACKET *)
-				      &res->DevicePnPHeap[dev->AllocatedOffset],
-				      "allocated");
-		if ( dev->PossibleOffset )
-			printpackets( (union _PnP_TAG_PACKET *)
-				      &res->DevicePnPHeap[dev->PossibleOffset],
-				      "possible");
-		if ( dev->CompatibleOffset )
-			printpackets( (union _PnP_TAG_PACKET *)
-				      &res->DevicePnPHeap[dev->CompatibleOffset],
-				      "compatible");
-	}
-}
-
-
-#if 0
-static void __init printVPD(void) {
-#define vpd res->VitalProductData
-	int ps=vpd.PageSize, i, j;
-	static const char* Usage[]={
-	  "FirmwareStack",  "FirmwareHeap",  "FirmwareCode", "BootImage",
-	  "Free", "Unpopulated", "ISAAddr", "PCIConfig",
-	  "IOMemory", "SystemIO", "SystemRegs", "PCIAddr",
-	  "UnPopSystemRom", "SystemROM", "ResumeBlock", "Other"
-	};
-	static const unsigned char *FWMan[]={
-	  "IBM", "Motorola", "FirmWorks", "Bull"
-	};
-	static const unsigned char *FWFlags[]={
-	  "Conventional", "OpenFirmware", "Diagnostics", "LowDebug",
-	  "MultiBoot", "LowClient", "Hex41", "FAT",
-	  "ISO9660", "SCSI_ID_Override", "Tape_Boot", "FW_Boot_Path"
-	};
-	static const unsigned char *ESM[]={
-	  "Port92", "PCIConfigA8", "FF001030", "????????"
-	};
-	static const unsigned char *SIOM[]={
-	  "Port850", "????????", "PCIConfigA8", "????????"
-	};
-
-	printk("Model: %s\n",vpd.PrintableModel);
-	printk("Serial: %s\n", vpd.Serial);
-	printk("FirmwareSupplier: %s\n", FWMan[vpd.FirmwareSupplier]);
-	printk("FirmwareFlags:");
-	for(j=0; j<12; j++) {
-	  	if (vpd.FirmwareSupports & (1<<j)) {
-			printk(" %s%c", FWFlags[j],
-			       vpd.FirmwareSupports&(-2<<j) ? ',' : '\n');
-		}
-	}
-	printk("NVRamSize: %ld\n", vpd.NvramSize);
-	printk("SIMMslots: %ld\n", vpd.NumSIMMSlots);
-	printk("EndianSwitchMethod: %s\n",
-	       ESM[vpd.EndianSwitchMethod>2 ? 2 : vpd.EndianSwitchMethod]);
-	printk("SpreadIOMethod: %s\n",
-	       SIOM[vpd.SpreadIOMethod>3 ? 3 : vpd.SpreadIOMethod]);
-	printk("Processor/Bus frequencies (Hz): %ld/%ld\n",
-	       vpd.ProcessorHz, vpd.ProcessorBusHz);
-	printk("Time Base Divisor: %ld\n", vpd.TimeBaseDivisor);
-	printk("WordWidth, PageSize: %ld, %d\n", vpd.WordWidth, ps);
-	printk("Cache sector size, Lock granularity: %ld, %ld\n",
-	       vpd.CoherenceBlockSize, vpd.GranuleSize);
-	for (i=0; i<res->ActualNumMemSegs; i++) {
-		int mask=res->Segs[i].Usage, first, j;
-		printk("%8.8lx-%8.8lx ",
-		       res->Segs[i].BasePage*ps,
-		       (res->Segs[i].PageCount+res->Segs[i].BasePage)*ps-1);
-		for(j=15, first=1; j>=0; j--) {
-			if (mask&(1<<j)) {
-				if (first) first=0;
-				else printk(", ");
-				printk("%s", Usage[j]);
-			}
-		}
-		printk("\n");
-	}
-}
-
-/*
- * Spit out some info about residual data
- */
-void print_residual_device_info(void)
-{
-	int i;
-	union _PnP_TAG_PACKET *pkt;
-	PPC_DEVICE *dev;
-#define did dev->DeviceId
-
-	/* make sure we have residual data first */
-	if (!have_residual_data)
-		return;
-	printk("Residual: %ld devices\n", res->ActualNumDevices);
-	for ( i = 0;
-	      i < res->ActualNumDevices ;
-	      i++)
-	{
-		dev = &res->Devices[i];
-		/*
-		 * pci devices
-		 */
-		if ( did.BusId & PCIDEVICE )
-		{
-			printk("PCI Device:");
-			/* unknown vendor */
-			if ( !strncmp( "Unknown", pci_strvendor(did.DevId>>16), 7) )
-				printk(" id %08lx types %d/%d", did.DevId,
-				       did.BaseType, did.SubType);
-			/* known vendor */
-			else
-				printk(" %s %s",
-				       pci_strvendor(did.DevId>>16),
-				       pci_strdev(did.DevId>>16,
-						  did.DevId&0xffff)
-					);
-
-			if ( did.BusId & PNPISADEVICE )
-			{
-				printk(" pnp:");
-				/* get pnp info on the device */
-				pkt = (union _PnP_TAG_PACKET *)
-					&res->DevicePnPHeap[dev->AllocatedOffset];
-				for (; pkt->S1_Pack.Tag != DF_END_TAG;
-				     pkt++ )
-				{
-					if ( (pkt->S1_Pack.Tag == S4_Packet) ||
-					     (pkt->S1_Pack.Tag == S4_Packet_flags) )
-						printk(" irq %02x%02x",
-						       pkt->S4_Pack.IRQMask[0],
-						       pkt->S4_Pack.IRQMask[1]);
-				}
-			}
-			printk("\n");
-			continue;
-		}
-		/*
-		 * isa devices
-		 */
-		if ( did.BusId & ISADEVICE )
-		{
-			printk("ISA Device: basetype: %d subtype: %d",
-			       did.BaseType, did.SubType);
-			printk("\n");
-			continue;
-		}
-		/*
-		 * eisa devices
-		 */
-		if ( did.BusId & EISADEVICE )
-		{
-			printk("EISA Device: basetype: %d subtype: %d",
-			       did.BaseType, did.SubType);
-			printk("\n");
-			continue;
-		}
-		/*
-		 * proc bus devices
-		 */
-		if ( did.BusId & PROCESSORDEVICE )
-		{
-			printk("ProcBus Device: basetype: %d subtype: %d",
-			       did.BaseType, did.SubType);
-			printk("\n");
-			continue;
-		}
-		/*
-		 * pcmcia devices
-		 */
-		if ( did.BusId & PCMCIADEVICE )
-		{
-			printk("PCMCIA Device: basetype: %d subtype: %d",
-			       did.BaseType, did.SubType);
-			printk("\n");
-			continue;
-		}
-		printk("Unknown bus access device: busid %lx\n",
-		       did.BusId);
-	}
-}
-#endif
-
-/* Returns the device index in the residual data,
-   any of the search items may be set as -1 for wildcard,
-   DevID number field (second halfword) is big endian !
-
-   Examples:
-   - search for the Interrupt controller (8259 type), 2 methods:
-     1) i8259 = residual_find_device(~0,
-                                     NULL,
-				     SystemPeripheral,
-				     ProgrammableInterruptController,
-				     ISA_PIC,
-				     0);
-     2) i8259 = residual_find_device(~0, "PNP0000", -1, -1, -1, 0)
-
-   - search for the first two serial devices, whatever their type)
-     iserial1 = residual_find_device(~0,NULL,
-                                     CommunicationsDevice,
-				     RS232Device,
-				     -1, 0)
-     iserial2 = residual_find_device(~0,NULL,
-                                     CommunicationsDevice,
-				     RS232Device,
-				     -1, 1)
-   - but search for typical COM1 and COM2 is not easy due to the
-     fact that the interface may be anything and the name "PNP0500" or
-     "PNP0501". Quite bad.
-
-*/
-
-/* devid are easier to uncompress than to compress, so to minimize bloat
-in this rarely used area we unencode and compare */
-
-/* in residual data number is big endian in the device table and
-little endian in the heap, so we use two parameters to avoid writing
-two very similar functions */
-
-static int __init same_DevID(unsigned short vendor,
-	       unsigned short Number,
-	       char * str)
-{
-	static unsigned const char hexdigit[]="0123456789ABCDEF";
-	if (strlen(str)!=7) return 0;
-	if ( ( ((vendor>>10)&0x1f)+'A'-1 == str[0])  &&
-	     ( ((vendor>>5)&0x1f)+'A'-1 == str[1])   &&
-	     ( (vendor&0x1f)+'A'-1 == str[2])        &&
-	     (hexdigit[(Number>>12)&0x0f] == str[3]) &&
-	     (hexdigit[(Number>>8)&0x0f] == str[4])  &&
-	     (hexdigit[(Number>>4)&0x0f] == str[5])  &&
-	     (hexdigit[Number&0x0f] == str[6]) ) return 1;
-	return 0;
-}
-
-PPC_DEVICE __init *residual_find_device(unsigned long BusMask,
-			 unsigned char * DevID,
-			 int BaseType,
-			 int SubType,
-			 int Interface,
-			 int n)
-{
-	int i;
-	if (!have_residual_data) return NULL;
-	for (i=0; i<res->ActualNumDevices; i++) {
-#define Dev res->Devices[i].DeviceId
-		if ( (Dev.BusId&BusMask)                                  &&
-		     (BaseType==-1 || Dev.BaseType==BaseType)             &&
-		     (SubType==-1 || Dev.SubType==SubType)                &&
-		     (Interface==-1 || Dev.Interface==Interface)          &&
-		     (DevID==NULL || same_DevID((Dev.DevId>>16)&0xffff,
-						Dev.DevId&0xffff, DevID)) &&
-		     !(n--) ) return res->Devices+i;
-#undef Dev
-	}
-	return NULL;
-}
-
-PPC_DEVICE __init *residual_find_device_id(unsigned long BusMask,
-			 unsigned short DevID,
-			 int BaseType,
-			 int SubType,
-			 int Interface,
-			 int n)
-{
-	int i;
-	if (!have_residual_data) return NULL;
-	for (i=0; i<res->ActualNumDevices; i++) {
-#define Dev res->Devices[i].DeviceId
-		if ( (Dev.BusId&BusMask)                                  &&
-		     (BaseType==-1 || Dev.BaseType==BaseType)             &&
-		     (SubType==-1 || Dev.SubType==SubType)                &&
-		     (Interface==-1 || Dev.Interface==Interface)          &&
-		     (DevID==0xffff || (Dev.DevId&0xffff) == DevID)	  &&
-		     !(n--) ) return res->Devices+i;
-#undef Dev
-	}
-	return NULL;
-}
-
-static int __init
-residual_scan_pcibridge(PnP_TAG_PACKET * pkt, struct pci_dev *dev)
-{
-	int irq = -1;
-
-#define data pkt->L4_Pack.L4_Data.L4_PPCPack.PPCData
-	if (dev->bus->number == data[16]) {
-		int i, size;
-
-		size = 3 + ld_le16((u_short *) (&pkt->L4_Pack.Count0));
-		for (i = 20; i < size - 4; i += 12) {
-			unsigned char pin;
-			int line_irq;
-
-			if (dev->devfn != data[i + 1])
-				continue;
-
-			pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
-			if (pin) {
-				line_irq = ld_le16((unsigned short *)
-						(&data[i + 4 + 2 * (pin - 1)]));
-				irq = (line_irq == 0xffff) ? 0
-							   : line_irq & 0x7fff;
-			} else
-				irq = 0;
-
-			break;
-		}
-	}
-#undef data
-
-	return irq;
-}
-
-int __init
-residual_pcidev_irq(struct pci_dev *dev)
-{
-	int i = 0;
-	int irq = -1;
-	PPC_DEVICE *bridge;
-
-	while ((bridge = residual_find_device
-	       (-1, NULL, BridgeController, PCIBridge, -1, i++))) {
-
-		PnP_TAG_PACKET *pkt;
-		if (bridge->AllocatedOffset) {
-			pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap +
-					   bridge->AllocatedOffset, 3, 0);
-			if (!pkt)
-				continue;
-
-			irq = residual_scan_pcibridge(pkt, dev);
-			if (irq != -1)
-				break;
-		}
-	}
-
-	return (irq < 0) ? 0 : irq;
-}
-
-void __init residual_irq_mask(char *irq_edge_mask_lo, char *irq_edge_mask_hi)
-{
-	PPC_DEVICE *dev;
-	int i = 0;
-	unsigned short irq_mask = 0x000; /* default to edge */
-
-	while ((dev = residual_find_device(-1, NULL, -1, -1, -1, i++))) {
-		PnP_TAG_PACKET *pkt;
-		unsigned short mask;
-		int size;
-		int offset = dev->AllocatedOffset;
-
-		if (!offset)
-			continue;
-
-		pkt = PnP_find_packet(res->DevicePnPHeap + offset,
-					      IRQFormat, 0);
-		if (!pkt)
-			continue;
-
-		size = tag_small_count(pkt->S1_Pack.Tag) + 1;
-		mask = ld_le16((unsigned short *)pkt->S4_Pack.IRQMask);
-		if (size > 3 && (pkt->S4_Pack.IRQInfo & 0x0c))
-			irq_mask |= mask;
-	}
-
-	*irq_edge_mask_lo = irq_mask & 0xff;
-	*irq_edge_mask_hi = irq_mask >> 8;
-}
-
-unsigned int __init residual_isapic_addr(void)
-{
-	PPC_DEVICE *isapic;
-	PnP_TAG_PACKET *pkt;
-	unsigned int addr;
-
-	isapic = residual_find_device(~0, NULL, SystemPeripheral,
-				      ProgrammableInterruptController,
-				      ISA_PIC, 0);
-	if (!isapic)
-		goto unknown;
-
-	pkt = PnP_find_large_vendor_packet(res->DevicePnPHeap +
-						isapic->AllocatedOffset, 9, 0);
-	if (!pkt)
-		goto unknown;
-
-#define p pkt->L4_Pack.L4_Data.L4_PPCPack
-	/* Must be 32-bit system address */
-	if (!((p.PPCData[0] == 3) && (p.PPCData[1] == 32)))
-		goto unknown;
-
-	/* It doesn't seem to work where length != 1 (what can I say? :-/ ) */
-	if (ld_le32((unsigned int *)(p.PPCData + 12)) != 1)
-		goto unknown;
-
-	addr = ld_le32((unsigned int *) (p.PPCData + 4));
-#undef p
-	return addr;
-unknown:
-	return 0;
-}
-
-PnP_TAG_PACKET *PnP_find_packet(unsigned char *p,
-				unsigned packet_tag,
-				int n)
-{
-	unsigned mask, masked_tag, size;
-	if(!p) return NULL;
-	if (tag_type(packet_tag)) mask=0xff; else mask=0xF8;
-	masked_tag = packet_tag&mask;
-	for(; *p != END_TAG; p+=size) {
-		if ((*p & mask) == masked_tag && !(n--))
-			return (PnP_TAG_PACKET *) p;
-		if (tag_type(*p))
-			size=ld_le16((unsigned short *)(p+1))+3;
-		else
-			size=tag_small_count(*p)+1;
-	}
-	return NULL; /* not found */
-}
-
-PnP_TAG_PACKET __init *PnP_find_small_vendor_packet(unsigned char *p,
-					     unsigned packet_type,
-					     int n)
-{
-	int next=0;
-	while (p) {
-		p = (unsigned char *) PnP_find_packet(p, 0x70, next);
-		if (p && p[1]==packet_type && !(n--))
-			return (PnP_TAG_PACKET *) p;
-		next = 1;
-	};
-	return NULL; /* not found */
-}
-
-PnP_TAG_PACKET __init *PnP_find_large_vendor_packet(unsigned char *p,
-					   unsigned packet_type,
-					   int n)
-{
-	int next=0;
-	while (p) {
-		p = (unsigned char *) PnP_find_packet(p, 0x84, next);
-		if (p && p[3]==packet_type && !(n--))
-			return (PnP_TAG_PACKET *) p;
-		next = 1;
-	};
-	return NULL; /* not found */
-}
-
-#ifdef CONFIG_PROC_PREPRESIDUAL
-static int proc_prep_residual_read(char * buf, char ** start, off_t off,
-		int count, int *eof, void *data)
-{
-	int n;
-
-	n = res->ResidualLength - off;
-	if (n < 0) {
-		*eof = 1;
-		n = 0;
-	}
-	else {
-		if (n > count)
-			n = count;
-		else
-			*eof = 1;
-
-		memcpy(buf, (char *)res + off, n);
-		*start = buf;
-	}
-
-	return n;
-}
-
-int __init
-proc_prep_residual_init(void)
-{
-	if (have_residual_data)
-		create_proc_read_entry("residual", S_IRUGO, NULL,
-					proc_prep_residual_read, NULL);
-	return 0;
-}
-
-__initcall(proc_prep_residual_init);
-#endif
diff --git a/arch/ppc/platforms/rpx8260.h b/arch/ppc/platforms/rpx8260.h
deleted file mode 100644
index 843494a50ef..00000000000
--- a/arch/ppc/platforms/rpx8260.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * A collection of structures, addresses, and values associated with
- * the Embedded Planet RPX6 (or RPX Super) MPC8260 board.
- * Copied from the RPX-Classic and SBS8260 stuff.
- *
- * Copyright (c) 2001 Dan Malek <dan@embeddededge.com>
- */
-#ifdef __KERNEL__
-#ifndef __ASM_PLATFORMS_RPX8260_H__
-#define __ASM_PLATFORMS_RPX8260_H__
-
-/* A Board Information structure that is given to a program when
- * prom starts it up.
- */
-typedef struct bd_info {
-	unsigned int	bi_memstart;	/* Memory start address */
-	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
-	unsigned int	bi_nvsize;	/* NVRAM size in bytes (can be 0) */
-	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
-	unsigned int	bi_busfreq;	/* Bus Freq, in MHz */
-	unsigned int	bi_cpmfreq;	/* CPM Freq, in MHz */
-	unsigned int	bi_brgfreq;	/* BRG Freq, in MHz */
-	unsigned int	bi_vco;		/* VCO Out from PLL */
-	unsigned int	bi_baudrate;	/* Default console baud rate */
-	unsigned int	bi_immr;	/* IMMR when called from boot rom */
-	unsigned char	bi_enetaddr[6];
-} bd_t;
-
-extern bd_t m8xx_board_info;
-
-/* Memory map is configured by the PROM startup.
- * We just map a few things we need.  The CSR is actually 4 byte-wide
- * registers that can be accessed as 8-, 16-, or 32-bit values.
- */
-#define CPM_MAP_ADDR		((uint)0xf0000000)
-#define RPX_CSR_ADDR		((uint)0xfa000000)
-#define RPX_CSR_SIZE		((uint)(512 * 1024))
-#define RPX_NVRTC_ADDR		((uint)0xfa080000)
-#define RPX_NVRTC_SIZE		((uint)(512 * 1024))
-
-/* The RPX6 has 16, byte wide control/status registers.
- * Not all are used (yet).
- */
-extern volatile u_char *rpx6_csr_addr;
-
-/* Things of interest in the CSR.
-*/
-#define BCSR0_ID_MASK		((u_char)0xf0)		/* Read only */
-#define BCSR0_SWITCH_MASK	((u_char)0x0f)		/* Read only */
-#define BCSR1_XCVR_SMC1		((u_char)0x80)
-#define BCSR1_XCVR_SMC2		((u_char)0x40)
-#define BCSR2_FLASH_WENABLE	((u_char)0x20)
-#define BCSR2_NVRAM_ENABLE	((u_char)0x10)
-#define BCSR2_ALT_IRQ2		((u_char)0x08)
-#define BCSR2_ALT_IRQ3		((u_char)0x04)
-#define BCSR2_PRST		((u_char)0x02)		/* Force reset */
-#define BCSR2_ENPRST		((u_char)0x01)		/* Enable POR */
-#define BCSR3_MODCLK_MASK	((u_char)0xe0)
-#define BCSR3_ENCLKHDR		((u_char)0x10)
-#define BCSR3_LED5		((u_char)0x04)		/* 0 == on */
-#define BCSR3_LED6		((u_char)0x02)		/* 0 == on */
-#define BCSR3_LED7		((u_char)0x01)		/* 0 == on */
-#define BCSR4_EN_PHY		((u_char)0x80)		/* Enable PHY */
-#define BCSR4_EN_MII		((u_char)0x40)		/* Enable PHY */
-#define BCSR4_MII_READ		((u_char)0x04)
-#define BCSR4_MII_MDC		((u_char)0x02)
-#define BCSR4_MII_MDIO		((u_char)0x01)
-#define BCSR13_FETH_IRQMASK	((u_char)0xf0)
-#define BCSR15_FETH_IRQ		((u_char)0x20)
-
-#define PHY_INTERRUPT	SIU_INT_IRQ7
-
-/* For our show_cpuinfo hooks. */
-#define CPUINFO_VENDOR		"Embedded Planet"
-#define CPUINFO_MACHINE		"EP8260 PowerPC"
-
-/* Warm reset vector. */
-#define BOOTROM_RESTART_ADDR	((uint)0xfff00104)
-
-#endif /* __ASM_PLATFORMS_RPX8260_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/rpxclassic.h b/arch/ppc/platforms/rpxclassic.h
deleted file mode 100644
index a3c1118e5b0..00000000000
--- a/arch/ppc/platforms/rpxclassic.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * A collection of structures, addresses, and values associated with
- * the RPCG RPX-Classic board.  Copied from the RPX-Lite stuff.
- *
- * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
- */
-#ifdef __KERNEL__
-#ifndef __MACH_RPX_DEFS
-#define __MACH_RPX_DEFS
-
-
-#ifndef __ASSEMBLY__
-/* A Board Information structure that is given to a program when
- * prom starts it up.
- */
-typedef struct bd_info {
-	unsigned int	bi_memstart;	/* Memory start address */
-	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
-	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
-	unsigned int	bi_busfreq;	/* Bus Freq, in Hz */
-	unsigned char	bi_enetaddr[6];
-	unsigned int	bi_baudrate;
-} bd_t;
-
-extern bd_t m8xx_board_info;
-
-/* Memory map is configured by the PROM startup.
- * We just map a few things we need.  The CSR is actually 4 byte-wide
- * registers that can be accessed as 8-, 16-, or 32-bit values.
- */
-#define PCI_ISA_IO_ADDR		((unsigned)0x80000000)
-#define PCI_ISA_IO_SIZE		((uint)(512 * 1024 * 1024))
-#define PCI_ISA_MEM_ADDR	((unsigned)0xc0000000)
-#define PCI_ISA_MEM_SIZE	((uint)(512 * 1024 * 1024))
-#define RPX_CSR_ADDR		((uint)0xfa400000)
-#define RPX_CSR_SIZE		((uint)(4 * 1024))
-#define IMAP_ADDR		((uint)0xfa200000)
-#define IMAP_SIZE		((uint)(64 * 1024))
-#define PCI_CSR_ADDR		((uint)0x80000000)
-#define PCI_CSR_SIZE		((uint)(64 * 1024))
-#define PCMCIA_MEM_ADDR		((uint)0xe0000000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
-#define PCMCIA_IO_ADDR		((uint)0xe4000000)
-#define PCMCIA_IO_SIZE		((uint)(4 * 1024))
-#define PCMCIA_ATTRB_ADDR	((uint)0xe8000000)
-#define PCMCIA_ATTRB_SIZE	((uint)(4 * 1024))
-
-/* Things of interest in the CSR.
-*/
-#define BCSR0_ETHEN		((uint)0x80000000)
-#define BCSR0_ETHLPBK		((uint)0x40000000)
-#define BCSR0_COLTESTDIS	((uint)0x20000000)
-#define BCSR0_FULLDPLXDIS	((uint)0x10000000)
-#define BCSR0_ENFLSHSEL		((uint)0x04000000)
-#define BCSR0_FLASH_SEL		((uint)0x02000000)
-#define BCSR0_ENMONXCVR		((uint)0x01000000)
-
-#define BCSR0_PCMCIAVOLT	((uint)0x000f0000)	/* CLLF */
-#define BCSR0_PCMCIA3VOLT	((uint)0x000a0000)	/* CLLF */
-#define BCSR0_PCMCIA5VOLT	((uint)0x00060000)	/* CLLF */
-
-#define BCSR1_IPB5SEL           ((uint)0x00100000)
-#define BCSR1_PCVCTL4           ((uint)0x00080000)
-#define BCSR1_PCVCTL5           ((uint)0x00040000)
-#define BCSR1_PCVCTL6           ((uint)0x00020000)
-#define BCSR1_PCVCTL7           ((uint)0x00010000)
-
-#define BCSR2_EN232XCVR		((uint)0x00008000)
-#define BCSR2_QSPACESEL		((uint)0x00004000)
-#define BCSR2_FETHLEDMODE	((uint)0x00000800)	/* CLLF */
-
-/* define IO_BASE for pcmcia, CLLF only */
-#if !defined(CONFIG_PCI)
-#define _IO_BASE 0x80000000
-#define _IO_BASE_SIZE 0x1000
-
-/* for pcmcia sandisk */
-#ifdef CONFIG_IDE
-# define MAX_HWIFS 1
-#endif
-#endif
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT	SIU_LEVEL1	/* FEC interrupt */
-
-
-/* CPM Ethernet through SCCx.
- *
- * Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PA_ENET_RXD	((ushort)0x0001)
-#define PA_ENET_TXD	((ushort)0x0002)
-#define PA_ENET_TCLK	((ushort)0x0200)
-#define PA_ENET_RCLK	((ushort)0x0800)
-#define PB_ENET_TENA	((uint)0x00001000)
-#define PC_ENET_CLSN	((ushort)0x0010)
-#define PC_ENET_RENA	((ushort)0x0020)
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK	((uint)0x000000ff)
-#define SICR_ENET_CLKRT	((uint)0x0000003d)
-
-/* We don't use the 8259.
-*/
-
-#define NR_8259_INTS	0
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __MACH_RPX_DEFS */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/rpxlite.h b/arch/ppc/platforms/rpxlite.h
deleted file mode 100644
index b615501d55f..00000000000
--- a/arch/ppc/platforms/rpxlite.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * A collection of structures, addresses, and values associated with
- * the RPCG RPX-Lite board.  Copied from the MBX stuff.
- *
- * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
- */
-#ifdef __KERNEL__
-#ifndef __MACH_RPX_DEFS
-#define __MACH_RPX_DEFS
-
-
-#ifndef __ASSEMBLY__
-/* A Board Information structure that is given to a program when
- * prom starts it up.
- */
-typedef struct bd_info {
-	unsigned int	bi_memstart;	/* Memory start address */
-	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
-	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
-	unsigned int	bi_busfreq;	/* Bus Freq, in Hz */
-	unsigned char	bi_enetaddr[6];
-	unsigned int	bi_baudrate;
-} bd_t;
-
-extern bd_t m8xx_board_info;
-
-/* Memory map is configured by the PROM startup.
- * We just map a few things we need.  The CSR is actually 4 byte-wide
- * registers that can be accessed as 8-, 16-, or 32-bit values.
- */
-#define RPX_CSR_ADDR		((uint)0xfa400000)
-#define RPX_CSR_SIZE		((uint)(4 * 1024))
-#define IMAP_ADDR		((uint)0xfa200000)
-#define IMAP_SIZE		((uint)(64 * 1024))
-#define PCMCIA_MEM_ADDR		((uint)0x04000000)
-#define PCMCIA_MEM_SIZE		((uint)(64 * 1024))
-#define PCMCIA_IO_ADDR		((uint)0x04400000)
-#define PCMCIA_IO_SIZE		((uint)(4 * 1024))
-
-/* Things of interest in the CSR.
-*/
-#define BCSR0_ETHEN		((uint)0x80000000)
-#define BCSR0_ETHLPBK		((uint)0x40000000)
-#define BCSR0_COLTESTDIS	((uint)0x20000000)
-#define BCSR0_FULLDPLXDIS	((uint)0x10000000)
-#define BCSR0_LEDOFF		((uint)0x08000000)
-#define BCSR0_USBDISABLE	((uint)0x04000000)
-#define BCSR0_USBHISPEED	((uint)0x02000000)
-#define BCSR0_USBPWREN		((uint)0x01000000)
-#define BCSR0_PCMCIAVOLT	((uint)0x000f0000)
-#define BCSR0_PCMCIA3VOLT	((uint)0x000a0000)
-#define BCSR0_PCMCIA5VOLT	((uint)0x00060000)
-
-#define BCSR1_IPB5SEL          ((uint)0x00100000)
-#define BCSR1_PCVCTL4          ((uint)0x00080000)
-#define BCSR1_PCVCTL5          ((uint)0x00040000)
-#define BCSR1_PCVCTL6          ((uint)0x00020000)
-#define BCSR1_PCVCTL7          ((uint)0x00010000)
-
-/* define IO_BASE for pcmcia */
-#define _IO_BASE 0x80000000
-#define _IO_BASE_SIZE 0x1000
-
-#ifdef CONFIG_IDE
-# define MAX_HWIFS 1
-#endif
-
-/* CPM Ethernet through SCCx.
- *
- * This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
- * this may be unique to the RPX-Lite configuration.
- * Note TENA is on Port B.
- */
-#define PA_ENET_RXD	((ushort)0x0004)
-#define PA_ENET_TXD	((ushort)0x0008)
-#define PA_ENET_TCLK	((ushort)0x0200)
-#define PA_ENET_RCLK	((ushort)0x0800)
-#define PB_ENET_TENA	((uint)0x00002000)
-#define PC_ENET_CLSN	((ushort)0x0040)
-#define PC_ENET_RENA	((ushort)0x0080)
-
-#define SICR_ENET_MASK	((uint)0x0000ff00)
-#define SICR_ENET_CLKRT	((uint)0x00003d00)
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif /* !__ASSEMBLY__ */
-#endif /* __MACH_RPX_DEFS */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/sandpoint.c b/arch/ppc/platforms/sandpoint.c
deleted file mode 100644
index b4897bdb742..00000000000
--- a/arch/ppc/platforms/sandpoint.c
+++ /dev/null
@@ -1,651 +0,0 @@
-/*
- * Board setup routines for the Motorola SPS Sandpoint Test Platform.
- *
- * Author: Mark A. Greer
- *	 mgreer@mvista.com
- *
- * 2000-2003 (c) MontaVista Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * This file adds support for the Motorola SPS Sandpoint Test Platform.
- * These boards have a PPMC slot for the processor so any combination
- * of cpu and host bridge can be attached.  This port is for an 8240 PPMC
- * module from Motorola SPS and other closely related cpu/host bridge
- * combinations (e.g., 750/755/7400 with MPC107 host bridge).
- * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
- * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
- * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
- * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
- * but are really 5V).
- *
- * The firmware on the sandpoint is called DINK (not my acronym :).  This port
- * depends on DINK to do some basic initialization (e.g., initialize the memory
- * ctlr) and to ensure that the processor is using MAP B (CHRP map).
- *
- * The switch settings for the Sandpoint board MUST be as follows:
- * 	S3: down
- * 	S4: up
- * 	S5: up
- * 	S6: down
- *
- * 'down' is in the direction from the PCI slots towards the PPMC slot;
- * 'up' is in the direction from the PPMC slot towards the PCI slots.
- * Be careful, the way the sandpoint board is installed in XT chasses will
- * make the directions reversed.
- *
- * Since Motorola listened to our suggestions for improvement, we now have
- * the Sandpoint X3 board.  All of the PCI slots are available, it uses
- * the serial interrupt interface (just a hardware thing we need to
- * configure properly).
- *
- * Use the default X3 switch settings.  The interrupts are then:
- *		EPIC	Source
- *		  0	SIOINT 		(8259, active low)
- *		  1	PCI #1
- *		  2	PCI #2
- *		  3	PCI #3
- *		  4	PCI #4
- *		  7	Winbond INTC	(IDE interrupt)
- *		  8	Winbond INTD	(IDE interrupt)
- *
- *
- * Motorola has finally released a version of DINK32 that correctly
- * (seemingly) initializes the memory controller correctly, regardless
- * of the amount of memory in the system.  Once a method of determining
- * what version of DINK initializes the system for us, if applicable, is
- * found, we can hopefully stop hardcoding 32MB of RAM.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/major.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/serial.h>
-#include <linux/tty.h>	/* for linux/serial_core.h */
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/time.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/prom.h>
-#include <asm/smp.h>
-#include <asm/vga.h>
-#include <asm/open_pic.h>
-#include <asm/i8259.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/mpc10x.h>
-#include <asm/pci-bridge.h>
-#include <asm/kgdb.h>
-#include <asm/ppc_sys.h>
-
-#include "sandpoint.h"
-
-/* Set non-zero if an X2 Sandpoint detected. */
-static int sandpoint_is_x2;
-
-unsigned char __res[sizeof(bd_t)];
-
-static void sandpoint_halt(void);
-static void sandpoint_probe_type(void);
-
-/*
- * Define all of the IRQ senses and polarities.  Taken from the
- * Sandpoint X3 User's manual.
- */
-static u_char sandpoint_openpic_initsenses[] __initdata = {
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 0: SIOINT */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 2: PCI Slot 1 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 3: PCI Slot 2 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 4: PCI Slot 3 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 5: PCI Slot 4 */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* 8: IDE (INT C) */
-	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)	/* 9: IDE (INT D) */
-};
-
-/*
- * Motorola SPS Sandpoint interrupt routing.
- */
-static inline int
-x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *	PCI IDSEL/INTPIN->INTLINE
-	 * 	   A   B   C   D
-	 */
-	{
-		{ 16,  0,  0,  0 },	/* IDSEL 11 - i8259 on Winbond */
-		{  0,  0,  0,  0 },	/* IDSEL 12 - unused */
-		{ 18, 21, 20, 19 },	/* IDSEL 13 - PCI slot 1 */
-		{ 19, 18, 21, 20 },	/* IDSEL 14 - PCI slot 2 */
-		{ 20, 19, 18, 21 },	/* IDSEL 15 - PCI slot 3 */
-		{ 21, 20, 19, 18 },	/* IDSEL 16 - PCI slot 4 */
-	};
-
-	const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static inline int
-x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-	/*
-	 *	PCI IDSEL/INTPIN->INTLINE
-	 * 	   A   B   C   D
-	 */
-	{
-		{ 18,  0,  0,  0 },	/* IDSEL 11 - i8259 on Windbond */
-		{  0,  0,  0,  0 },	/* IDSEL 12 - unused */
-		{ 16, 17, 18, 19 },	/* IDSEL 13 - PCI slot 1 */
-		{ 17, 18, 19, 16 },	/* IDSEL 14 - PCI slot 2 */
-		{ 18, 19, 16, 17 },	/* IDSEL 15 - PCI slot 3 */
-		{ 19, 16, 17, 18 },	/* IDSEL 16 - PCI slot 4 */
-	};
-
-	const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __init
-sandpoint_setup_winbond_83553(struct pci_controller *hose)
-{
-	int		devfn;
-
-	/*
-	 * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
-	 * We can't route the IDE interrupt to PCI INTC# or INTD# because those
-	 * woule interfere with the PMC's INTC# and INTD# lines.
-	 */
-	/*
-	 * Winbond Fcn 0
-	 */
-	devfn = PCI_DEVFN(11,0);
-
-	early_write_config_byte(hose,
-				0,
-				devfn,
-				0x43, /* IDE Interrupt Routing Control */
-				0xef);
-	early_write_config_word(hose,
-				0,
-				devfn,
-				0x44, /* PCI Interrupt Routing Control */
-				0x0000);
-
-	/* Want ISA memory cycles to be forwarded to PCI bus */
-	early_write_config_byte(hose,
-				0,
-				devfn,
-				0x48, /* ISA-to-PCI Addr Decoder Control */
-				0xf0);
-
-	/* Enable Port 92.  */
-	early_write_config_byte(hose,
-				0,
-				devfn,
-				0x4e,	/* AT System Control Register */
-				0x06);
-	/*
-	 * Winbond Fcn 1
-	 */
-	devfn = PCI_DEVFN(11,1);
-
-	/* Put IDE controller into native mode. */
-	early_write_config_byte(hose,
-				0,
-				devfn,
-				0x09,	/* Programming interface Register */
-				0x8f);
-
-	/* Init IRQ routing, enable both ports, disable fast 16 */
-	early_write_config_dword(hose,
-				0,
-				devfn,
-				0x40,	/* IDE Control/Status Register */
-				0x00ff0011);
-	return;
-}
-
-/* On the sandpoint X2, we must avoid sending configuration cycles to
- * device #12 (IDSEL addr = AD12).
- */
-static int
-x2_exclude_device(u_char bus, u_char devfn)
-{
-	if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
-		return PCIBIOS_DEVICE_NOT_FOUND;
-	else
-		return PCIBIOS_SUCCESSFUL;
-}
-
-static void __init
-sandpoint_find_bridges(void)
-{
-	struct pci_controller	*hose;
-
-	hose = pcibios_alloc_controller();
-
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	if (mpc10x_bridge_init(hose,
-			       MPC10X_MEM_MAP_B,
-			       MPC10X_MEM_MAP_B,
-			       MPC10X_MAPB_EUMB_BASE) == 0) {
-
-		/* Do early winbond init, then scan PCI bus */
-		sandpoint_setup_winbond_83553(hose);
-		hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-		ppc_md.pcibios_fixup = NULL;
-		ppc_md.pcibios_fixup_bus = NULL;
-		ppc_md.pci_swizzle = common_swizzle;
-		if (sandpoint_is_x2) {
-			ppc_md.pci_map_irq = x2_map_irq;
-			ppc_md.pci_exclude_device = x2_exclude_device;
-		} else
-			ppc_md.pci_map_irq = x3_map_irq;
-	}
-	else {
-		if (ppc_md.progress)
-			ppc_md.progress("Bridge init failed", 0x100);
-		printk("Host bridge init failed\n");
-	}
-
-	return;
-}
-
-static void __init
-sandpoint_setup_arch(void)
-{
-	/* Probe for Sandpoint model */
-	sandpoint_probe_type();
-	if (sandpoint_is_x2)
-		epic_serial_mode = 0;
-
-	loops_per_jiffy = 100000000 / HZ;
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef	CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_HDA1;
-#endif
-
-	/* Lookup PCI host bridges */
-	sandpoint_find_bridges();
-
-	if (strncmp (cur_ppc_sys_spec->ppc_sys_name, "8245", 4) == 0)
-	{
-		bd_t *bp = (bd_t *)__res;
-		struct plat_serial8250_port *pdata;
-
-		pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART0);
-		if (pdata)
-		{
-			pdata[0].uartclk = bp->bi_busfreq;
-		}
-
-#ifdef CONFIG_SANDPOINT_ENABLE_UART1
-		pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC10X_UART1);
-		if (pdata)
-		{
-			pdata[0].uartclk = bp->bi_busfreq;
-		}
-#else
-		ppc_sys_device_remove(MPC10X_UART1);
-#endif
-	}
-
-	printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
-	printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
-
-	/* DINK32 12.3 and below do not correctly enable any caches.
-	 * We will do this now with good known values.  Future versions
-	 * of DINK32 are supposed to get this correct.
-	 */
-	if (cpu_has_feature(CPU_FTR_SPEC7450))
-		/* 745x is different.  We only want to pass along enable. */
-		_set_L2CR(L2CR_L2E);
-	else if (cpu_has_feature(CPU_FTR_L2CR))
-		/* All modules have 1MB of L2.  We also assume that an
-		 * L2 divisor of 3 will work.
-		 */
-		_set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
-				| L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
-#if 0
-	/* Untested right now. */
-	if (cpu_has_feature(CPU_FTR_L3CR)) {
-		/* Magic value. */
-		_set_L3CR(0x8f032000);
-	}
-#endif
-}
-
-#define	SANDPOINT_87308_CFG_ADDR		0x15c
-#define	SANDPOINT_87308_CFG_DATA		0x15d
-
-#define	SANDPOINT_87308_CFG_INB(addr, byte) {				\
-	outb((addr), SANDPOINT_87308_CFG_ADDR);				\
-	(byte) = inb(SANDPOINT_87308_CFG_DATA);				\
-}
-
-#define	SANDPOINT_87308_CFG_OUTB(addr, byte) {				\
-	outb((addr), SANDPOINT_87308_CFG_ADDR);				\
-	outb((byte), SANDPOINT_87308_CFG_DATA);				\
-}
-
-#define SANDPOINT_87308_SELECT_DEV(dev_num) {				\
-	SANDPOINT_87308_CFG_OUTB(0x07, (dev_num));			\
-}
-
-#define	SANDPOINT_87308_DEV_ENABLE(dev_num) {				\
-	SANDPOINT_87308_SELECT_DEV(dev_num);				\
-	SANDPOINT_87308_CFG_OUTB(0x30, 0x01);				\
-}
-
-/*
- * To probe the Sandpoint type, we need to check for a connection between GPIO
- * pins 6 and 7 on the NS87308 SuperIO.
- */
-static void __init sandpoint_probe_type(void)
-{
-	u8 x;
-	/* First, ensure that the GPIO pins are enabled. */
-	SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
-	SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
-	SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
-	SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
-
-	/* Now, set pin 7 to output and pin 6 to input. */
-	outb((inb(0x701) | 0x80) & 0xbf, 0x701);
-	/* Set push-pull output */
-	outb(inb(0x702) | 0x80, 0x702);
-	/* Set pull-up on input */
-	outb(inb(0x703) | 0x40, 0x703);
-	/* Set output high and check */
-	x = inb(0x700);
-	outb(x | 0x80, 0x700);
-	x = inb(0x700);
-	sandpoint_is_x2 = ! (x & 0x40);
-	if (ppc_md.progress && sandpoint_is_x2)
-		ppc_md.progress("High output says X2", 0);
-	/* Set output low and check */
-	outb(x & 0x7f, 0x700);
-	sandpoint_is_x2 |= inb(0x700) & 0x40;
-	if (ppc_md.progress && sandpoint_is_x2)
-		ppc_md.progress("Low output says X2", 0);
-	if (ppc_md.progress && ! sandpoint_is_x2)
-		ppc_md.progress("Sandpoint is X3", 0);
-}
-
-/*
- * Fix IDE interrupts.
- */
-static int __init
-sandpoint_fix_winbond_83553(void)
-{
-	/* Make some 8259 interrupt level sensitive */
-	outb(0xe0, 0x4d0);
-	outb(0xde, 0x4d1);
-
-	return 0;
-}
-
-arch_initcall(sandpoint_fix_winbond_83553);
-
-/*
- * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
- */
-static int __init
-sandpoint_setup_natl_87308(void)
-{
-	u_char	reg;
-
-	/*
-	 * Enable all the devices on the Super I/O chip.
-	 */
-	SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
-	SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
-	SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
-	SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
-	SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
-	SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
-	SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
-	SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
-	SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
-	SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
-	SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
-
-	/* Set up floppy in PS/2 mode */
-	outb(0x09, SIO_CONFIG_RA);
-	reg = inb(SIO_CONFIG_RD);
-	reg = (reg & 0x3F) | 0x40;
-	outb(reg, SIO_CONFIG_RD);
-	outb(reg, SIO_CONFIG_RD);	/* Have to write twice to change! */
-
-	return 0;
-}
-
-arch_initcall(sandpoint_setup_natl_87308);
-
-static int __init
-sandpoint_request_io(void)
-{
-	request_region(0x00,0x20,"dma1");
-	request_region(0x20,0x20,"pic1");
-	request_region(0x40,0x20,"timer");
-	request_region(0x80,0x10,"dma page reg");
-	request_region(0xa0,0x20,"pic2");
-	request_region(0xc0,0x20,"dma2");
-
-	return 0;
-}
-
-arch_initcall(sandpoint_request_io);
-
-/*
- * Interrupt setup and service.  Interrupts on the Sandpoint come
- * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
- * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
- * IDE is on EPIC 7 and 8.
- */
-static void __init
-sandpoint_init_IRQ(void)
-{
-	int i;
-
-	OpenPIC_InitSenses = sandpoint_openpic_initsenses;
-	OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
-
-	mpc10x_set_openpic();
-	openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
-			i8259_irq);
-
-	/*
-	 * The EPIC allows for a read in the range of 0xFEF00000 ->
-	 * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
-	 */
-	i8259_init(0xfef00000, 0);
-}
-
-static unsigned long __init
-sandpoint_find_end_of_memory(void)
-{
-	bd_t *bp = (bd_t *)__res;
-
-	if (bp->bi_memsize)
-		return bp->bi_memsize;
-
-	/* DINK32 13.0 correctly initializes things, so iff you use
-	 * this you _should_ be able to change this instead of a
-	 * hardcoded value. */
-#if 0
-	return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
-#else
-	return 32*1024*1024;
-#endif
-}
-
-static void __init
-sandpoint_map_io(void)
-{
-	io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
-}
-
-static void
-sandpoint_restart(char *cmd)
-{
-	local_irq_disable();
-
-	/* Set exception prefix high - to the firmware */
-	_nmask_and_or_msr(0, MSR_IP);
-
-	/* Reset system via Port 92 */
-	outb(0x00, 0x92);
-	outb(0x01, 0x92);
-	for(;;);	/* Spin until reset happens */
-}
-
-static void
-sandpoint_power_off(void)
-{
-	local_irq_disable();
-	for(;;);	/* No way to shut power off with software */
-	/* NOTREACHED */
-}
-
-static void
-sandpoint_halt(void)
-{
-	sandpoint_power_off();
-	/* NOTREACHED */
-}
-
-static int
-sandpoint_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: Motorola SPS\n");
-	seq_printf(m, "machine\t\t: Sandpoint\n");
-
-	return 0;
-}
-
-/*
- * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
- */
-static __inline__ void
-sandpoint_set_bat(void)
-{
-	unsigned long bat3u, bat3l;
-
-	__asm__ __volatile__(
-			" lis %0,0xf800\n	\
-			ori %1,%0,0x002a\n	\
-			ori %0,%0,0x0ffe\n	\
-			mtspr 0x21e,%0\n	\
-			mtspr 0x21f,%1\n	\
-			isync\n			\
-			sync "
-			: "=r" (bat3u), "=r" (bat3l));
-}
-
-TODC_ALLOC();
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-		unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	/* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
-	 * are non-zero, then we should use the board info from the bd_t
-	 * structure and the cmdline pointed to by r6 instead of the
-	 * information from birecs, if any.  Otherwise, use the information
-	 * from birecs as discovered by the preceding call to
-	 * parse_bootinfo().  This rule should work with both PPCBoot, which
-	 * uses a bd_t board info structure, and the kernel boot wrapper,
-	 * which uses birecs.
-	 */
-	if (r3 && r6) {
-		/* copy board info structure */
-		memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
-		/* copy command line */
-		*(char *)(r7+KERNELBASE) = 0;
-		strcpy(cmd_line, (char *)(r6+KERNELBASE));
-	}
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	/* take care of initrd if we have one */
-	if (r4) {
-		initrd_start = r4 + KERNELBASE;
-		initrd_end = r5 + KERNELBASE;
-	}
-#endif /* CONFIG_BLK_DEV_INITRD */
-
-	/* Map in board regs, etc. */
-	sandpoint_set_bat();
-
-	isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
-	isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
-	pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
-	ISA_DMA_THRESHOLD = 0x00ffffff;
-	DMA_MODE_READ = 0x44;
-	DMA_MODE_WRITE = 0x48;
-	ppc_do_canonicalize_irqs = 1;
-
-	ppc_md.setup_arch = sandpoint_setup_arch;
-	ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
-	ppc_md.init_IRQ = sandpoint_init_IRQ;
-	ppc_md.get_irq = openpic_get_irq;
-
-	ppc_md.restart = sandpoint_restart;
-	ppc_md.power_off = sandpoint_power_off;
-	ppc_md.halt = sandpoint_halt;
-
-	ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
-	ppc_md.setup_io_mappings = sandpoint_map_io;
-
-	TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.calibrate_decr = todc_calibrate_decr;
-
-	ppc_md.nvram_read_val = todc_mc146818_read_val;
-	ppc_md.nvram_write_val = todc_mc146818_write_val;
-
-#ifdef CONFIG_KGDB
-	ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
-#endif
-#ifdef CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.progress = gen550_progress;
-#endif
-}
diff --git a/arch/ppc/platforms/sandpoint.h b/arch/ppc/platforms/sandpoint.h
deleted file mode 100644
index ed83759e404..00000000000
--- a/arch/ppc/platforms/sandpoint.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Definitions for Motorola SPS Sandpoint Test Platform
- *
- * Author: Mark A. Greer
- *         mgreer@mvista.com
- *
- * 2000-2003 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-/*
- * Sandpoint uses the CHRP map (Map B).
- */
-
-#ifndef __PPC_PLATFORMS_SANDPOINT_H
-#define __PPC_PLATFORMS_SANDPOINT_H
-
-#include <asm/ppcboot.h>
-
-#if 0
-/* The Sandpoint X3 allows the IDE interrupt to be directly connected
- * from the Windbond (PCI INTC or INTD) to the serial EPIC.  Someday
- * we should try this, but it was easier to use the existing 83c553
- * initialization than change it to route the different interrupts :-).
- *	-- Dan
- */
-#define SANDPOINT_IDE_INT0		23	/* EPIC 7 */
-#define SANDPOINT_IDE_INT1		24	/* EPIC 8 */
-#endif
-
-/*
- * The sandpoint boards have processor modules that either have an 8240 or
- * an MPC107 host bridge on them.  These bridges have an IDSEL line that allows
- * them to respond to PCI transactions as if they were a normal PCI devices.
- * However, the processor on the processor side of the bridge can not reach
- * out onto the PCI bus and then select the bridge or bad things will happen
- * (documented in the 8240 and 107 manuals).
- * Because of this, we always skip the bridge PCI device when accessing the
- * PCI bus.  The PCI slot that the bridge occupies is defined by the macro
- * below.
- */
-#define SANDPOINT_HOST_BRIDGE_IDSEL     12
-
-/*
- * Serial defines.
- */
-#define SANDPOINT_SERIAL_0		0xfe0003f8
-#define SANDPOINT_SERIAL_1		0xfe0002f8
-
-#define RS_TABLE_SIZE  2
-
-/* Rate for the 1.8432 Mhz clock for the onboard serial chip */
-#define BASE_BAUD			( 1843200 / 16 )
-#define UART_CLK			1843200
-
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF)
-#endif
-
-#define STD_SERIAL_PORT_DFNS \
-        { 0, BASE_BAUD, SANDPOINT_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
-		iomem_base: (u8 *)SANDPOINT_SERIAL_0,			  \
-		io_type: SERIAL_IO_MEM },				  \
-        { 0, BASE_BAUD, SANDPOINT_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
-		iomem_base: (u8 *)SANDPOINT_SERIAL_1,			  \
-		io_type: SERIAL_IO_MEM },
-
-#define SERIAL_PORT_DFNS \
-        STD_SERIAL_PORT_DFNS
-
-#endif /* __PPC_PLATFORMS_SANDPOINT_H */
diff --git a/arch/ppc/platforms/sbc82xx.c b/arch/ppc/platforms/sbc82xx.c
deleted file mode 100644
index 24f6e0694ac..00000000000
--- a/arch/ppc/platforms/sbc82xx.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * SBC82XX platform support
- *
- * Author: Guy Streeter <streeter@redhat.com>
- *
- * Derived from: est8260_setup.c by Allen Curtis, ONZ
- *
- * Copyright 2004 Red Hat, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/stddef.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/init.h>
-#include <linux/pci.h>
-
-#include <asm/mpc8260.h>
-#include <asm/machdep.h>
-#include <asm/io.h>
-#include <asm/todc.h>
-#include <asm/immap_cpm2.h>
-#include <asm/pci.h>
-
-static void (*callback_init_IRQ)(void);
-
-extern unsigned char __res[sizeof(bd_t)];
-
-#ifdef CONFIG_GEN_RTC
-TODC_ALLOC();
-
-/*
- * Timer init happens before mem_init but after paging init, so we cannot
- * directly use ioremap() at that time.
- * late_time_init() is call after paging init.
- */
-
-static void sbc82xx_time_init(void)
-{
-	volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
-
-	/* Set up CS11 for RTC chip */
-	mc->memc_br11=0;
-	mc->memc_or11=0xffff0836;
-	mc->memc_br11=SBC82xx_TODC_NVRAM_ADDR | 0x0801;
-
-	TODC_INIT(TODC_TYPE_MK48T59, 0, 0, SBC82xx_TODC_NVRAM_ADDR, 0);
-
-	todc_info->nvram_data =
-		(unsigned int)ioremap(todc_info->nvram_data, 0x2000);
-	BUG_ON(!todc_info->nvram_data);
-	ppc_md.get_rtc_time	= todc_get_rtc_time;
-	ppc_md.set_rtc_time	= todc_set_rtc_time;
-	ppc_md.nvram_read_val	= todc_direct_read_val;
-	ppc_md.nvram_write_val	= todc_direct_write_val;
-	todc_time_init();
-}
-#endif /* CONFIG_GEN_RTC */
-
-static volatile char *sbc82xx_i8259_map;
-static char sbc82xx_i8259_mask = 0xff;
-static DEFINE_SPINLOCK(sbc82xx_i8259_lock);
-
-static void sbc82xx_i8259_mask_and_ack_irq(unsigned int irq_nr)
-{
-	unsigned long flags;
-
-	irq_nr -= NR_SIU_INTS;
-
-	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
-	sbc82xx_i8259_mask |= 1 << irq_nr;
-	(void) sbc82xx_i8259_map[1];	/* Dummy read */
-	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
-	sbc82xx_i8259_map[0] = 0x20;	/* OCW2: Non-specific EOI */
-	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
-}
-
-static void sbc82xx_i8259_mask_irq(unsigned int irq_nr)
-{
-	unsigned long flags;
-
-	irq_nr -= NR_SIU_INTS;
-
-	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
-	sbc82xx_i8259_mask |= 1 << irq_nr;
-	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
-	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
-}
-
-static void sbc82xx_i8259_unmask_irq(unsigned int irq_nr)
-{
-	unsigned long flags;
-
-	irq_nr -= NR_SIU_INTS;
-
-	spin_lock_irqsave(&sbc82xx_i8259_lock, flags);
-	sbc82xx_i8259_mask &= ~(1 << irq_nr);
-	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask;
-	spin_unlock_irqrestore(&sbc82xx_i8259_lock, flags);
-}
-
-static void sbc82xx_i8259_end_irq(unsigned int irq)
-{
-	if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))
-	    && irq_desc[irq].action)
-		sbc82xx_i8259_unmask_irq(irq);
-}
-
-
-struct hw_interrupt_type sbc82xx_i8259_ic = {
-	.typename = " i8259     ",
-	.enable = sbc82xx_i8259_unmask_irq,
-	.disable = sbc82xx_i8259_mask_irq,
-	.ack = sbc82xx_i8259_mask_and_ack_irq,
-	.end = sbc82xx_i8259_end_irq,
-};
-
-static irqreturn_t sbc82xx_i8259_demux(int dummy, void *dev_id)
-{
-	int irq;
-
-	spin_lock(&sbc82xx_i8259_lock);
-
-	sbc82xx_i8259_map[0] = 0x0c;	/* OCW3: Read IR register on RD# pulse */
-	irq = sbc82xx_i8259_map[0] & 7;	/* Read IRR */
-
-	if (irq == 7) {
-		/* Possible spurious interrupt */
-		int isr;
-		sbc82xx_i8259_map[0] = 0x0b;	/* OCW3: Read IS register on RD# pulse */
-		isr = sbc82xx_i8259_map[0];	/* Read ISR */
-
-		if (!(isr & 0x80)) {
-			printk(KERN_INFO "Spurious i8259 interrupt\n");
-			return IRQ_HANDLED;
-		}
-	}
-	__do_IRQ(NR_SIU_INTS + irq);
-	return IRQ_HANDLED;
-}
-
-static struct irqaction sbc82xx_i8259_irqaction = {
-	.handler = sbc82xx_i8259_demux,
-	.flags = IRQF_DISABLED,
-	.mask = CPU_MASK_NONE,
-	.name = "i8259 demux",
-};
-
-void __init sbc82xx_init_IRQ(void)
-{
-	volatile memctl_cpm2_t *mc = &cpm2_immr->im_memctl;
-	volatile intctl_cpm2_t *ic = &cpm2_immr->im_intctl;
-	int i;
-
-	callback_init_IRQ();
-
-	/* u-boot doesn't always set the board up correctly */
-	mc->memc_br5 = 0;
-	mc->memc_or5 = 0xfff00856;
-	mc->memc_br5 = 0x22000801;
-
-	sbc82xx_i8259_map = ioremap(0x22008000, 2);
-	if (!sbc82xx_i8259_map) {
-		printk(KERN_CRIT "Mapping i8259 interrupt controller failed\n");
-		return;
-	}
-	
-	/* Set up the interrupt handlers for the i8259 IRQs */
-	for (i = NR_SIU_INTS; i < NR_SIU_INTS + 8; i++) {
-                irq_desc[i].chip = &sbc82xx_i8259_ic;
-		irq_desc[i].status |= IRQ_LEVEL;
-	}
-
-	/* make IRQ6 level sensitive */
-	ic->ic_siexr &= ~(1 << (14 - (SIU_INT_IRQ6 - SIU_INT_IRQ1)));
-	irq_desc[SIU_INT_IRQ6].status |= IRQ_LEVEL;
-
-	/* Initialise the i8259 */
-	sbc82xx_i8259_map[0] = 0x1b;	/* ICW1: Level, no cascade, ICW4 */
-	sbc82xx_i8259_map[1] = 0x00;	/* ICW2: vector base */
-					/* No ICW3 (no cascade) */
-	sbc82xx_i8259_map[1] = 0x01;	/* ICW4: 8086 mode, normal EOI */
-
-	sbc82xx_i8259_map[0] = 0x0b;	/* OCW3: Read IS register on RD# pulse */
-
-	sbc82xx_i8259_map[1] = sbc82xx_i8259_mask; /* Set interrupt mask */
-
-	/* Request cascade IRQ */
-	if (setup_irq(SIU_INT_IRQ6, &sbc82xx_i8259_irqaction)) {
-		printk("Installation of i8259 IRQ demultiplexer failed.\n");
-	}
-}
-
-static int sbc82xx_pci_map_irq(struct pci_dev *dev, unsigned char idsel,
-			       unsigned char pin)
-{
-	static char pci_irq_table[][4] = {
-		/*
-		 * PCI IDSEL/INTPIN->INTLINE
-		 *  A      B      C      D
-		 */
-		{ SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD },	/* IDSEL 16 - PMC slot */
-		{ SBC82xx_PC_IRQA, SBC82xx_PC_IRQB, -1,  -1  },			/* IDSEL 17 - CardBus */
-		{ SBC82xx_PIRQA, SBC82xx_PIRQB, SBC82xx_PIRQC, SBC82xx_PIRQD }, /* IDSEL 18 - PCI-X bridge */
-	};
-
-	const long min_idsel = 16, max_idsel = 18, irqs_per_slot = 4;
-
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __devinit quirk_sbc8260_cardbus(struct pci_dev *pdev)
-{
-	uint32_t ctrl;
-
-	if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(17, 0))
-		return;
-
-	printk(KERN_INFO "Setting up CardBus controller\n");
-
-	/* Set P2CCLK bit in System Control Register */
-	pci_read_config_dword(pdev, 0x80, &ctrl);
-	ctrl |= (1<<27);
-	pci_write_config_dword(pdev, 0x80, ctrl);
-
-	/* Set MFUNC up for PCI IRQ routing via INTA and INTB, and LEDs. */
-	pci_write_config_dword(pdev, 0x8c, 0x00c01d22);
-
-}
-DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1420, quirk_sbc8260_cardbus);
-
-void __init
-m82xx_board_init(void)
-{
-	/* u-boot may be using one of the FCC Ethernet devices.
-	   Use the MAC address to the SCC. */
-	__res[offsetof(bd_t, bi_enetaddr[5])] &= ~3;
-
-	/* Anything special for this platform */
-	callback_init_IRQ	= ppc_md.init_IRQ;
-
-	ppc_md.init_IRQ		= sbc82xx_init_IRQ;
-	ppc_md.pci_map_irq	= sbc82xx_pci_map_irq;
-#ifdef CONFIG_GEN_RTC
-	ppc_md.time_init        = NULL;
-	ppc_md.get_rtc_time     = NULL;
-	ppc_md.set_rtc_time     = NULL;
-	ppc_md.nvram_read_val   = NULL;
-	ppc_md.nvram_write_val  = NULL;
-	late_time_init		= sbc82xx_time_init;
-#endif /* CONFIG_GEN_RTC */
-}
diff --git a/arch/ppc/platforms/sbc82xx.h b/arch/ppc/platforms/sbc82xx.h
deleted file mode 100644
index e4042d4995f..00000000000
--- a/arch/ppc/platforms/sbc82xx.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Board information for the SBCPowerQUICCII, which should be generic for
- * all 8260 boards.  The IMMR is now given to us so the hard define
- * will soon be removed.  All of the clock values are computed from
- * the configuration SCMR and the Power-On-Reset word.
- */
-
-#ifndef __PPC_SBC82xx_H__
-#define __PPC_SBC82xx_H__
-
-#include <asm/ppcboot.h>
-
-#define CPM_MAP_ADDR			0xf0000000
-
-#define SBC82xx_TODC_NVRAM_ADDR		0xd0000000
-
-#define SBC82xx_MACADDR_NVRAM_FCC1	0x220000c9	/* JP6B */
-#define SBC82xx_MACADDR_NVRAM_SCC1	0x220000cf	/* JP6A */
-#define SBC82xx_MACADDR_NVRAM_FCC2	0x220000d5	/* JP7A */
-#define SBC82xx_MACADDR_NVRAM_FCC3	0x220000db	/* JP7B */
-
-/* For our show_cpuinfo hooks. */
-#define CPUINFO_VENDOR		"Wind River"
-#define CPUINFO_MACHINE		"SBC PowerQUICC II"
-
-#define BOOTROM_RESTART_ADDR      ((uint)0x40000104)
-
-#define SBC82xx_PC_IRQA (NR_SIU_INTS+0)
-#define SBC82xx_PC_IRQB (NR_SIU_INTS+1)
-#define SBC82xx_MPC185_IRQ (NR_SIU_INTS+2)
-#define SBC82xx_ATM_IRQ (NR_SIU_INTS+3)
-#define SBC82xx_PIRQA (NR_SIU_INTS+4)
-#define SBC82xx_PIRQB (NR_SIU_INTS+5)
-#define SBC82xx_PIRQC (NR_SIU_INTS+6)
-#define SBC82xx_PIRQD (NR_SIU_INTS+7)
-
-#endif /* __PPC_SBC82xx_H__ */
diff --git a/arch/ppc/platforms/sbs8260.h b/arch/ppc/platforms/sbs8260.h
deleted file mode 100644
index d51427a0f0d..00000000000
--- a/arch/ppc/platforms/sbs8260.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __ASSEMBLY__
-/* Board information for various SBS 8260 cards, which should be generic for
- * all 8260 boards.  The IMMR is now given to us so the hard define
- * will soon be removed.  All of the clock values are computed from
- * the configuration SCMR and the Power-On-Reset word.
- */
-
-#define CPM_MAP_ADDR	((uint)0xfe000000)
-
-
-/* A Board Information structure that is given to a program when
- * prom starts it up.
- */
-typedef struct bd_info {
-	unsigned int	bi_memstart;	/* Memory start address */
-	unsigned int	bi_memsize;	/* Memory (end) size in bytes */
-	unsigned int	bi_intfreq;	/* Internal Freq, in Hz */
-	unsigned int	bi_busfreq;	/* Bus Freq, in MHz */
-	unsigned int	bi_cpmfreq;	/* CPM Freq, in MHz */
-	unsigned int	bi_brgfreq;	/* BRG Freq, in MHz */
-	unsigned int	bi_vco;		/* VCO Out from PLL */
-	unsigned int	bi_baudrate;	/* Default console baud rate */
-	unsigned int	bi_immr;	/* IMMR when called from boot rom */
-	unsigned char	bi_enetaddr[6];
-} bd_t;
-
-extern bd_t m8xx_board_info;
-#endif /* !__ASSEMBLY__ */
diff --git a/arch/ppc/platforms/spruce.c b/arch/ppc/platforms/spruce.c
deleted file mode 100644
index a344134f14b..00000000000
--- a/arch/ppc/platforms/spruce.c
+++ /dev/null
@@ -1,322 +0,0 @@
-/*
- * Board and PCI setup routines for IBM Spruce
- *
- * Author: MontaVista Software <source@mvista.com>
- *
- * 2000-2004 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/stddef.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/reboot.h>
-#include <linux/pci.h>
-#include <linux/kdev_t.h>
-#include <linux/types.h>
-#include <linux/major.h>
-#include <linux/initrd.h>
-#include <linux/console.h>
-#include <linux/delay.h>
-#include <linux/seq_file.h>
-#include <linux/root_dev.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/serial_core.h>
-#include <linux/serial_8250.h>
-
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/dma.h>
-#include <asm/io.h>
-#include <asm/machdep.h>
-#include <asm/time.h>
-#include <asm/todc.h>
-#include <asm/bootinfo.h>
-#include <asm/kgdb.h>
-
-#include <syslib/cpc700.h>
-
-#include "spruce.h"
-
-static inline int
-spruce_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
-	static char pci_irq_table[][4] =
-		/*
-		 * 	PCI IDSEL/INTPIN->INTLINE
-		 * 	A	B	C	D
-		 */
-	{
-		{23, 24, 25, 26},	/* IDSEL 1 - PCI slot 3 */
-		{24, 25, 26, 23},	/* IDSEL 2 - PCI slot 2 */
-		{25, 26, 23, 24},	/* IDSEL 3 - PCI slot 1 */
-		{26, 23, 24, 25},	/* IDSEL 4 - PCI slot 0 */
-	};
-
-	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
-	return PCI_IRQ_TABLE_LOOKUP;
-}
-
-static void __init
-spruce_setup_hose(void)
-{
-	struct pci_controller *hose;
-
-	/* Setup hose */
-	hose = pcibios_alloc_controller();
-	if (!hose)
-		return;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	pci_init_resource(&hose->io_resource,
-			SPRUCE_PCI_LOWER_IO,
-			SPRUCE_PCI_UPPER_IO,
-			IORESOURCE_IO,
-			"PCI host bridge");
-
-	pci_init_resource(&hose->mem_resources[0],
-			SPRUCE_PCI_LOWER_MEM,
-			SPRUCE_PCI_UPPER_MEM,
-			IORESOURCE_MEM,
-			"PCI host bridge");
-
-	hose->io_space.start = SPRUCE_PCI_LOWER_IO;
-	hose->io_space.end = SPRUCE_PCI_UPPER_IO;
-	hose->mem_space.start = SPRUCE_PCI_LOWER_MEM;
-	hose->mem_space.end = SPRUCE_PCI_UPPER_MEM;
-	hose->io_base_virt = (void *)SPRUCE_ISA_IO_BASE;
-
-	setup_indirect_pci(hose,
-			SPRUCE_PCI_CONFIG_ADDR,
-			SPRUCE_PCI_CONFIG_DATA);
-
-	hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
-
-	ppc_md.pci_swizzle = common_swizzle;
-	ppc_md.pci_map_irq = spruce_map_irq;
-}
-
-/*
- * CPC700 PIC interrupt programming table
- *
- * First entry is the sensitivity (level/edge), second is the polarity.
- */
-unsigned int cpc700_irq_assigns[32][2] = {
-	{ 1, 1 },       /* IRQ  0: ECC Correctable Error - rising edge */
-	{ 1, 1 },       /* IRQ  1: PCI Write Mem Range   - rising edge */
-	{ 0, 1 },       /* IRQ  2: PCI Write Command Reg - active high */
-	{ 0, 1 },       /* IRQ  3: UART 0                - active high */
-	{ 0, 1 },       /* IRQ  4: UART 1                - active high */
-	{ 0, 1 },       /* IRQ  5: ICC 0                 - active high */
-	{ 0, 1 },       /* IRQ  6: ICC 1                 - active high */
-	{ 0, 1 },       /* IRQ  7: GPT Compare 0         - active high */
-	{ 0, 1 },       /* IRQ  8: GPT Compare 1         - active high */
-	{ 0, 1 },       /* IRQ  9: GPT Compare 2         - active high */
-	{ 0, 1 },       /* IRQ 10: GPT Compare 3         - active high */
-	{ 0, 1 },       /* IRQ 11: GPT Compare 4         - active high */
-	{ 0, 1 },       /* IRQ 12: GPT Capture 0         - active high */
-	{ 0, 1 },       /* IRQ 13: GPT Capture 1         - active high */
-	{ 0, 1 },       /* IRQ 14: GPT Capture 2         - active high */
-	{ 0, 1 },       /* IRQ 15: GPT Capture 3         - active high */
-	{ 0, 1 },       /* IRQ 16: GPT Capture 4         - active high */
-	{ 0, 0 },       /* IRQ 17: Reserved */
-	{ 0, 0 },       /* IRQ 18: Reserved */
-	{ 0, 0 },       /* IRQ 19: Reserved */
-	{ 0, 1 },       /* IRQ 20: FPGA EXT_IRQ0         - active high */
-	{ 1, 1 },       /* IRQ 21: Mouse                 - rising edge */
-	{ 1, 1 },       /* IRQ 22: Keyboard              - rising edge */
-	{ 0, 0 },       /* IRQ 23: PCI Slot 3            - active low */
-	{ 0, 0 },       /* IRQ 24: PCI Slot 2            - active low */
-	{ 0, 0 },       /* IRQ 25: PCI Slot 1            - active low */
-	{ 0, 0 },       /* IRQ 26: PCI Slot 0            - active low */
-};
-
-static void __init
-spruce_calibrate_decr(void)
-{
-	int freq, divisor = 4;
-
-	/* determine processor bus speed */
-	freq = SPRUCE_BUS_SPEED;
-	tb_ticks_per_jiffy = freq / HZ / divisor;
-	tb_to_us = mulhwu_scale_factor(freq/divisor, 1000000);
-}
-
-static int
-spruce_show_cpuinfo(struct seq_file *m)
-{
-	seq_printf(m, "vendor\t\t: IBM\n");
-	seq_printf(m, "machine\t\t: Spruce\n");
-
-	return 0;
-}
-
-static void __init
-spruce_early_serial_map(void)
-{
-	u32 uart_clk;
-	struct uart_port serial_req;
-
-	if (SPRUCE_UARTCLK_IS_33M(readb(SPRUCE_FPGA_REG_A)))
-		uart_clk = SPRUCE_BAUD_33M * 16;
-	else
-		uart_clk = SPRUCE_BAUD_30M * 16;
-
-	/* Setup serial port access */
-	memset(&serial_req, 0, sizeof(serial_req));
-	serial_req.uartclk = uart_clk;
-	serial_req.irq = UART0_INT;
-	serial_req.flags = UPF_BOOT_AUTOCONF;
-	serial_req.iotype = UPIO_MEM;
-	serial_req.membase = (u_char *)UART0_IO_BASE;
-	serial_req.regshift = 0;
-
-#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
-	gen550_init(0, &serial_req);
-#endif
-#ifdef CONFIG_SERIAL_8250
-	if (early_serial_setup(&serial_req) != 0)
-		printk("Early serial init of port 0 failed\n");
-#endif
-
-	/* Assume early_serial_setup() doesn't modify serial_req */
-	serial_req.line = 1;
-	serial_req.irq = UART1_INT;
-	serial_req.membase = (u_char *)UART1_IO_BASE;
-
-#if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
-	gen550_init(1, &serial_req);
-#endif
-#ifdef CONFIG_SERIAL_8250
-	if (early_serial_setup(&serial_req) != 0)
-		printk("Early serial init of port 1 failed\n");
-#endif
-}
-
-TODC_ALLOC();
-
-static void __init
-spruce_setup_arch(void)
-{
-	/* Setup TODC access */
-	TODC_INIT(TODC_TYPE_DS1643, 0, 0, SPRUCE_RTC_BASE_ADDR, 8);
-
-	/* init to some ~sane value until calibrate_delay() runs */
-	loops_per_jiffy = 50000000 / HZ;
-
-	/* Setup PCI host bridge */
-	spruce_setup_hose();
-
-#ifdef CONFIG_BLK_DEV_INITRD
-	if (initrd_start)
-		ROOT_DEV = Root_RAM0;
-	else
-#endif
-#ifdef CONFIG_ROOT_NFS
-		ROOT_DEV = Root_NFS;
-#else
-		ROOT_DEV = Root_SDA1;
-#endif
-
-	/* Identify the system */
-	printk(KERN_INFO "System Identification: IBM Spruce\n");
-	printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
-}
-
-static void
-spruce_restart(char *cmd)
-{
-	local_irq_disable();
-
-	/* SRR0 has system reset vector, SRR1 has default MSR value */
-	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
-	__asm__ __volatile__
-	("\n\
-	lis	3,0xfff0	\n\
-	ori	3,3,0x0100	\n\
-	mtspr	26,3		\n\
-	li	3,0		\n\
-	mtspr	27,3		\n\
-	rfi			\n\
-	");
-	for(;;);
-}
-
-static void
-spruce_power_off(void)
-{
-	for(;;);
-}
-
-static void
-spruce_halt(void)
-{
-	spruce_restart(NULL);
-}
-
-static void __init
-spruce_map_io(void)
-{
-	io_block_mapping(SPRUCE_PCI_IO_BASE, SPRUCE_PCI_PHY_IO_BASE,
-			 0x08000000, _PAGE_IO);
-}
-
-/*
- * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
- */
-static __inline__ void
-spruce_set_bat(void)
-{
-	mb();
-	mtspr(SPRN_DBAT1U, 0xf8000ffe);
-	mtspr(SPRN_DBAT1L, 0xf800002a);
-	mb();
-}
-
-void __init
-platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
-	      unsigned long r6, unsigned long r7)
-{
-	parse_bootinfo(find_bootinfo());
-
-	/* Map in board regs, etc. */
-	spruce_set_bat();
-
-	isa_io_base = SPRUCE_ISA_IO_BASE;
-	pci_dram_offset = SPRUCE_PCI_SYS_MEM_BASE;
-
-	ppc_md.setup_arch = spruce_setup_arch;
-	ppc_md.show_cpuinfo = spruce_show_cpuinfo;
-	ppc_md.init_IRQ = cpc700_init_IRQ;
-	ppc_md.get_irq = cpc700_get_irq;
-
-	ppc_md.setup_io_mappings = spruce_map_io;
-
-	ppc_md.restart = spruce_restart;
-	ppc_md.power_off = spruce_power_off;
-	ppc_md.halt = spruce_halt;
-
-	ppc_md.time_init = todc_time_init;
-	ppc_md.set_rtc_time = todc_set_rtc_time;
-	ppc_md.get_rtc_time = todc_get_rtc_time;
-	ppc_md.calibrate_decr = spruce_calibrate_decr;
-
-	ppc_md.nvram_read_val = todc_direct_read_val;
-	ppc_md.nvram_write_val = todc_direct_write_val;
-
-	spruce_early_serial_map();
-
-#ifdef CONFIG_SERIAL_TEXT_DEBUG
-	ppc_md.progress = gen550_progress;
-#endif /* CONFIG_SERIAL_TEXT_DEBUG */
-#ifdef CONFIG_KGDB
-	ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
-#endif
-}
diff --git a/arch/ppc/platforms/spruce.h b/arch/ppc/platforms/spruce.h
deleted file mode 100644
index f1f96f1de72..00000000000
--- a/arch/ppc/platforms/spruce.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * arch/ppc/platforms/spruce.h
- *
- * Definitions for IBM Spruce reference board support
- *
- * Authors: Matt Porter and Johnnie Peters
- *          mporter@mvista.com
- *          jpeters@mvista.com
- *
- * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_SPRUCE_H__
-#define __ASM_SPRUCE_H__
-
-#define SPRUCE_PCI_CONFIG_ADDR	0xfec00000
-#define SPRUCE_PCI_CONFIG_DATA	0xfec00004
-
-#define SPRUCE_PCI_PHY_IO_BASE	0xf8000000
-#define SPRUCE_PCI_IO_BASE	SPRUCE_PCI_PHY_IO_BASE
-
-#define SPRUCE_PCI_SYS_MEM_BASE	0x00000000
-
-#define SPRUCE_PCI_LOWER_MEM	0x80000000
-#define SPRUCE_PCI_UPPER_MEM	0x9fffffff
-#define SPRUCE_PCI_LOWER_IO	0x00000000
-#define SPRUCE_PCI_UPPER_IO	0x03ffffff
-
-#define	SPRUCE_ISA_IO_BASE	SPRUCE_PCI_IO_BASE
-
-#define SPRUCE_MEM_SIZE		0x04000000
-#define SPRUCE_BUS_SPEED	66666667
-
-#define SPRUCE_NVRAM_BASE_ADDR	0xff800000
-#define SPRUCE_RTC_BASE_ADDR	SPRUCE_NVRAM_BASE_ADDR
-
-/*
- * Serial port defines
- */
-#define SPRUCE_FPGA_REG_A	0xff820000
-#define SPRUCE_UARTCLK_33M	0x02
-#define SPRUCE_UARTCLK_IS_33M(reg)	(reg & SPRUCE_UARTCLK_33M)
-
-#define UART0_IO_BASE	0xff600300
-#define UART1_IO_BASE	0xff600400
-
-#define RS_TABLE_SIZE	2
-
-#define SPRUCE_BAUD_33M	(33000000/64)
-#define SPRUCE_BAUD_30M	(30000000/64)
-#define BASE_BAUD	SPRUCE_BAUD_33M
-
-#define UART0_INT	3
-#define UART1_INT	4
-
-#define STD_UART_OP(num)						\
-	{ 0, BASE_BAUD, 0, UART##num##_INT,				\
-		ASYNC_BOOT_AUTOCONF,					\
-		iomem_base: (unsigned char *) UART##num##_IO_BASE,	\
-		io_type: SERIAL_IO_MEM},
-
-#define SERIAL_PORT_DFNS	\
-	STD_UART_OP(0)		\
-	STD_UART_OP(1)
-
-#endif /* __ASM_SPRUCE_H__ */
-#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/tqm8260.h b/arch/ppc/platforms/tqm8260.h
deleted file mode 100644
index 7f8c9a6928f..00000000000
--- a/arch/ppc/platforms/tqm8260.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * TQM8260 board specific definitions
- *
- * Copyright (c) 2001 Wolfgang Denk (wd@denx.de)
- */
-
-#ifndef __TQM8260_PLATFORM
-#define __TQM8260_PLATFORM
-
-
-#include <asm/ppcboot.h>
-
-#define CPM_MAP_ADDR		((uint)0xFFF00000)
-#define PHY_INTERRUPT		25
-
-/* For our show_cpuinfo hooks. */
-#define CPUINFO_VENDOR		"IN2 Systems"
-#define CPUINFO_MACHINE		"TQM8260 PowerPC"
-
-#define BOOTROM_RESTART_ADDR	((uint)0x40000104)
-
-#endif	/* __TQM8260_PLATFORM */
diff --git a/arch/ppc/platforms/tqm8260_setup.c b/arch/ppc/platforms/tqm8260_setup.c
deleted file mode 100644
index b766339f44a..00000000000
--- a/arch/ppc/platforms/tqm8260_setup.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * TQM8260 platform support
- *
- * Author: Allen Curtis <acurtis@onz.com>
- * Derived from: m8260_setup.c by Dan Malek, MVista
- *
- * Copyright 2002 Ones and Zeros, Inc.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#include <linux/init.h>
-
-#include <asm/mpc8260.h>
-#include <asm/cpm2.h>
-#include <asm/machdep.h>
-
-static int
-tqm8260_set_rtc_time(unsigned long time)
-{
-	((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt = time;
-	((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcntsc = 0x3;
-
-	return(0);
-}
-
-static unsigned long
-tqm8260_get_rtc_time(void)
-{
-	return ((cpm2_map_t *)CPM_MAP_ADDR)->im_sit.sit_tmcnt;
-}
-
-void __init
-m82xx_board_init(void)
-{
-	/* Anything special for this platform */
-	ppc_md.set_rtc_time	= tqm8260_set_rtc_time;
-	ppc_md.get_rtc_time	= tqm8260_get_rtc_time;
-}
diff --git a/arch/ppc/platforms/tqm8xx.h b/arch/ppc/platforms/tqm8xx.h
deleted file mode 100644
index 662131d0eb3..00000000000
--- a/arch/ppc/platforms/tqm8xx.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * TQM8xx(L) board specific definitions
- *
- * Copyright (c) 1999-2002 Wolfgang Denk (wd@denx.de)
- */
-
-#ifdef __KERNEL__
-#ifndef __MACH_TQM8xx_H
-#define __MACH_TQM8xx_H
-
-
-#include <asm/ppcboot.h>
-
-#ifndef __ASSEMBLY__
-#define	TQM_IMMR_BASE	0xFFF00000	/* phys. addr of IMMR */
-#define	TQM_IMAP_SIZE	(64 * 1024)	/* size of mapped area */
-
-#define	IMAP_ADDR	TQM_IMMR_BASE	/* physical base address of IMMR area */
-#define IMAP_SIZE	TQM_IMAP_SIZE	/* mapped size of IMMR area */
-
-/*-----------------------------------------------------------------------
- * PCMCIA stuff
- *-----------------------------------------------------------------------
- *
- */
-#define PCMCIA_MEM_SIZE		( 64 << 20 )
-
-#ifndef CONFIG_KUP4K
-# define	MAX_HWIFS	1	/* overwrite default in include/asm-ppc/ide.h	*/
-
-#else	/* CONFIG_KUP4K */
-
-# define	MAX_HWIFS	2	/* overwrite default in include/asm-ppc/ide.h	*/
-# ifndef __ASSEMBLY__
-# include <asm/8xx_immap.h>
-static __inline__ void ide_led(int on)
-{
-	volatile immap_t	*immap = (immap_t *)IMAP_ADDR;
-
-	if (on) {
-		immap->im_ioport.iop_padat &= ~0x80;
-	} else {
-		immap->im_ioport.iop_padat |= 0x80;
-	}
-}
-# endif	/* __ASSEMBLY__ */
-# define IDE_LED(x) ide_led((x))
-#endif	/* CONFIG_KUP4K */
-
-/*
- * Definitions for IDE0 Interface
- */
-#define IDE0_BASE_OFFSET		0
-#define IDE0_DATA_REG_OFFSET		(PCMCIA_MEM_SIZE + 0x320)
-#define IDE0_ERROR_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 1)
-#define IDE0_NSECTOR_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 2)
-#define IDE0_SECTOR_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 3)
-#define IDE0_LCYL_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 4)
-#define IDE0_HCYL_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 5)
-#define IDE0_SELECT_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 6)
-#define IDE0_STATUS_REG_OFFSET		(2 * PCMCIA_MEM_SIZE + 0x320 + 7)
-#define IDE0_CONTROL_REG_OFFSET		0x0106
-#define IDE0_IRQ_REG_OFFSET		0x000A	/* not used */
-
-/* define IO_BASE for PCMCIA */
-#define _IO_BASE 0x80000000
-#define _IO_BASE_SIZE  (64<<10)
-
-#define	FEC_INTERRUPT		 9	/* = SIU_LEVEL4			*/
-#define PHY_INTERRUPT		12	/* = IRQ6			*/
-#define	IDE0_INTERRUPT		13
-
-#ifdef CONFIG_IDE
-#endif
-
-/*-----------------------------------------------------------------------
- * CPM Ethernet through SCCx.
- *-----------------------------------------------------------------------
- *
- */
-
-/***  TQM823L, TQM850L  ***********************************************/
-
-#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L)
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
-#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
-#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
-#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
-
-#define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
-
-#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
-#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK	((uint)0x0000ff00)
-#define SICR_ENET_CLKRT	((uint)0x00002600)
-#endif	/* CONFIG_TQM823L, CONFIG_TQM850L */
-
-/***  TQM860L  ********************************************************/
-
-#ifdef CONFIG_TQM860L
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
-#define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
-#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
-#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
-
-#define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
-#define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
-#define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
-
-/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
- * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
- */
-#define SICR_ENET_MASK	((uint)0x000000ff)
-#define SICR_ENET_CLKRT	((uint)0x00000026)
-#endif	/* CONFIG_TQM860L */
-
-/***  FPS850L  *********************************************************/
-
-#ifdef CONFIG_FPS850L
-/* Bits in parallel I/O port registers that have to be set/cleared
- * to configure the pins for SCC1 use.
- */
-#define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
-#define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
-#define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
-#define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
-
-#define PC_ENET_TENA	((ushort)0x0002)	/* PC 14 */
-#define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
-#define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
-
-/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
- * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
- */
-#define SICR_ENET_MASK	((uint)0x0000ff00)
-#define SICR_ENET_CLKRT	((uint)0x00002600)
-#endif	/* CONFIG_FPS850L */
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS	0
-
-#endif /* !__ASSEMBLY__ */
-#endif	/* __MACH_TQM8xx_H */
-#endif /* __KERNEL__ */