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| author | James Morris <jmorris@namei.org> | 2009-06-19 08:20:55 +1000 |
|---|---|---|
| committer | James Morris <jmorris@namei.org> | 2009-06-19 08:20:55 +1000 |
| commit | d905163c5b23f6d8511971e06081a1b525e8a0bd (patch) | |
| tree | f76918c1be802ec068d37763466f5518efdb690e /arch/sh/Kconfig.cpu | |
| parent | 44c2d9bdd7022ca7d240d5adc009296fc1c6ce08 (diff) | |
| parent | 0732f87761dbe417cb6e084b712d07e879e876ef (diff) | |
Merge branch 'master' into next
Diffstat (limited to 'arch/sh/Kconfig.cpu')
| -rw-r--r-- | arch/sh/Kconfig.cpu | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu index c7d704381a6..cd6e3ea598d 100644 --- a/arch/sh/Kconfig.cpu +++ b/arch/sh/Kconfig.cpu @@ -76,11 +76,6 @@ config SPECULATIVE_EXECUTION If unsure, say N. -config SH64_USER_MISALIGNED_FIXUP - def_bool y - prompt "Fixup misaligned loads/stores occurring in user mode" - depends on SUPERH64 - config SH64_ID2815_WORKAROUND bool "Include workaround for SH5-101 cut2 silicon defect ID2815" depends on CPU_SUBTYPE_SH5_101 @@ -101,9 +96,6 @@ config CPU_HAS_SR_RB See <file:Documentation/sh/register-banks.txt> for further information on SR.RB and register banking in the kernel in general. -config CPU_HAS_PTEA - bool - config CPU_HAS_PTEAEX bool |