diff options
| author | Takashi Yoshii <yoshii.takashi@renesas.com> | 2009-04-02 09:03:30 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-04-04 11:50:52 -0400 |
| commit | 68b42d1b548be1840aff7122fdebeb804daf0fa3 (patch) | |
| tree | b971d30d186a197eeabc18c150eee0496c4614ff /arch/sh/drivers/pci/ops-sh7785lcr.c | |
| parent | 01ab10393c510342ec4ce85df11ccfa3df06bbb2 (diff) | |
sh: sh7785lcr: Map whole PCI address space.
PCI still doesn't work on sh7785lcr 29bit 256M map mode.
On SH7785, PCI -> SHwy address translation is not base+offset but
somewhat like base|offset (See HW Manual (rej09b0261) Fig. 13.11).
So, you can't export CS2,3,4,5 by 256M at CS2 (results CS0,1,2,3
exported, I guess). There are two candidates.
a) 128M@CS2 + 128M@CS4
b) 512M@CS0
Attached patch is B. It maps 512M Byte at 0 independently of memory
size. It results CS0 to CS6 and perhaps some more being accessible
from PCI.
Tested on
7785lcr 29bit 128M map
7785lcr 29bit 256M map
(NOT tested on 32bit)
Signed-off-by: Takashi YOSHII <yoshii.takashi@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/ops-sh7785lcr.c')
| -rw-r--r-- | arch/sh/drivers/pci/ops-sh7785lcr.c | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/sh/drivers/pci/ops-sh7785lcr.c b/arch/sh/drivers/pci/ops-sh7785lcr.c index b3bd6870205..e8b7446a7c2 100644 --- a/arch/sh/drivers/pci/ops-sh7785lcr.c +++ b/arch/sh/drivers/pci/ops-sh7785lcr.c @@ -48,13 +48,8 @@ EXPORT_SYMBOL(board_pci_channels); static struct sh4_pci_address_map sh7785_pci_map = { .window0 = { - .base = SH7780_CS2_BASE_ADDR, - .size = 0x04000000, - }, - - .window1 = { - .base = SH7780_CS3_BASE_ADDR, - .size = 0x04000000, + .base = SH7780_CS0_BASE_ADDR, + .size = 0x20000000, }, .flags = SH4_PCIC_NO_RESET, |