diff options
| author | Matt Fleming <matt@console-pimps.org> | 2009-12-13 14:38:50 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-12-17 14:31:20 +0900 |
| commit | 5d9b4b19f118abfb75e352841f7bf74580d7e427 (patch) | |
| tree | 5b9d0ec51bd12165d842d1d8a208e7568971757b /arch/sh/include/asm/pgalloc.h | |
| parent | b73c806341cfc7492ede6a2ce713cb579547d0ab (diff) | |
sh: Definitions for 3-level page table layout
If using 64-bit PTEs and 4K pages then each page table has 512 entries
(as opposed to 1024 entries with 32-bit PTEs). Unlike MIPS, SH follows
the convention that all structures in the page table (pgd_t, pmd_t,
pgprot_t, etc) must be the same size. Therefore, 64-bit PTEs require
64-bit PGD entries, etc. Using 2-levels of page tables and 64-bit PTEs
it is only possible to map 1GB of virtual address space.
In order to map all 4GB of virtual address space we need to adopt a
3-level page table layout. This actually works out better for
CONFIG_SUPERH32 because we only waste 2 PGD entries on the P1 and P2
areas (which are untranslated) instead of 256.
Signed-off-by: Matt Fleming <matt@console-pimps.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/asm/pgalloc.h')
| -rw-r--r-- | arch/sh/include/asm/pgalloc.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sh/include/asm/pgalloc.h b/arch/sh/include/asm/pgalloc.h index fe9f037ac5f..4ea27855c3b 100644 --- a/arch/sh/include/asm/pgalloc.h +++ b/arch/sh/include/asm/pgalloc.h @@ -6,7 +6,11 @@ #define QUICK_PT 1 /* Other page table pages that are zero on free */ +#ifdef CONFIG_PGTABLE_LEVELS_3 +#include <asm/pgalloc_pmd.h> +#else #include <asm/pgalloc_nopmd.h> +#endif static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte) |