diff options
| author | Yoshinori Sato <ysato@users.sourceforge.jp> | 2008-08-04 16:33:47 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-08-04 16:33:47 +0900 |
| commit | cce2d453e4940d3fccd42a6917d01027148e11c3 (patch) | |
| tree | bf921bfd41e4a40e513a1994d474e03f44089c0e /arch/sh/include/cpu-sh2/cpu/cache.h | |
| parent | 1af446edfe3239b2b731f3458b3c285c397464cc (diff) | |
SH2(A) cache update
Includes:
- SH2 (7619) Writeback support.
- SH2A cache handling fix.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh2/cpu/cache.h')
| -rw-r--r-- | arch/sh/include/cpu-sh2/cpu/cache.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/sh/include/cpu-sh2/cpu/cache.h b/arch/sh/include/cpu-sh2/cpu/cache.h index 4e0b1650068..673515bc413 100644 --- a/arch/sh/include/cpu-sh2/cpu/cache.h +++ b/arch/sh/include/cpu-sh2/cpu/cache.h @@ -21,11 +21,11 @@ #define CCR 0xffffffec #define CCR_CACHE_CE 0x01 /* Cache enable */ -#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */ +#define CCR_CACHE_WT 0x02 /* CCR[bit1=1,bit2=1] */ /* 0x00000000-0x7fffffff: Write-through */ /* 0x80000000-0x9fffffff: Write-back */ /* 0xc0000000-0xdfffffff: Write-through */ -#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */ +#define CCR_CACHE_CB 0x04 /* CCR[bit1=0,bit2=0] */ /* 0x00000000-0x7fffffff: Write-back */ /* 0x80000000-0x9fffffff: Write-through */ /* 0xc0000000-0xdfffffff: Write-back */ @@ -36,6 +36,8 @@ #define CCR_CACHE_ENABLE CCR_CACHE_CE #define CCR_CACHE_INVALIDATE CCR_CACHE_CF +#define CACHE_PHYSADDR_MASK 0x1ffffc00 + #endif #endif /* __ASM_CPU_SH2_CACHE_H */ |