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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2008-08-07 09:55:03 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-08-07 09:55:03 +0100 |
| commit | 4fb8af10d0fd09372d52966b76922b9e82bbc950 (patch) | |
| tree | d240e4d40357583e3f3eb228dccf20122a5b31ed /arch/sh/include/cpu-sh3/cpu/cache.h | |
| parent | f44f82e8a20b98558486eb14497b2f71c78fa325 (diff) | |
| parent | 64a99d2a8c3ed5c4e39f3ae1cc682aa8fd3977fc (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild-fixes
Diffstat (limited to 'arch/sh/include/cpu-sh3/cpu/cache.h')
| -rw-r--r-- | arch/sh/include/cpu-sh3/cpu/cache.h | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh3/cpu/cache.h b/arch/sh/include/cpu-sh3/cpu/cache.h new file mode 100644 index 00000000000..bee2d81c56b --- /dev/null +++ b/arch/sh/include/cpu-sh3/cpu/cache.h @@ -0,0 +1,43 @@ +/* + * include/asm-sh/cpu-sh3/cache.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_CACHE_H +#define __ASM_CPU_SH3_CACHE_H + +#define L1_CACHE_SHIFT 4 + +#define SH_CACHE_VALID 1 +#define SH_CACHE_UPDATED 2 +#define SH_CACHE_COMBINED 4 +#define SH_CACHE_ASSOC 8 + +#define CCR 0xffffffec /* Address of Cache Control Register */ + +#define CCR_CACHE_CE 0x01 /* Cache Enable */ +#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ +#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */ +#define CCR_CACHE_CF 0x08 /* Cache Flush */ +#define CCR_CACHE_ORA 0x20 /* RAM mode */ + +#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 +#define CACHE_PHYSADDR_MASK 0x1ffffc00 + +#define CCR_CACHE_ENABLE CCR_CACHE_CE +#define CCR_CACHE_INVALIDATE CCR_CACHE_CF + +#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7710) || \ + defined(CONFIG_CPU_SUBTYPE_SH7720) || \ + defined(CONFIG_CPU_SUBTYPE_SH7721) +#define CCR3_REG 0xa40000b4 +#define CCR_CACHE_16KB 0x00010000 +#define CCR_CACHE_32KB 0x00020000 +#endif + +#endif /* __ASM_CPU_SH3_CACHE_H */ |