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authorIngo Molnar <mingo@elte.hu>2008-10-13 11:05:51 +0200
committerIngo Molnar <mingo@elte.hu>2008-10-13 11:05:51 +0200
commitaccba5f3965d6a9d1bf7c1e1a7995d17e9d521b6 (patch)
tree8fb40782e79472ed882ff2098d4dd295557278ee /arch/sh/include/cpu-sh4/cpu/fpu.h
parent6852fd9b86d05063c6ef49d2e12e061cc7f6a105 (diff)
parent4480f15b3306f43bbb0310d461142b4e897ca45b (diff)
Merge branch 'linus' into oprofile-v2
Conflicts: arch/x86/kernel/apic_32.c arch/x86/oprofile/nmi_int.c include/linux/pci_ids.h
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu/fpu.h')
-rw-r--r--arch/sh/include/cpu-sh4/cpu/fpu.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/fpu.h b/arch/sh/include/cpu-sh4/cpu/fpu.h
new file mode 100644
index 00000000000..febef734252
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/fpu.h
@@ -0,0 +1,32 @@
+/*
+ * linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h
+ *
+ * Copyright (C) 2006 STMicroelectronics Limited
+ * Author: Carl Shaw <carl.shaw@st.com>
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License Version 2. See linux/COPYING for more information.
+ *
+ * Definitions for SH4 FPU operations
+ */
+
+#ifndef __CPU_SH4_FPU_H
+#define __CPU_SH4_FPU_H
+
+#define FPSCR_ENABLE_MASK 0x00000f80UL
+
+#define FPSCR_FMOV_DOUBLE (1<<1)
+
+#define FPSCR_CAUSE_INEXACT (1<<12)
+#define FPSCR_CAUSE_UNDERFLOW (1<<13)
+#define FPSCR_CAUSE_OVERFLOW (1<<14)
+#define FPSCR_CAUSE_DIVZERO (1<<15)
+#define FPSCR_CAUSE_INVALID (1<<16)
+#define FPSCR_CAUSE_ERROR (1<<17)
+
+#define FPSCR_DBL_PRECISION (1<<19)
+#define FPSCR_ROUNDING_MODE(x) ((x >> 20) & 3)
+#define FPSCR_RM_NEAREST (0)
+#define FPSCR_RM_ZERO (1)
+
+#endif