diff options
| author | Magnus Damm <damm@igel.co.jp> | 2009-06-03 08:18:56 +0000 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2009-06-11 09:09:19 +0300 |
| commit | ed740cb9b7f6eaee7bb45a07ce53ff9e73a92798 (patch) | |
| tree | 9fc54e73a4005fb395c3db48376ab89fc5ebf2fb /arch/sh/include/cpu-sh4/cpu/sh7722.h | |
| parent | 36e5b26bdac0ee3791071d240334853ddd7b9790 (diff) | |
sh: sh7722 mode pin definitions
This patch adds sh7722 mode pin and pin function
controller comments.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu/sh7722.h')
| -rw-r--r-- | arch/sh/include/cpu-sh4/cpu/sh7722.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7722.h b/arch/sh/include/cpu-sh4/cpu/sh7722.h index 4b3096f5307..738ea43c503 100644 --- a/arch/sh/include/cpu-sh4/cpu/sh7722.h +++ b/arch/sh/include/cpu-sh4/cpu/sh7722.h @@ -1,6 +1,20 @@ #ifndef __ASM_SH7722_H__ #define __ASM_SH7722_H__ +/* Boot Mode Pins: + * + * MD0: CPG - Clock Mode 0->3 + * MD1: CPG - Clock Mode 0->3 + * MD2: CPG - Reserved (L: Normal operation) + * MD3: BSC - Area0 Bus Width (16/32-bit) [CS0BCR.9,10] + * MD5: BSC - Endian Mode (L: Big, H: Little) [CMNCR.3] + * MD8: Test Mode + */ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_Pxx - GPIO mapped to real I/O pin on CPU + */ enum { /* PTA */ GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4, |