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authorIngo Molnar <mingo@kernel.org>2014-03-11 11:53:50 +0100
committerIngo Molnar <mingo@kernel.org>2014-03-11 11:53:50 +0100
commit0066f3b93e144762b409940fa37bb1cd36c1baf7 (patch)
tree0c99b2754fb16c2a787bc1d086bd6fb268b12b1a /arch/sh/include/cpu-sh4/cpu
parente65312fe868da53077780de618e213a53dc90d00 (diff)
parentb8ad0f912b93c23c34dfedc615a0eeba6ca29463 (diff)
Merge branch 'perf/urgent' into perf/core
Merge the latest fixes. Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/sh/include/cpu-sh4/cpu')
-rw-r--r--arch/sh/include/cpu-sh4/cpu/cache.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sh/include/cpu-sh4/cpu/cache.h b/arch/sh/include/cpu-sh4/cpu/cache.h
index 7bfb9e8b069..92c4cd119b6 100644
--- a/arch/sh/include/cpu-sh4/cpu/cache.h
+++ b/arch/sh/include/cpu-sh4/cpu/cache.h
@@ -17,7 +17,7 @@
#define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8
-#define CCR 0xff00001c /* Address of Cache Control Register */
+#define SH_CCR 0xff00001c /* Address of Cache Control Register */
#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */