diff options
| author | Yoshinori Sato <ysato@users.sourceforge.jp> | 2006-11-05 15:40:13 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2006-12-06 10:45:36 +0900 |
| commit | 9d4436a6fbc8c5eccdfcb8f5884e0a7b4a57f6d2 (patch) | |
| tree | a8b7532fffa76ae526dea547cc87200466e00842 /arch/sh/kernel/cpu/init.c | |
| parent | e62438630ca37539c8cc1553710bbfaa3cf960a7 (diff) | |
sh: Add support for SH7206 and SH7619 CPU subtypes.
This implements initial support for the SH7206 (SH-2A) and SH7619
(SH-2) MMU-less CPUs.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/init.c')
| -rw-r--r-- | arch/sh/kernel/cpu/init.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c index bfb90eb0b7a..48121766e8d 100644 --- a/arch/sh/kernel/cpu/init.c +++ b/arch/sh/kernel/cpu/init.c @@ -68,12 +68,14 @@ static void __init cache_init(void) waysize = cpu_data->dcache.sets; +#ifdef CCR_CACHE_ORA /* * If the OC is already in RAM mode, we only have * half of the entries to flush.. */ if (ccr & CCR_CACHE_ORA) waysize >>= 1; +#endif waysize <<= cpu_data->dcache.entry_shift; |