diff options
| author | Paul Mundt <lethal@linux-sh.org> | 2010-10-13 07:17:03 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2010-10-13 07:17:03 +0900 |
| commit | 5e5b3a9dc8405f6a49531a02754a6cc2a1c6cd28 (patch) | |
| tree | 424cc279f568fe669857fd8983af94f636953e08 /arch/sh/kernel/cpu/sh4a | |
| parent | ace2dc7d12693545b67f15ab8cdb3d255c937713 (diff) | |
sh: perf: Support SH-X3 hardware counters.
The PMCAT location has conveniently moved on newer SH-X3 parts, special
case this for now with a note. This will probably want to be redone in a
less visually offensive way when/if more information becomes available.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/kernel/cpu/sh4a')
| -rw-r--r-- | arch/sh/kernel/cpu/sh4a/perf_event.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/perf_event.c b/arch/sh/kernel/cpu/sh4a/perf_event.c index eddc21973fa..b8b873d8d6b 100644 --- a/arch/sh/kernel/cpu/sh4a/perf_event.c +++ b/arch/sh/kernel/cpu/sh4a/perf_event.c @@ -1,7 +1,7 @@ /* * Performance events support for SH-4A performance counters * - * Copyright (C) 2009 Paul Mundt + * Copyright (C) 2009, 2010 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive @@ -22,7 +22,25 @@ #define CCBR_CMDS (1 << 1) #define CCBR_PPCE (1 << 0) +#ifdef CONFIG_CPU_SHX3 +/* + * The PMCAT location for SH-X3 CPUs was quietly moved, while the CCBR + * and PMCTR locations remains tentatively constant. This change remains + * wholly undocumented, and was simply found through trial and error. + * + * Early cuts of SH-X3 still appear to use the SH-X/SH-X2 locations, and + * it's unclear when this ceased to be the case. For now we always use + * the new location (if future parts keep up with this trend then + * scanning for them at runtime also remains a viable option.) + * + * The gap in the register space also suggests that there are other + * undocumented counters, so this will need to be revisited at a later + * point in time. + */ +#define PPC_PMCAT 0xfc100240 +#else #define PPC_PMCAT 0xfc100080 +#endif #define PMCAT_OVF3 (1 << 27) #define PMCAT_CNN3 (1 << 26) |