sh: Get SH-5 caches working again post-unification.

A number of cleanups to get the SH-5 cache management code in line with
the rest of the SH backend.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

1 files changed, 28 insertions, 33 deletions

diff --git a/arch/sh/kernel/cpu/sh5/probe.c b/arch/sh/kernel/cpu/sh5/probe.c
index 15d167fd0ae..31f8cb0f637 100644
--- a/arch/sh/kernel/cpu/sh5/probe.c
+++ b/arch/sh/kernel/cpu/sh5/probe.c
@@ -20,19 +20,18 @@ int __init detect_cpu_and_cache_system(void)
 {
 	unsigned long long cir;
 
-	/* Do peeks in real mode to avoid having to set up a mapping for the
-	   WPC registers. On SH5-101 cut2, such a mapping would be exposed to
-	   an address translation erratum which would make it hard to set up
-	   correctly. */
+	/*
+	 * Do peeks in real mode to avoid having to set up a mapping for
+	 * the WPC registers. On SH5-101 cut2, such a mapping would be
+	 * exposed to an address translation erratum which would make it
+	 * hard to set up correctly.
+	 */
 	cir = peek_real_address_q(0x0d000008);
-	if ((cir & 0xffff) == 0x5103) {
+	if ((cir & 0xffff) == 0x5103)
 		boot_cpu_data.type = CPU_SH5_103;
-	} else if (((cir >> 32) & 0xffff) == 0x51e2) {
+	else if (((cir >> 32) & 0xffff) == 0x51e2)
 		/* CPU.VCR aliased at CIR address on SH5-101 */
 		boot_cpu_data.type = CPU_SH5_101;
-	} else {
-		boot_cpu_data.type = CPU_SH_NONE;
-	}
 
 	/*
 	 * First, setup some sane values for the I-cache.
@@ -40,37 +39,33 @@ int __init detect_cpu_and_cache_system(void)
 	boot_cpu_data.icache.ways		= 4;
 	boot_cpu_data.icache.sets		= 256;
 	boot_cpu_data.icache.linesz		= L1_CACHE_BYTES;
+	boot_cpu_data.icache.way_incr		= (1 << 13);
+	boot_cpu_data.icache.entry_shift	= 5;
+	boot_cpu_data.icache.way_size		= boot_cpu_data.icache.sets *
+						  boot_cpu_data.icache.linesz;
+	boot_cpu_data.icache.entry_mask		= 0x1fe0;
+	boot_cpu_data.icache.flags		= 0;
 
-#if 0
 	/*
-	 * FIXME: This can probably be cleaned up a bit as well.. for example,
-	 * do we really need the way shift _and_ the way_step_shift ?? Judging
-	 * by the existing code, I would guess no.. is there any valid reason
-	 * why we need to be tracking this around?
+	 * Next, setup some sane values for the D-cache.
+	 *
+	 * On the SH5, these are pretty consistent with the I-cache settings,
+	 * so we just copy over the existing definitions.. these can be fixed
+	 * up later, especially if we add runtime CPU probing.
+	 *
+	 * Though in the meantime it saves us from having to duplicate all of
+	 * the above definitions..
 	 */
-	boot_cpu_data.icache.way_shift		= 13;
-	boot_cpu_data.icache.entry_shift	= 5;
-	boot_cpu_data.icache.set_shift		= 4;
-	boot_cpu_data.icache.way_step_shift	= 16;
-	boot_cpu_data.icache.asid_shift		= 2;
+	boot_cpu_data.dcache		= boot_cpu_data.icache;
 
 	/*
-	 * way offset = cache size / associativity, so just don't factor in
-	 * associativity in the first place..
+	 * Setup any cache-related flags here
 	 */
-	boot_cpu_data.icache.way_ofs	= boot_cpu_data.icache.sets *
-					  boot_cpu_data.icache.linesz;
-
-	boot_cpu_data.icache.asid_mask		= 0x3fc;
-	boot_cpu_data.icache.idx_mask		= 0x1fe0;
-	boot_cpu_data.icache.epn_mask		= 0xffffe000;
+#if defined(CONFIG_CACHE_WRITETHROUGH)
+	set_bit(SH_CACHE_MODE_WT, &(boot_cpu_data.dcache.flags));
+#elif defined(CONFIG_CACHE_WRITEBACK)
+	set_bit(SH_CACHE_MODE_WB, &(boot_cpu_data.dcache.flags));
 #endif
 
-	boot_cpu_data.icache.flags		= 0;
-
-	/* A trivial starting point.. */
-	memcpy(&boot_cpu_data.dcache,
-	       &boot_cpu_data.icache, sizeof(struct cache_info));
-
 	return 0;
 }