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authorLen Brown <len.brown@intel.com>2011-03-23 02:33:54 -0400
committerLen Brown <len.brown@intel.com>2011-03-23 02:33:54 -0400
commit5c129a8600100a5d0f5fdbc1014c5dba1d307bc4 (patch)
tree9877a14b49cff43d0ba10c12f407ec551c77daa5 /arch/sh/lib/delay.c
parent797b10a07069e153d41aedb4ae8e76660279e2ee (diff)
parent521cb40b0c44418a4fd36dc633f575813d59a43d (diff)
Merge commit 'v2.6.38' into release
Diffstat (limited to 'arch/sh/lib/delay.c')
-rw-r--r--arch/sh/lib/delay.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/sh/lib/delay.c b/arch/sh/lib/delay.c
index faa8f86c0db..0901b2f14e1 100644
--- a/arch/sh/lib/delay.c
+++ b/arch/sh/lib/delay.c
@@ -10,6 +10,16 @@
void __delay(unsigned long loops)
{
__asm__ __volatile__(
+ /*
+ * ST40-300 appears to have an issue with this code,
+ * normally taking two cycles each loop, as with all
+ * other SH variants. If however the branch and the
+ * delay slot straddle an 8 byte boundary, this increases
+ * to 3 cycles.
+ * This align directive ensures this doesn't occur.
+ */
+ ".balign 8\n\t"
+
"tst %0, %0\n\t"
"1:\t"
"bf/s 1b\n\t"