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| author | Eric Anholt <eric@anholt.net> | 2009-12-01 09:01:54 -0800 |
|---|---|---|
| committer | Eric Anholt <eric@anholt.net> | 2009-12-01 09:01:54 -0800 |
| commit | f40d6817a5c2bf84f5fe7b5d1a83f1e8f8669951 (patch) | |
| tree | 1c515a34a60f65cbfd3cf1a387427d0a9fdf878f /arch/sparc/include/asm/system_64.h | |
| parent | 103a196f4224dc6872081305cf7f82ebf67aa7bd (diff) | |
| parent | 46557bef3f3834ac33031c7be27d39d90d507442 (diff) | |
Merge remote branch 'airlied/drm-next' into drm-intel-next
Diffstat (limited to 'arch/sparc/include/asm/system_64.h')
| -rw-r--r-- | arch/sparc/include/asm/system_64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h index 25e848f0cad..d47a98e6697 100644 --- a/arch/sparc/include/asm/system_64.h +++ b/arch/sparc/include/asm/system_64.h @@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ : : : "memory"); \ } while (0) +/* The kernel always executes in TSO memory model these days, + * and furthermore most sparc64 chips implement more stringent + * memory ordering than required by the specifications. + */ #define mb() membar_safe("#StoreLoad") #define rmb() __asm__ __volatile__("":::"memory") #define wmb() __asm__ __volatile__("":::"memory") |