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| author | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-04 14:59:47 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-12-04 14:59:47 +0000 |
| commit | 5cb2faa6ede7ada9cb2bffc832c4ce60f53d6834 (patch) | |
| tree | 7b72b66081d042a41dc822575503133364857ce2 /arch/sparc/include/asm/system_64.h | |
| parent | e0ee98513d1a2e24d2ddbdecf4216bcca29d1158 (diff) | |
| parent | 6060e8df517847bf445ebc61de7d4d9c7faae990 (diff) | |
Merge branch 'pending-misc' (early part) into devel
Diffstat (limited to 'arch/sparc/include/asm/system_64.h')
| -rw-r--r-- | arch/sparc/include/asm/system_64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h index 25e848f0cad..d47a98e6697 100644 --- a/arch/sparc/include/asm/system_64.h +++ b/arch/sparc/include/asm/system_64.h @@ -63,6 +63,10 @@ do { __asm__ __volatile__("ba,pt %%xcc, 1f\n\t" \ : : : "memory"); \ } while (0) +/* The kernel always executes in TSO memory model these days, + * and furthermore most sparc64 chips implement more stringent + * memory ordering than required by the specifications. + */ #define mb() membar_safe("#StoreLoad") #define rmb() __asm__ __volatile__("":::"memory") #define wmb() __asm__ __volatile__("":::"memory") |