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authorIngo Molnar <mingo@kernel.org>2013-07-01 11:16:54 +0200
committerIngo Molnar <mingo@kernel.org>2013-07-01 11:18:53 +0200
commit2fd1b487884310d0aa0c0640179dc7490ad86313 (patch)
tree1083dce15bd7dc0858c3883b8a361242046c5e09 /arch/sparc/kernel/leon_pmc.c
parent333bb864f192015a53b5060b829089decd0220ef (diff)
parent8bb495e3f02401ee6f76d1b1d77f3ac9f079e376 (diff)
Merge tag 'v3.10' into sched/core
Merge in a recent upstream commit: c2853c8df57f include/linux/math64.h: add div64_ul() because: 72a4cf20cb71 sched: Change cfs_rq load avg to unsigned long relies on it. [ We don't rebase sched/core for this, because the handful of followup commits after the broken commit are not behavioral changes so are unlikely to be needed during bisection. ] Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/sparc/kernel/leon_pmc.c')
-rw-r--r--arch/sparc/kernel/leon_pmc.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/sparc/kernel/leon_pmc.c b/arch/sparc/kernel/leon_pmc.c
index bdf53d9a8d4..b0b3967a2dd 100644
--- a/arch/sparc/kernel/leon_pmc.c
+++ b/arch/sparc/kernel/leon_pmc.c
@@ -47,6 +47,10 @@ void pmc_leon_idle_fixup(void)
* MMU does not get a TLB miss here by using the MMU BYPASS ASI.
*/
register unsigned int address = (unsigned int)leon3_irqctrl_regs;
+
+ /* Interrupts need to be enabled to not hang the CPU */
+ local_irq_enable();
+
__asm__ __volatile__ (
"wr %%g0, %%asr19\n"
"lda [%0] %1, %%g0\n"
@@ -60,6 +64,9 @@ void pmc_leon_idle_fixup(void)
*/
void pmc_leon_idle(void)
{
+ /* Interrupts need to be enabled to not hang the CPU */
+ local_irq_enable();
+
/* For systems without power-down, this will be no-op */
__asm__ __volatile__ ("wr %g0, %asr19\n\t");
}