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authorYinghai Lu <yinghai@kernel.org>2012-07-09 19:55:29 -0600
committerBjorn Helgaas <bhelgaas@google.com>2012-07-09 19:55:29 -0600
commitfd591341102ba5eb9e517d3889e7566fa45e021e (patch)
treee4e658bac28fe3626c9507a459d648d14a007b5e /arch/sparc/kernel/pci.c
parent2b28ae1912e5ce5bb0527e352ae6ff04e76183d1 (diff)
PCI: support sizing P2P bridge I/O windows with 1K granularity
Some bridges support I/O windows with 1K alignment, not just the 4K alignment defined by the PCI spec. For example, see the IOBL_ADR register and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2). This patch adds support for sizing the window in 1K increments based on the requirements of downstream devices. [bhelgaas: changelog, comment] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'arch/sparc/kernel/pci.c')
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