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authorDavid S. Miller <davem@sunset.davemloft.net>2006-02-02 21:55:10 -0800
committerDavid S. Miller <davem@sunset.davemloft.net>2006-03-20 01:11:35 -0800
commitffe483d55229fadbaf4cc7316d47024a24ecd1a2 (patch)
tree70bdb6c94d5b3512a7b2a3ff06979ac2e4e869bf /arch/sparc64/kernel/rtrap.S
parent92704a1c63c3b481870d02636d0b5a70c7e21cd1 (diff)
[SPARC64]: Add explicit register args to trap state loading macros.
This, as well as making the code cleaner, allows a simplification in the TSB miss handling path. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/rtrap.S')
-rw-r--r--arch/sparc64/kernel/rtrap.S2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sparc64/kernel/rtrap.S b/arch/sparc64/kernel/rtrap.S
index 64bc03610bc..61bd45e7697 100644
--- a/arch/sparc64/kernel/rtrap.S
+++ b/arch/sparc64/kernel/rtrap.S
@@ -226,7 +226,7 @@ rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
brz,pt %l3, 1f
nop
/* Must do this before thread reg is clobbered below. */
- LOAD_PER_CPU_BASE(%i0, %i1, %i2)
+ LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7