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authorDavid S. Miller <davem@sunset.davemloft.net>2005-10-04 15:23:20 -0700
committerDavid S. Miller <davem@sunset.davemloft.net>2005-10-04 15:23:20 -0700
commit0835ae0f27c0bfde67613d189ef6c537e004a6de (patch)
treead5cad209eeb11bd1bf49a3b5cffa49618c717c8 /arch/sparc64/kernel/trampoline.S
parentdd7205ed0f022a2a5e60eb7404e6c9f49d2301c3 (diff)
[SPARC64]: Replace cheetah+ code patching with variables.
Instead of code patching to handle the page size fields in the context registers, just use variables from which we get the proper values. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/trampoline.S')
-rw-r--r--arch/sparc64/kernel/trampoline.S15
1 files changed, 4 insertions, 11 deletions
diff --git a/arch/sparc64/kernel/trampoline.S b/arch/sparc64/kernel/trampoline.S
index 89f2fcfcd66..9478551cb02 100644
--- a/arch/sparc64/kernel/trampoline.S
+++ b/arch/sparc64/kernel/trampoline.S
@@ -336,20 +336,13 @@ do_unlock:
call init_irqwork_curcpu
nop
- BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g2,g3,1f)
- ba,pt %xcc, 2f
- nop
-
-1: /* Start using proper page size encodings in ctx register. */
- sethi %uhi(CTX_CHEETAH_PLUS_NUC), %g3
+ /* Start using proper page size encodings in ctx register. */
+ sethi %hi(sparc64_kern_pri_context), %g3
+ ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
mov PRIMARY_CONTEXT, %g1
- sllx %g3, 32, %g3
- sethi %hi(CTX_CHEETAH_PLUS_CTX0), %g2
- or %g3, %g2, %g3
- stxa %g3, [%g1] ASI_DMMU
+ stxa %g2, [%g1] ASI_DMMU
membar #Sync
-2:
rdpr %pstate, %o1
or %o1, PSTATE_IE, %o1
wrpr %o1, 0, %pstate