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| author | Ingo Molnar <mingo@elte.hu> | 2008-10-27 10:50:54 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-10-27 10:50:54 +0100 |
| commit | 4944dd62de21230af039eda7cd218e9a09021d11 (patch) | |
| tree | bac70f7bab8506c7e1b0408bacbdb0b1d77262e9 /arch/um/include/asm/cache.h | |
| parent | f17845e5d97ead8fbdadfd40039e058ec7cf4a42 (diff) | |
| parent | 0173a3265b228da319ceb9c1ec6a5682fd1b2d92 (diff) | |
Merge commit 'v2.6.28-rc2' into tracing/urgent
Diffstat (limited to 'arch/um/include/asm/cache.h')
| -rw-r--r-- | arch/um/include/asm/cache.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/um/include/asm/cache.h b/arch/um/include/asm/cache.h new file mode 100644 index 00000000000..19e1bdd6741 --- /dev/null +++ b/arch/um/include/asm/cache.h @@ -0,0 +1,17 @@ +#ifndef __UM_CACHE_H +#define __UM_CACHE_H + + +#if defined(CONFIG_UML_X86) && !defined(CONFIG_64BIT) +# define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT) +#elif defined(CONFIG_UML_X86) /* 64-bit */ +# define L1_CACHE_SHIFT 6 /* Should be 7 on Intel */ +#else +/* XXX: this was taken from x86, now it's completely random. Luckily only + * affects SMP padding. */ +# define L1_CACHE_SHIFT 5 +#endif + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#endif |