diff options
| author | Len Brown <len.brown@intel.com> | 2009-01-09 03:39:43 -0500 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2009-01-09 03:39:43 -0500 |
| commit | b2576e1d4408e134e2188c967b1f28af39cd79d4 (patch) | |
| tree | 004f3c82faab760f304ce031d6d2f572e7746a50 /arch/x86/include/asm/mtrr.h | |
| parent | 3cc8a5f4ba91f67bbdb81a43a99281a26aab8d77 (diff) | |
| parent | 2150edc6c5cf00f7adb54538b9ea2a3e9cedca3f (diff) | |
Merge branch 'linus' into release
Diffstat (limited to 'arch/x86/include/asm/mtrr.h')
| -rw-r--r-- | arch/x86/include/asm/mtrr.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h index 7c1e4258b31..cb988aab716 100644 --- a/arch/x86/include/asm/mtrr.h +++ b/arch/x86/include/asm/mtrr.h @@ -57,6 +57,31 @@ struct mtrr_gentry { }; #endif /* !__i386__ */ +struct mtrr_var_range { + u32 base_lo; + u32 base_hi; + u32 mask_lo; + u32 mask_hi; +}; + +/* In the Intel processor's MTRR interface, the MTRR type is always held in + an 8 bit field: */ +typedef u8 mtrr_type; + +#define MTRR_NUM_FIXED_RANGES 88 +#define MTRR_MAX_VAR_RANGES 256 + +struct mtrr_state_type { + struct mtrr_var_range var_ranges[MTRR_MAX_VAR_RANGES]; + mtrr_type fixed_ranges[MTRR_NUM_FIXED_RANGES]; + unsigned char enabled; + unsigned char have_fixed; + mtrr_type def_type; +}; + +#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) +#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) + /* These are the various ioctls */ #define MTRRIOC_ADD_ENTRY _IOW(MTRR_IOCTL_BASE, 0, struct mtrr_sentry) #define MTRRIOC_SET_ENTRY _IOW(MTRR_IOCTL_BASE, 1, struct mtrr_sentry) |