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| author | Ingo Molnar <mingo@elte.hu> | 2008-12-25 12:48:18 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-12-25 12:48:18 +0100 |
| commit | a3eeeefbf1cd1d142c52238cc19c75d14c3bc8d5 (patch) | |
| tree | 28eedba6d432e9d9d772962e6f92732aef1be065 /arch/x86/kernel/cpu/intel.c | |
| parent | 30cd324e9787ccc9a5ede59742d5409857550692 (diff) | |
| parent | 7e3cbc3f774f31ecd88a51edae3d9377f60a4c00 (diff) | |
Merge branch 'x86/tsc' into tracing/core
Merge it to resolve this incidental conflict between the BTS fixes/cleanups
and changes in x86/tsc:
Conflicts:
arch/x86/kernel/cpu/intel.c
Diffstat (limited to 'arch/x86/kernel/cpu/intel.c')
| -rw-r--r-- | arch/x86/kernel/cpu/intel.c | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index cd413d9a021..8ea6929e974 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -40,6 +40,16 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c) if (c->x86 == 15 && c->x86_cache_alignment == 64) c->x86_cache_alignment = 128; #endif + + /* + * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate + * with P/T states and does not stop in deep C-states + */ + if (c->x86_power & (1 << 8)) { + set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); + set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); + } + } #ifdef CONFIG_X86_32 @@ -241,6 +251,13 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) intel_workarounds(c); + /* + * Detect the extended topology information if available. This + * will reinitialise the initial_apicid which will be used + * in init_intel_cacheinfo() + */ + detect_extended_topology(c); + l2 = init_intel_cacheinfo(c); if (c->cpuid_level > 9) { unsigned eax = cpuid_eax(10); @@ -308,7 +325,6 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c) set_cpu_cap(c, X86_FEATURE_P3); #endif - detect_extended_topology(c); if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) { /* * let's use the legacy cpuid vector 0x1 and 0x4 for topology |