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authorRobert Richter <robert.richter@amd.com>2010-10-25 16:28:14 +0200
committerRobert Richter <robert.richter@amd.com>2010-10-25 16:29:12 +0200
commitdbd1e66e04558a582e673bc4a9cd933ce0228d93 (patch)
tree85f3633276282cde0a3ac558d988704eaa3e68af /arch/x86/kernel/cpu/scattered.c
parent328b8f1ba50b708a1b3c0acd7c41ee1b356822f6 (diff)
parent4a60cfa9457749f7987fd4f3c956dbba5a281129 (diff)
Merge commit 'linux-2.6/master' (early part) into oprofile/core
This branch depends on these apic patches: apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets apic, x86: Check if EILVT APIC registers are available (AMD only) Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86/kernel/cpu/scattered.c')
-rw-r--r--arch/x86/kernel/cpu/scattered.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
index d4907951512..c7f64e6f537 100644
--- a/arch/x86/kernel/cpu/scattered.c
+++ b/arch/x86/kernel/cpu/scattered.c
@@ -44,6 +44,12 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
{ X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a, 0 },
{ X86_FEATURE_SVML, CR_EDX, 2, 0x8000000a, 0 },
{ X86_FEATURE_NRIPS, CR_EDX, 3, 0x8000000a, 0 },
+ { X86_FEATURE_TSCRATEMSR, CR_EDX, 4, 0x8000000a, 0 },
+ { X86_FEATURE_VMCBCLEAN, CR_EDX, 5, 0x8000000a, 0 },
+ { X86_FEATURE_FLUSHBYASID, CR_EDX, 6, 0x8000000a, 0 },
+ { X86_FEATURE_DECODEASSISTS, CR_EDX, 7, 0x8000000a, 0 },
+ { X86_FEATURE_PAUSEFILTER, CR_EDX,10, 0x8000000a, 0 },
+ { X86_FEATURE_PFTHRESHOLD, CR_EDX,12, 0x8000000a, 0 },
{ 0, 0, 0, 0, 0 }
};