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authorMax Filippov <jcmvbkbc@gmail.com>2013-03-04 03:40:42 +0400
committerChris Zankel <chris@zankel.net>2013-05-09 01:07:09 -0700
commitd83ff0bb828854d9e7172ac5d8d007a7466934c9 (patch)
tree188dfa08078c116698d4673a42a38b40e75a4ccb /arch/xtensa/platforms/xtfpga
parent74f5bf029ee052e3d845672728e80b7240d14f09 (diff)
xtensa: fix ibreakenable register update
Only set the register when there is at least one ibreak register, otherwise the build fails: arch/xtensa/kernel/head.S:105: Error: invalid register 'ibreakenable' for 'wsr' instruction arch/xtensa/platforms/iss/setup.c:67: Error: invalid register 'ibreakenable' for 'wsr' instruction Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/platforms/xtfpga')
-rw-r--r--arch/xtensa/platforms/xtfpga/setup.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/xtensa/platforms/xtfpga/setup.c b/arch/xtensa/platforms/xtfpga/setup.c
index 9d888a2a575..96ef8eeb064 100644
--- a/arch/xtensa/platforms/xtfpga/setup.c
+++ b/arch/xtensa/platforms/xtfpga/setup.c
@@ -60,7 +60,9 @@ void platform_restart(void)
"wsr a2, icountlevel\n\t"
"movi a2, 0\n\t"
"wsr a2, icount\n\t"
+#if XCHAL_NUM_IBREAK > 0
"wsr a2, ibreakenable\n\t"
+#endif
"wsr a2, lcount\n\t"
"movi a2, 0x1f\n\t"
"wsr a2, ps\n\t"