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authorSuresh Siddha <suresh.b.siddha@intel.com>2011-11-04 15:42:17 -0700
committerIngo Molnar <mingo@elte.hu>2011-12-05 18:00:31 +0100
commit28a00184be261e3dc152ba0d664a067bbe235b6a (patch)
tree9c56ce8c758a244173c9b0016cac43f45609d4ed /arch/xtensa
parent8e8da023f5af71662867729db5547dc54786093c (diff)
x86, tsc: Skip TSC synchronization checks for tsc=reliable
tsc=reliable boot parameter is supposed to skip all the TSC stablility checks during boot time. On a 8-socket system where we want to run an experiment with the "tsc=reliable" boot option, TSC synchronization checks are not getting skipped and marking the TSC as not stable. Check for tsc_clocksource_reliable (which is set via tsc=reliable or for platforms supporting synthetic TSC_RELIABLE feature bit etc) and when set, skip the TSC synchronization tests during boot. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Acked-by: John Stultz <johnstul@us.ibm.com> Tested-by: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com> Link: http://lkml.kernel.org/r/1320446537.15071.14.camel@sbsiddha-desk.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/xtensa')
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