diff options
| author | Russ Anderson <rja@sgi.com> | 2007-06-14 16:01:24 -0500 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2007-06-26 13:34:16 -0700 |
| commit | c034637967881830979b5415e55578e42f806659 (patch) | |
| tree | 8485c5f219af8df274f2a73b1663c73ff8d997c0 /arch | |
| parent | eaf6c766446c0faa326b339900f975e6f1f62b01 (diff) | |
[IA64] Force error to surface in nofault code
Montecito behaves slightly differently than previous processors,
resulting in the MCA due to a failed PIO read to sometimes surfacing
outside the nofault code. Adding an additional or and stop bits
ensures the MCA surfaces in the nofault code.
Signed-off-by: Russ Anderson <rja@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/ia64/sn/kernel/xp_nofault.S | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/ia64/sn/kernel/xp_nofault.S b/arch/ia64/sn/kernel/xp_nofault.S index b772543053c..54e8973b6e9 100644 --- a/arch/ia64/sn/kernel/xp_nofault.S +++ b/arch/ia64/sn/kernel/xp_nofault.S @@ -21,7 +21,8 @@ xp_nofault_PIOR: mov r8=r0 // Stage a success return value ld8.acq r9=[r32];; // PIO Read the specified register - adds r9=1,r9 // Add to force a consume + adds r9=1,r9;; // Add to force consumption + or r9=r9,r9;; // Or to force consumption br.ret.sptk.many b0;; // Return success .global xp_error_PIOR |