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authorPeter Zijlstra <a.p.zijlstra@chello.nl>2010-03-08 13:57:14 +0100
committerIngo Molnar <mingo@elte.hu>2010-03-10 13:23:37 +0100
commitd329527e47851f84b1e7944ed9601205f35f1b93 (patch)
tree15bd3e3ca7524f160cf1b6ddc5769b38abadcc40 /arch
parent2df202bf7520eaffcbfb07e45dfa3cfb0aeee2c0 (diff)
perf, x86: Reorder intel_pmu_enable_all()
The documentation says we have to enable PEBS before we enable the PMU proper. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Arnaldo Carvalho de Melo <acme@infradead.org> Cc: paulus@samba.org Cc: eranian@google.com Cc: robert.richter@amd.com Cc: fweisbec@gmail.com LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index c135ed735b2..d3e2424069a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -487,6 +487,8 @@ static void intel_pmu_enable_all(void)
{
struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ intel_pmu_pebs_enable_all();
+ intel_pmu_lbr_enable_all();
wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
@@ -498,9 +500,6 @@ static void intel_pmu_enable_all(void)
intel_pmu_enable_bts(event->hw.config);
}
-
- intel_pmu_pebs_enable_all();
- intel_pmu_lbr_enable_all();
}
static inline u64 intel_pmu_get_status(void)