diff options
| author | Pallipadi, Venkatesh <venkatesh.pallipadi@intel.com> | 2009-05-21 17:09:10 -0700 |
|---|---|---|
| committer | Len Brown <len.brown@intel.com> | 2009-05-27 21:57:30 -0400 |
| commit | ee1ca48fae7e575d5e399d4fdcfe0afc1212a64c (patch) | |
| tree | d2d8c9bd4a806e603ba272a7f71644af1fdb16a3 /arch | |
| parent | cd86a536c81e9300d984327517548ca0652eebf9 (diff) | |
ACPI: Disable ARB_DISABLE on platforms where it is not needed
ARB_DISABLE is a NOP on all of the recent Intel platforms.
For such platforms, reduce contention on c3_lock
by skipping the fake ARB_DISABLE.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/acpi/cstate.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c index bbbe4bbb6f3..8c44c232efc 100644 --- a/arch/x86/kernel/acpi/cstate.c +++ b/arch/x86/kernel/acpi/cstate.c @@ -34,12 +34,22 @@ void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, flags->bm_check = 1; else if (c->x86_vendor == X86_VENDOR_INTEL) { /* - * Today all CPUs that support C3 share cache. - * TBD: This needs to look at cache shared map, once - * multi-core detection patch makes to the base. + * Today all MP CPUs that support C3 share cache. + * And caches should not be flushed by software while + * entering C3 type state. */ flags->bm_check = 1; } + + /* + * On all recent Intel platforms, ARB_DISABLE is a nop. + * So, set bm_control to zero to indicate that ARB_DISABLE + * is not required while entering C3 type state on + * P4, Core and beyond CPUs + */ + if (c->x86_vendor == X86_VENDOR_INTEL && + (c->x86 > 0x6 || (c->x86 == 6 && c->x86_model >= 14))) + flags->bm_control = 0; } EXPORT_SYMBOL(acpi_processor_power_init_bm_check); |