diff options
| author | Michael Hennerich <michael.hennerich@analog.com> | 2008-01-22 18:38:02 +0800 |
|---|---|---|
| committer | Bryan Wu <bryan.wu@analog.com> | 2008-01-22 18:38:02 +0800 |
| commit | 444ad82bc3eaa554be40d22dc248e58aeefd54d9 (patch) | |
| tree | 3244f4f4585847419dc28c706aec658cba6e05be /arch | |
| parent | a628a8bcd8a6daea6096fe781fc36cae4ac1ed48 (diff) | |
[Blackfin] arch: Add proper SW System Reset delay sequence
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/blackfin/kernel/reboot.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c index 06501a594dd..483f93dfc1b 100644 --- a/arch/blackfin/kernel/reboot.c +++ b/arch/blackfin/kernel/reboot.c @@ -19,6 +19,11 @@ #define SYSCR_VAL 0x10 #endif +/* + * Delay min 5 SCLK cycles using worst case CCLK/SCLK ratio (15) + */ +#define SWRST_DELAY (5 * 15) + /* A system soft reset makes external memory unusable * so force this function into L1. */ @@ -34,11 +39,15 @@ void bfin_reset(void) while (1) { /* initiate system soft reset with magic 0x7 */ bfin_write_SWRST(0x7); - bfin_read_SWRST(); - asm("ssync;"); + + /* Wait for System reset to actually reset, needs to be 5 SCLKs, */ + /* Assume CCLK / SCLK ratio is worst case (15), and use 5*15 */ + + asm("LSETUP(.Lfoo,.Lfoo) LC0 = %0\n .Lfoo: NOP;\n" + : : "a" (SWRST_DELAY) : "LC0", "LT0", "LB0"); + /* clear system soft reset */ bfin_write_SWRST(0); - bfin_read_SWRST(); asm("ssync;"); /* issue core reset */ asm("raise 1"); |