diff options
| author | J Keerthy <j-keerthy@ti.com> | 2013-07-23 12:05:40 +0530 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-01-17 12:36:31 -0800 |
| commit | a0289f917402a08b049b818ffba638cb16994315 (patch) | |
| tree | 12f3f765392d2460457e76d239eba4489443877b /arch | |
| parent | c3be7acdeb5ce5bc857ee47664b0be36241e2402 (diff) | |
ARM: dts: DRA7: Add PCIe related clock nodes
This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk
which are used by PCIe phy. It also adds a mux clock to choose
the source of optfclk_pciephy_div_clk clock.
Signed-off-by: J Keerthy <j-keerthy@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/dra7xx-clocks.dtsi | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index d616359baed..e96da9a898a 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,6 +1165,31 @@ reg = <0x021c>, <0x0220>; }; + optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { + compatible = "ti,divider-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x021c>; + ti,bit-shift = <8>; + ti,max-div = <2>; + }; + + optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&apll_pcie_ck>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <9>; + }; + + optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { + compatible = "ti,gate-clock"; + clocks = <&optfclk_pciephy_div>; + #clock-cells = <0>; + reg = <0x13b0>; + ti,bit-shift = <10>; + }; + apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { #clock-cells = <0>; compatible = "fixed-factor-clock"; |