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authorBaruch Siach <baruch@tkos.co.il>2010-06-10 12:14:32 +0300
committerSascha Hauer <s.hauer@pengutronix.de>2010-07-26 14:18:18 +0200
commitac0eb0f3ca3e3fff6ac083ee3a51b98f87d67843 (patch)
treec84fb2892d3b543892d1da2eac2b2d7d3030ecf9 /arch
parentfd3c46b3062ac1ce0aa532c81922f9a0e28a6454 (diff)
mx25: add a comment documenting undocumented IPG clocks
The information in the i.MX25 Reference Manual is lacking. Add information from the Freescale BSP. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Acked-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-mx25/clock.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 74cf27d48bf..2bb4f1d73cb 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -179,6 +179,28 @@ static void clk_cgcr_disable(struct clk *clk)
.secondary = s, \
}
+/*
+ * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
+ * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
+ * taken from the Freescale released BSP.
+ *
+ * bit reg offset clock
+ *
+ * 0 CGCR1 0 AUDMUX
+ * 12 CGCR1 12 ESAI
+ * 16 CGCR1 16 GPIO1
+ * 17 CGCR1 17 GPIO2
+ * 18 CGCR1 18 GPIO3
+ * 23 CGCR1 23 I2C1
+ * 24 CGCR1 24 I2C2
+ * 25 CGCR1 25 I2C3
+ * 27 CGCR1 27 IOMUXC
+ * 28 CGCR1 28 KPP
+ * 30 CGCR1 30 OWIRE
+ * 36 CGCR2 4 RTIC
+ * 51 CGCR2 19 WDOG
+ */
+
DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);