diff options
| author | Greg Ungerer <gerg@uclinux.org> | 2011-07-04 15:30:55 +1000 |
|---|---|---|
| committer | Greg Ungerer <gerg@uclinux.org> | 2011-07-25 11:20:41 +1000 |
| commit | 35de674982aa13de98cf470c640895164017563e (patch) | |
| tree | d4223dbd6880b9fcb04a4755e2daf63b97e389b4 /arch | |
| parent | f3c23a28ace0a42ea06b5860b3bd25f71fc14c89 (diff) | |
m68k: fix some atomic operation asm address modes for ColdFire
The ColdFire processors have a much more limited set of addressing modes
that can be used for most instructions. A number of the atomic operations
have already been fixed to limit the addressing modes used with add and
sub instructions when building for ColdFire. But we missed a few.
Fix the remaining atomic operations to be clean for ColdFire processors.
Signed-off-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/m68k/include/asm/atomic.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/m68k/include/asm/atomic.h b/arch/m68k/include/asm/atomic.h index 03ae3d14cd4..307a573881a 100644 --- a/arch/m68k/include/asm/atomic.h +++ b/arch/m68k/include/asm/atomic.h @@ -169,18 +169,18 @@ static inline int atomic_add_negative(int i, atomic_t *v) char c; __asm__ __volatile__("addl %2,%1; smi %0" : "=d" (c), "+m" (*v) - : "id" (i)); + : ASM_DI (i)); return c != 0; } static inline void atomic_clear_mask(unsigned long mask, unsigned long *v) { - __asm__ __volatile__("andl %1,%0" : "+m" (*v) : "id" (~(mask))); + __asm__ __volatile__("andl %1,%0" : "+m" (*v) : ASM_DI (~(mask))); } static inline void atomic_set_mask(unsigned long mask, unsigned long *v) { - __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask)); + __asm__ __volatile__("orl %1,%0" : "+m" (*v) : ASM_DI (mask)); } static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) |