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authorNicos Gollan <gtdev@spearhead.de>2011-05-05 21:00:37 +0200
committerGreg Kroah-Hartman <gregkh@suse.de>2011-06-07 09:35:21 -0700
commit7808edcd306f22aeb23775d34e70b7fa2f58b852 (patch)
treeb477dbde7a82a42940a2d5634571d3b1b8626a45 /block/blk-iopoll.c
parent59c5f46fbe01a00eedf54a23789634438bb80603 (diff)
Basic support for Moschip 9900 family I/O chips
Add I/O based support for serial and parallel ports of the following chips: Vendor: Moschip (0x9710) Parts (device IDs) * 9900 (0x9900) * 9904 (0x9904 * 9901 (0x9912, also sold as 9912) * 9922 (0x9922) On all chips but the 9900, a single port is provided per PCI subdevice (subvendor-ID 0xA000, subdevice-IDs 0x1000 for serial, 0x2000 for parallel with proper class codes). In cascading configurations, the 9900 provides two devices per subdevice, with subvendor-ID 0xA000 and subdevice-IDs 0x30ps where p is the number of parallel ports and s the number of serial ports. Basic testing was only done on the serial part of a 9912 to the point where it can be used for a serial kernel console, and advanced features are completely untested. It is possible to reduce functionality of the chips by adding a configuration EEPROM, and the datasheet [1] is inconsistent w.r.t subdevices in the 4s+2s1p and 2s1p+4s configurations. The subdevice-ID 0x3012 should likely read 0x3011 with a serial port in function 3, which would be consistent with the BAR layouts. For now, the drivers ignore subdevices with ID 0x1000 and no class code. The parallel ports are integrated in parport_serial even for purely parallel parts to reduce the footprint of the patch. [1] http://www.moschip.com/data/products/MCS9900/MCS9900_Datasheet.pdf Signed-off-by: Nicos Gollan <gtdev@spearhead.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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