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authorCatalin Marinas <catalin.marinas@arm.com>2012-03-05 11:49:32 +0000
committerCatalin Marinas <catalin.marinas@arm.com>2012-09-17 13:42:13 +0100
commit53631b54c8704fe5de435582c82ddbc0bfabf06a (patch)
tree3bca49152b4e2eeaf7a96f2405ed963ce17da1e5 /block
parent3dd681d944f6d861f12ee03aff17a14342963330 (diff)
arm64: Floating point and SIMD
This patch adds support for FP/ASIMD register bank saving and restoring during context switch and FP exception handling to generate SIGFPE. There are 32 128-bit registers and the context switching is currently done non-lazily. Benchmarks on real hardware are required before implementing lazy FP state saving/restoring. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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