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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-29 15:09:57 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-29 15:09:57 +0100
commit22b1908610dd7ff68471cd4fbd383dbdfe5e0ecd (patch)
tree696d910ef791433a6a6bbd30ae841a106ce78a88 /block
parent264edb35ce5c85749bfdd2942c74b786ea1cde41 (diff)
[ARM] nommu: provide a way for correct control register value selection
Most MMU-based CPUs have a restriction on the setting of the data cache enable and mmu enable bits in the control register, whereby if the data cache is enabled, the MMU must also be enabled. Enabling the data cache without the MMU is an invalid combination. However, there are CPUs where the data cache can be enabled without the MMU. In order to allow these CPUs to take advantage of that, provide a method whereby each proc-*.S file defines the control regsiter value for use with nommu (with the MMU disabled.) Later on, when we add support for enabling the MMU on these devices, we can adjust the "crval" macro to also enable the data cache for nommu. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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