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authorMagnus Damm <damm@igel.co.jp>2007-07-18 17:25:09 +0900
committerPaul Mundt <lethal@linux-sh.org>2007-07-20 12:18:20 +0900
commit02ab3f70791f7d5c9098acaa31a72dd7d0961cb0 (patch)
treeb95f0ec8cc57ed2166eb28e53bb604374e6f0f44 /crypto/md5.c
parent53aba19f82045c1df838570b8484043e93c4442a (diff)
sh: intc - shared IPR and INTC2 controller
This is the second version of the shared interrupt controller patch for the sh architecture, fixing up handling of intc_reg_fns[]. The three main advantages with this controller over the existing ones are: - Both priority (ipr) and bitmap (intc2) registers are supported - External pin sense configuration is supported, ie edge vs level triggered - CPU/Board specific code maps 1:1 with datasheet for easy verification This controller can easily coexist with the current IPR and INTC2 controllers, but the idea is that CPUs/Boards should be moved over to this controller over time so we have a single code base to maintain. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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