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authorAnson Huang <b20788@freescale.com>2013-01-31 11:23:53 -0500
committerMark Brown <broonie@opensource.wolfsonmicro.com>2013-01-31 14:40:49 +0800
commit9ee417c07479b9a87d0808dd3c8b4ce3925983f1 (patch)
tree639728c1c15217843d2d4641cdf13c5146d39aa8 /crypto/rng.c
parent949db153b6466c6f7cad5a427ecea94985927311 (diff)
regulators: anatop: add set_voltage_time_sel interface
some of anatop's regulators(cpu, vddpu and vddsoc) have register settings about LDO's step time, which will impact the LDO ramp up speed, need to use set_voltage_time_sel interface to add necessary delay everytime LDOs' voltage is increased. offset 0x170: bit [24-25]: cpu bit [26-27]: vddpu bit [28-29]: vddsoc field definition: 0'b00: 64 cycles of 24M clock; 0'b01: 128 cycles of 24M clock; 0'b02: 256 cycles of 24M clock; 0'b03: 512 cycles of 24M clock; Signed-off-by: Anson Huang <b20788@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Diffstat (limited to 'crypto/rng.c')
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