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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2008-12-18 19:13:54 +0000
committerPaul Mackerras <paulus@samba.org>2008-12-21 14:21:16 +1100
commit9dce3ce5c55c848f00429005a46fd6246cfabfbe (patch)
treed70f72b77732c582adfaddfadc658bb461a79d14 /crypto
parent64b3d0e8122b422e879b23d42f9e0e8efbbf9744 (diff)
powerpc/44x: 44x TLB doesn't need "Guarded" set for all pages
After discussing with chip designers, it appears that it's not necessary to set G everywhere on 440 cores. The various core errata related to prefetch should be sorted out by firmware by disabling icache prefetching in CCR0. We add the workaround to the kernel however just in case oooold firmwares don't do it. This is valid for -all- 4xx core variants. Later ones hard wire the absence of prefetch but it doesn't harm to clear the bits in CCR0 (they should already be cleared anyway). We still leave G=1 on the linear mapping for now, we need to stop over-mapping RAM to be able to remove it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Josh Boyer <jwboyer@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions