diff options
| author | Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> | 2006-01-11 22:44:21 +0100 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-01-11 19:04:54 -0800 |
| commit | 6eb0a0fd059598ee0d49c6283ce25cccd743e9fc (patch) | |
| tree | a608f92e3b8a94cba89e94786169897c64629580 /drivers/acpi/processor_idle.c | |
| parent | 5a07a30c3cc4dc438494d6416ffa74008a2194b3 (diff) | |
[PATCH] i386: Handle missing local APIC timer interrupts on C3 state
Whenever we see that a CPU is capable of C3 (during ACPI cstate init), we
disable local APIC timer and switch to using a broadcast from external timer
interrupt (IRQ 0). This is needed because Intel CPUs stop the local
APIC timer in C3. This is currently only enabled for Intel CPUs.
Patch below adds the code for i386 and also the ACPI hunk.
Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/acpi/processor_idle.c')
| -rw-r--r-- | drivers/acpi/processor_idle.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c index 807b0df308f..cc049338e41 100644 --- a/drivers/acpi/processor_idle.c +++ b/drivers/acpi/processor_idle.c @@ -843,6 +843,15 @@ static int acpi_processor_power_verify(struct acpi_processor *pr) unsigned int i; unsigned int working = 0; +#ifdef ARCH_APICTIMER_STOPS_ON_C3 + struct cpuinfo_x86 *c = cpu_data + pr->id; + cpumask_t mask = cpumask_of_cpu(pr->id); + + if (c->x86_vendor == X86_VENDOR_INTEL) { + on_each_cpu(switch_ipi_to_APIC_timer, &mask, 1, 1); + } +#endif + for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) { struct acpi_processor_cx *cx = &pr->power.states[i]; @@ -857,6 +866,12 @@ static int acpi_processor_power_verify(struct acpi_processor *pr) case ACPI_STATE_C3: acpi_processor_power_verify_c3(pr, cx); +#ifdef ARCH_APICTIMER_STOPS_ON_C3 + if (c->x86_vendor == X86_VENDOR_INTEL) { + on_each_cpu(switch_APIC_timer_to_ipi, + &mask, 1, 1); + } +#endif break; } |