diff options
| author | Colin Tuckley <colin.tuckley@arm.com> | 2010-06-04 16:19:51 +0200 |
|---|---|---|
| committer | Jeff Garzik <jgarzik@redhat.com> | 2010-06-07 16:03:13 -0400 |
| commit | 7a4f876b876afb13856a79a0402f71b9dfbe86a8 (patch) | |
| tree | b0b4cad190e8406eb11513b3205552c7a5e3f256 /drivers/ata/sata_sil24.c | |
| parent | 4daedcfe8c6851aa01cc1997220f2577f4039c13 (diff) | |
sata_sil24: fix kernel panic on ARM caused by unaligned access in sata_sil24
The sata_sil24 driver has six 16-bit registers that are initialised with
32-bit writes. This cause a kernel panic on ARM due to the unaligned
accesses which result.
This patch changes the accesses to the correct 16-bit ones.
Signed-off-by: Colin Tuckley <colin.tuckley@arm.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/ata/sata_sil24.c')
| -rw-r--r-- | drivers/ata/sata_sil24.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/ata/sata_sil24.c b/drivers/ata/sata_sil24.c index e9250514734..70b58fe9e5b 100644 --- a/drivers/ata/sata_sil24.c +++ b/drivers/ata/sata_sil24.c @@ -539,12 +539,12 @@ static void sil24_config_port(struct ata_port *ap) writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); /* zero error counters. */ - writel(0x8000, port + PORT_DECODE_ERR_THRESH); - writel(0x8000, port + PORT_CRC_ERR_THRESH); - writel(0x8000, port + PORT_HSHK_ERR_THRESH); - writel(0x0000, port + PORT_DECODE_ERR_CNT); - writel(0x0000, port + PORT_CRC_ERR_CNT); - writel(0x0000, port + PORT_HSHK_ERR_CNT); + writew(0x8000, port + PORT_DECODE_ERR_THRESH); + writew(0x8000, port + PORT_CRC_ERR_THRESH); + writew(0x8000, port + PORT_HSHK_ERR_THRESH); + writew(0x0000, port + PORT_DECODE_ERR_CNT); + writew(0x0000, port + PORT_CRC_ERR_CNT); + writew(0x0000, port + PORT_HSHK_ERR_CNT); /* always use 64bit activation */ writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); |